pwm: sifive: Ensure the clk is enabled exactly once per running PWM

.apply() assumes the clk to be for a given PWM iff the PWM is enabled.
So make sure this is the case when .probe() completes. And in .remove()
disable the according number of times.

This fixes a clk enable/disable imbalance, if some PWMs are already running
at probe time.

Fixes: 9e37a53eb051 (pwm: sifive: Add a driver for SiFive SoC PWM)
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Tested-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>

diff --git a/drivers/pwm/pwm-sifive.c b/drivers/pwm/pwm-sifive.c
index 34d23d56fa254800779c0bcb6156ea97649d588e..da40ade0ebdf7db010c7c6728606a5a1d6d5af81 100644 (file)
--- a/drivers/pwm/pwm-sifive.c
+++ b/drivers/pwm/pwm-sifive.c
@@ -216,6 +216,8 @@ static int pwm_sifive_probe(struct platform_device *pdev)
        struct pwm_sifive_ddata *ddata;
        struct pwm_chip *chip;
        int ret;
+       u32 val;
+       unsigned int enabled_pwms = 0, enabled_clks = 1;
 
        ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
        if (!ddata)
@@ -242,6 +244,33 @@ static int pwm_sifive_probe(struct platform_device *pdev)
                return ret;
        }
 
+       val = readl(ddata->regs + PWM_SIFIVE_PWMCFG);
+       if (val & PWM_SIFIVE_PWMCFG_EN_ALWAYS) {
+               unsigned int i;
+
+               for (i = 0; i < chip->npwm; ++i) {
+                       val = readl(ddata->regs + PWM_SIFIVE_PWMCMP(i));
+                       if (val > 0)
+                               ++enabled_pwms;
+               }
+       }
+
+       /* The clk should be on once for each running PWM. */
+       if (enabled_pwms) {
+               while (enabled_clks < enabled_pwms) {
+                       /* This is not expected to fail as the clk is already on */
+                       ret = clk_enable(ddata->clk);
+                       if (unlikely(ret)) {
+                               dev_err_probe(dev, ret, "Failed to enable clk\n");
+                               goto disable_clk;
+                       }
+                       ++enabled_clks;
+               }
+       } else {
+               clk_disable(ddata->clk);
+               enabled_clks = 0;
+       }
+
        /* Watch for changes to underlying clock frequency */
        ddata->notifier.notifier_call = pwm_sifive_clock_notifier;
        ret = clk_notifier_register(ddata->clk, &ddata->notifier);
@@ -264,7 +293,11 @@ static int pwm_sifive_probe(struct platform_device *pdev)
 unregister_clk:
        clk_notifier_unregister(ddata->clk, &ddata->notifier);
 disable_clk:
-       clk_disable_unprepare(ddata->clk);
+       while (enabled_clks) {
+               clk_disable(ddata->clk);
+               --enabled_clks;
+       }
+       clk_unprepare(ddata->clk);
 
        return ret;
 }
@@ -272,21 +305,16 @@ disable_clk:
 static int pwm_sifive_remove(struct platform_device *dev)
 {
        struct pwm_sifive_ddata *ddata = platform_get_drvdata(dev);
-       bool is_enabled = false;
        struct pwm_device *pwm;
        int ch;
 
        for (ch = 0; ch < ddata->chip.npwm; ch++) {
                pwm = &ddata->chip.pwms[ch];
-               if (pwm->state.enabled) {
-                       is_enabled = true;
-                       break;
-               }
+               if (pwm->state.enabled)
+                       clk_disable(ddata->clk);
        }
-       if (is_enabled)
-               clk_disable(ddata->clk);
 
-       clk_disable_unprepare(ddata->clk);
+       clk_unprepare(ddata->clk);
        pwmchip_remove(&ddata->chip);
        clk_notifier_unregister(ddata->clk, &ddata->notifier);