mutex_lock(&d->lock);
 }
 
-static int regmap_irq_update_bits(struct regmap_irq_chip_data *d,
-                                 unsigned int reg, unsigned int mask,
-                                 unsigned int val)
-{
-       if (d->chip->mask_writeonly)
-               return regmap_write_bits(d->map, reg, mask, val);
-       else
-               return regmap_update_bits(d->map, reg, mask, val);
-}
-
 static void regmap_irq_sync_unlock(struct irq_data *data)
 {
        struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
 
                reg = sub_irq_reg(d, d->chip->mask_base, i);
                if (d->chip->mask_invert) {
-                       ret = regmap_irq_update_bits(d, reg,
+                       ret = regmap_update_bits(d->map, reg,
                                         d->mask_buf_def[i], ~d->mask_buf[i]);
                } else if (d->chip->unmask_base) {
                        /* set mask with mask_base register */
-                       ret = regmap_irq_update_bits(d, reg,
+                       ret = regmap_update_bits(d->map, reg,
                                        d->mask_buf_def[i], ~d->mask_buf[i]);
                        if (ret < 0)
                                dev_err(d->map->dev,
                        unmask_offset = d->chip->unmask_base -
                                                        d->chip->mask_base;
                        /* clear mask with unmask_base register */
-                       ret = regmap_irq_update_bits(d,
+                       ret = regmap_update_bits(d->map,
                                        reg + unmask_offset,
                                        d->mask_buf_def[i],
                                        d->mask_buf[i]);
                } else {
-                       ret = regmap_irq_update_bits(d, reg,
+                       ret = regmap_update_bits(d->map, reg,
                                         d->mask_buf_def[i], d->mask_buf[i]);
                }
                if (ret != 0)
                reg = sub_irq_reg(d, d->chip->mask_base, i);
 
                if (chip->mask_invert)
-                       ret = regmap_irq_update_bits(d, reg,
+                       ret = regmap_update_bits(d->map, reg,
                                         d->mask_buf[i], ~d->mask_buf[i]);
                else if (d->chip->unmask_base) {
                        unmask_offset = d->chip->unmask_base -
                                        d->chip->mask_base;
-                       ret = regmap_irq_update_bits(d,
+                       ret = regmap_update_bits(d->map,
                                        reg + unmask_offset,
                                        d->mask_buf[i],
                                        d->mask_buf[i]);
                } else
-                       ret = regmap_irq_update_bits(d, reg,
+                       ret = regmap_update_bits(d->map, reg,
                                         d->mask_buf[i], d->mask_buf[i]);
                if (ret != 0) {
                        dev_err(map->dev, "Failed to set masks in 0x%x: %d\n",
 
  *
  * @status_base: Base status register address.
  * @mask_base:   Base mask register address.
- * @mask_writeonly: Base mask register is write only.
  * @unmask_base:  Base unmask register address. for chips who have
  *                separate mask and unmask registers
  * @ack_base:    Base ack address. If zero then the chip is clear on read.
        unsigned int type_base;
        unsigned int *virt_reg_base;
        unsigned int irq_reg_stride;
-       unsigned int mask_writeonly:1;
        unsigned int init_ack_masked:1;
        unsigned int mask_invert:1;
        unsigned int use_ack:1;