Allow the name 'cpu_env' to be used for something else.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
TCGv_ptr udata = tcg_temp_ebb_new_ptr();
tcg_gen_movi_ptr(udata, 0);
- tcg_gen_ld_i32(cpu_index, cpu_env,
+ tcg_gen_ld_i32(cpu_index, tcg_env,
-offsetof(ArchCPU, env) + offsetof(CPUState, cpu_index));
gen_helper_plugin_vcpu_udata_cb(cpu_index, udata);
tcg_gen_movi_i32(meminfo, info);
tcg_gen_movi_ptr(udata, 0);
- tcg_gen_ld_i32(cpu_index, cpu_env,
+ tcg_gen_ld_i32(cpu_index, tcg_env,
-offsetof(ArchCPU, env) + offsetof(CPUState, cpu_index));
gen_helper_plugin_vcpu_mem_cb(cpu_index, meminfo, addr, udata);
TCGv_ptr ptr = tcg_temp_ebb_new_ptr();
tcg_gen_movi_ptr(ptr, 0);
- tcg_gen_st_ptr(ptr, cpu_env, offsetof(CPUState, plugin_mem_cbs) -
+ tcg_gen_st_ptr(ptr, tcg_env, offsetof(CPUState, plugin_mem_cbs) -
offsetof(ArchCPU, env));
tcg_temp_free_ptr(ptr);
}
if (!tcg_ctx->plugin_tb->mem_helper) {
return;
}
- tcg_gen_st_ptr(tcg_constant_ptr(NULL), cpu_env,
+ tcg_gen_st_ptr(tcg_constant_ptr(NULL), tcg_env,
offsetof(CPUState, plugin_mem_cbs) - offsetof(ArchCPU, env));
}
db->saved_can_do_io = val;
QEMU_BUILD_BUG_ON(sizeof_field(CPUState, neg.can_do_io) != 1);
- tcg_gen_st8_i32(tcg_constant_i32(val), cpu_env,
+ tcg_gen_st8_i32(tcg_constant_i32(val), tcg_env,
offsetof(ArchCPU, parent_obj.neg.can_do_io) -
offsetof(ArchCPU, env));
}
if ((cflags & CF_USE_ICOUNT) || !(cflags & CF_NOIRQ)) {
count = tcg_temp_new_i32();
- tcg_gen_ld_i32(count, cpu_env,
+ tcg_gen_ld_i32(count, tcg_env,
offsetof(ArchCPU, parent_obj.neg.icount_decr.u32)
- offsetof(ArchCPU, env));
}
}
if (cflags & CF_USE_ICOUNT) {
- tcg_gen_st16_i32(count, cpu_env,
+ tcg_gen_st16_i32(count, tcg_env,
offsetof(ArchCPU, parent_obj.neg.icount_decr.u16.low)
- offsetof(ArchCPU, env));
}
extern __thread TCGContext *tcg_ctx;
extern const void *tcg_code_gen_epilogue;
extern uintptr_t tcg_splitwx_diff;
-extern TCGv_env cpu_env;
+extern TCGv_env tcg_env;
bool in_code_gen_buffer(const void *p);
int i;
for (i = 0; i < 31; i++) {
- cpu_std_ir[i] = tcg_global_mem_new_i64(cpu_env,
+ cpu_std_ir[i] = tcg_global_mem_new_i64(tcg_env,
offsetof(CPUAlphaState, ir[i]),
greg_names[i]);
}
for (i = 0; i < 31; i++) {
- cpu_fir[i] = tcg_global_mem_new_i64(cpu_env,
+ cpu_fir[i] = tcg_global_mem_new_i64(tcg_env,
offsetof(CPUAlphaState, fir[i]),
freg_names[i]);
}
memcpy(cpu_pal_ir, cpu_std_ir, sizeof(cpu_pal_ir));
for (i = 0; i < 8; i++) {
int r = (i == 7 ? 25 : i + 8);
- cpu_pal_ir[r] = tcg_global_mem_new_i64(cpu_env,
+ cpu_pal_ir[r] = tcg_global_mem_new_i64(tcg_env,
offsetof(CPUAlphaState,
shadow[i]),
shadow_names[i]);
for (i = 0; i < ARRAY_SIZE(vars); ++i) {
const GlobalVar *v = &vars[i];
- *v->var = tcg_global_mem_new_i64(cpu_env, v->ofs, v->name);
+ *v->var = tcg_global_mem_new_i64(tcg_env, v->ofs, v->name);
}
}
static void ld_flag_byte(TCGv val, unsigned shift)
{
- tcg_gen_ld8u_i64(val, cpu_env, get_flag_ofs(shift));
+ tcg_gen_ld8u_i64(val, tcg_env, get_flag_ofs(shift));
}
static void st_flag_byte(TCGv val, unsigned shift)
{
- tcg_gen_st8_i64(val, cpu_env, get_flag_ofs(shift));
+ tcg_gen_st8_i64(val, tcg_env, get_flag_ofs(shift));
}
static void gen_excp_1(int exception, int error_code)
tmp1 = tcg_constant_i32(exception);
tmp2 = tcg_constant_i32(error_code);
- gen_helper_excp(cpu_env, tmp1, tmp2);
+ gen_helper_excp(tcg_env, tmp1, tmp2);
}
static DisasJumpType gen_excp(DisasContext *ctx, int exception, int error_code)
tcg_gen_movi_i32(tmp, float_round_down);
break;
case QUAL_RM_D:
- tcg_gen_ld8u_i32(tmp, cpu_env,
+ tcg_gen_ld8u_i32(tmp, tcg_env,
offsetof(CPUAlphaState, fpcr_dyn_round));
break;
}
/* ??? The "fpu/softfloat.h" interface is to call set_float_rounding_mode.
With CONFIG_SOFTFLOAT that expands to an out-of-line call that just
sets the one field. */
- tcg_gen_st8_i32(tmp, cpu_env,
+ tcg_gen_st8_i32(tmp, tcg_env,
offsetof(CPUAlphaState, fp_status.float_rounding_mode));
#else
gen_helper_setroundmode(tmp);
tmp = tcg_temp_new_i32();
if (fn11) {
/* Underflow is enabled, use the FPCR setting. */
- tcg_gen_ld8u_i32(tmp, cpu_env,
+ tcg_gen_ld8u_i32(tmp, tcg_env,
offsetof(CPUAlphaState, fpcr_flush_to_zero));
} else {
/* Underflow is disabled, force flush-to-zero. */
}
#if defined(CONFIG_SOFTFLOAT_INLINE)
- tcg_gen_st8_i32(tmp, cpu_env,
+ tcg_gen_st8_i32(tmp, tcg_env,
offsetof(CPUAlphaState, fp_status.flush_to_zero));
#else
gen_helper_setflushzero(tmp);
val = cpu_fir[reg];
if ((fn11 & QUAL_S) == 0) {
if (is_cmp) {
- gen_helper_ieee_input_cmp(cpu_env, val);
+ gen_helper_ieee_input_cmp(tcg_env, val);
} else {
- gen_helper_ieee_input(cpu_env, val);
+ gen_helper_ieee_input(tcg_env, val);
}
} else {
#ifndef CONFIG_USER_ONLY
/* In system mode, raise exceptions for denormals like real
hardware. In user mode, proceed as if the OS completion
handler is handling the denormal as per spec. */
- gen_helper_ieee_input_s(cpu_env, val);
+ gen_helper_ieee_input_s(tcg_env, val);
#endif
}
}
or if we were to do something clever with imprecise exceptions. */
reg = tcg_constant_i32(rc + 32);
if (fn11 & QUAL_S) {
- gen_helper_fp_exc_raise_s(cpu_env, ign, reg);
+ gen_helper_fp_exc_raise_s(tcg_env, ign, reg);
} else {
- gen_helper_fp_exc_raise(cpu_env, ign, reg);
+ gen_helper_fp_exc_raise(tcg_env, ign, reg);
}
}
gen_qual_flushzero(ctx, fn11);
vb = gen_ieee_input(ctx, rb, fn11, 0);
- helper(dest_fpr(ctx, rc), cpu_env, vb);
+ helper(dest_fpr(ctx, rc), tcg_env, vb);
gen_fp_exc_raise(rc, fn11);
}
/* Almost all integer conversions use cropped rounding;
special case that. */
if ((fn11 & QUAL_RM_MASK) == QUAL_RM_C) {
- gen_helper_cvttq_c(vc, cpu_env, vb);
+ gen_helper_cvttq_c(vc, tcg_env, vb);
} else {
gen_qual_roundmode(ctx, fn11);
- gen_helper_cvttq(vc, cpu_env, vb);
+ gen_helper_cvttq(vc, tcg_env, vb);
}
gen_fp_exc_raise(rc, fn11);
}
is inexact. Thus we only need to worry about exceptions when
inexact handling is requested. */
if (fn11 & QUAL_I) {
- helper(vc, cpu_env, vb);
+ helper(vc, tcg_env, vb);
gen_fp_exc_raise(rc, fn11);
} else {
- helper(vc, cpu_env, vb);
+ helper(vc, tcg_env, vb);
}
}
va = gen_ieee_input(ctx, ra, fn11, 0);
vb = gen_ieee_input(ctx, rb, fn11, 0);
vc = dest_fpr(ctx, rc);
- helper(vc, cpu_env, va, vb);
+ helper(vc, tcg_env, va, vb);
gen_fp_exc_raise(rc, fn11);
}
va = gen_ieee_input(ctx, ra, fn11, 1);
vb = gen_ieee_input(ctx, rb, fn11, 1);
vc = dest_fpr(ctx, rc);
- helper(vc, cpu_env, va, vb);
+ helper(vc, tcg_env, va, vb);
gen_fp_exc_raise(rc, fn11);
}
break;
case 0x9E:
/* RDUNIQUE */
- tcg_gen_ld_i64(ctx->ir[IR_V0], cpu_env,
+ tcg_gen_ld_i64(ctx->ir[IR_V0], tcg_env,
offsetof(CPUAlphaState, unique));
break;
case 0x9F:
/* WRUNIQUE */
- tcg_gen_st_i64(ctx->ir[IR_A0], cpu_env,
+ tcg_gen_st_i64(ctx->ir[IR_A0], tcg_env,
offsetof(CPUAlphaState, unique));
break;
default:
break;
case 0x2D:
/* WRVPTPTR */
- tcg_gen_st_i64(ctx->ir[IR_A0], cpu_env,
+ tcg_gen_st_i64(ctx->ir[IR_A0], tcg_env,
offsetof(CPUAlphaState, vptptr));
break;
case 0x31:
/* WRVAL */
- tcg_gen_st_i64(ctx->ir[IR_A0], cpu_env,
+ tcg_gen_st_i64(ctx->ir[IR_A0], tcg_env,
offsetof(CPUAlphaState, sysval));
break;
case 0x32:
/* RDVAL */
- tcg_gen_ld_i64(ctx->ir[IR_V0], cpu_env,
+ tcg_gen_ld_i64(ctx->ir[IR_V0], tcg_env,
offsetof(CPUAlphaState, sysval));
break;
case 0x38:
/* WRUSP */
- tcg_gen_st_i64(ctx->ir[IR_A0], cpu_env,
+ tcg_gen_st_i64(ctx->ir[IR_A0], tcg_env,
offsetof(CPUAlphaState, usp));
break;
case 0x3A:
/* RDUSP */
- tcg_gen_ld_i64(ctx->ir[IR_V0], cpu_env,
+ tcg_gen_ld_i64(ctx->ir[IR_V0], tcg_env,
offsetof(CPUAlphaState, usp));
break;
case 0x3C:
/* WHAMI */
- tcg_gen_ld32s_i64(ctx->ir[IR_V0], cpu_env,
+ tcg_gen_ld32s_i64(ctx->ir[IR_V0], tcg_env,
-offsetof(AlphaCPU, env) + offsetof(CPUState, cpu_index));
break;
case 0x3E:
/* WTINT */
- tcg_gen_st_i32(tcg_constant_i32(1), cpu_env,
+ tcg_gen_st_i32(tcg_constant_i32(1), tcg_env,
-offsetof(AlphaCPU, env) +
offsetof(CPUState, halted));
tcg_gen_movi_i64(ctx->ir[IR_V0], 0);
}
tcg_gen_movi_i64(tmp, exc_addr);
- tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUAlphaState, exc_addr));
+ tcg_gen_st_i64(tmp, tcg_env, offsetof(CPUAlphaState, exc_addr));
entry += (palcode & 0x80
? 0x2000 + (palcode - 0x80) * 64
if (data == 0) {
tcg_gen_movi_i64(va, 0);
} else if (data & PR_LONG) {
- tcg_gen_ld32s_i64(va, cpu_env, data & ~PR_LONG);
+ tcg_gen_ld32s_i64(va, tcg_env, data & ~PR_LONG);
} else {
- tcg_gen_ld_i64(va, cpu_env, data);
+ tcg_gen_ld_i64(va, tcg_env, data);
}
break;
}
switch (regno) {
case 255:
/* TBIA */
- gen_helper_tbia(cpu_env);
+ gen_helper_tbia(tcg_env);
break;
case 254:
/* TBIS */
- gen_helper_tbis(cpu_env, vb);
+ gen_helper_tbis(tcg_env, vb);
break;
case 253:
/* WAIT */
- tcg_gen_st_i32(tcg_constant_i32(1), cpu_env,
+ tcg_gen_st_i32(tcg_constant_i32(1), tcg_env,
-offsetof(AlphaCPU, env) + offsetof(CPUState, halted));
return gen_excp(ctx, EXCP_HALTED, 0);
if (translator_io_start(&ctx->base)) {
ret = DISAS_PC_STALE;
}
- gen_helper_set_alarm(cpu_env, vb);
+ gen_helper_set_alarm(tcg_env, vb);
break;
case 7:
/* PALBR */
- tcg_gen_st_i64(vb, cpu_env, offsetof(CPUAlphaState, palbr));
+ tcg_gen_st_i64(vb, tcg_env, offsetof(CPUAlphaState, palbr));
/* Changing the PAL base register implies un-chaining all of the TBs
that ended with a CALL_PAL. Since the base register usually only
changes during boot, flushing everything works well. */
- gen_helper_tb_flush(cpu_env);
+ gen_helper_tb_flush(tcg_env);
return DISAS_PC_STALE;
case 32 ... 39:
data = cpu_pr_data(regno);
if (data != 0) {
if (data & PR_LONG) {
- tcg_gen_st32_i64(vb, cpu_env, data & ~PR_LONG);
+ tcg_gen_st32_i64(vb, tcg_env, data & ~PR_LONG);
} else {
- tcg_gen_st_i64(vb, cpu_env, data);
+ tcg_gen_st_i64(vb, tcg_env, data);
}
}
break;
tcg_gen_ext32s_i64(vc, vb);
tcg_gen_add_i64(tmp, tmp, vc);
tcg_gen_ext32s_i64(vc, tmp);
- gen_helper_check_overflow(cpu_env, vc, tmp);
+ gen_helper_check_overflow(tcg_env, vc, tmp);
break;
case 0x49:
/* SUBL/V */
tcg_gen_ext32s_i64(vc, vb);
tcg_gen_sub_i64(tmp, tmp, vc);
tcg_gen_ext32s_i64(vc, tmp);
- gen_helper_check_overflow(cpu_env, vc, tmp);
+ gen_helper_check_overflow(tcg_env, vc, tmp);
break;
case 0x4D:
/* CMPLT */
tcg_gen_and_i64(tmp, tmp, tmp2);
tcg_gen_shri_i64(tmp, tmp, 63);
tcg_gen_movi_i64(tmp2, 0);
- gen_helper_check_overflow(cpu_env, tmp, tmp2);
+ gen_helper_check_overflow(tcg_env, tmp, tmp2);
break;
case 0x69:
/* SUBQ/V */
tcg_gen_and_i64(tmp, tmp, tmp2);
tcg_gen_shri_i64(tmp, tmp, 63);
tcg_gen_movi_i64(tmp2, 0);
- gen_helper_check_overflow(cpu_env, tmp, tmp2);
+ gen_helper_check_overflow(tcg_env, tmp, tmp2);
break;
case 0x6D:
/* CMPLE */
tcg_gen_ext32s_i64(vc, vb);
tcg_gen_mul_i64(tmp, tmp, vc);
tcg_gen_ext32s_i64(vc, tmp);
- gen_helper_check_overflow(cpu_env, vc, tmp);
+ gen_helper_check_overflow(tcg_env, vc, tmp);
break;
case 0x60:
/* MULQ/V */
tmp2 = tcg_temp_new();
tcg_gen_muls2_i64(vc, tmp, va, vb);
tcg_gen_sari_i64(tmp2, vc, 63);
- gen_helper_check_overflow(cpu_env, tmp, tmp2);
+ gen_helper_check_overflow(tcg_env, tmp, tmp2);
break;
default:
goto invalid_opc;
REQUIRE_REG_31(ra);
REQUIRE_FEN;
vb = load_fpr(ctx, rb);
- gen_helper_sqrtf(vc, cpu_env, vb);
+ gen_helper_sqrtf(vc, tcg_env, vb);
break;
case 0x0B:
/* SQRTS */
REQUIRE_REG_31(ra);
REQUIRE_FEN;
vb = load_fpr(ctx, rb);
- gen_helper_sqrtg(vc, cpu_env, vb);
+ gen_helper_sqrtg(vc, tcg_env, vb);
break;
case 0x02B:
/* SQRTT */
case 0x00:
/* ADDF */
REQUIRE_FEN;
- gen_helper_addf(vc, cpu_env, va, vb);
+ gen_helper_addf(vc, tcg_env, va, vb);
break;
case 0x01:
/* SUBF */
REQUIRE_FEN;
- gen_helper_subf(vc, cpu_env, va, vb);
+ gen_helper_subf(vc, tcg_env, va, vb);
break;
case 0x02:
/* MULF */
REQUIRE_FEN;
- gen_helper_mulf(vc, cpu_env, va, vb);
+ gen_helper_mulf(vc, tcg_env, va, vb);
break;
case 0x03:
/* DIVF */
REQUIRE_FEN;
- gen_helper_divf(vc, cpu_env, va, vb);
+ gen_helper_divf(vc, tcg_env, va, vb);
break;
case 0x1E:
/* CVTDG -- TODO */
case 0x20:
/* ADDG */
REQUIRE_FEN;
- gen_helper_addg(vc, cpu_env, va, vb);
+ gen_helper_addg(vc, tcg_env, va, vb);
break;
case 0x21:
/* SUBG */
REQUIRE_FEN;
- gen_helper_subg(vc, cpu_env, va, vb);
+ gen_helper_subg(vc, tcg_env, va, vb);
break;
case 0x22:
/* MULG */
REQUIRE_FEN;
- gen_helper_mulg(vc, cpu_env, va, vb);
+ gen_helper_mulg(vc, tcg_env, va, vb);
break;
case 0x23:
/* DIVG */
REQUIRE_FEN;
- gen_helper_divg(vc, cpu_env, va, vb);
+ gen_helper_divg(vc, tcg_env, va, vb);
break;
case 0x25:
/* CMPGEQ */
REQUIRE_FEN;
- gen_helper_cmpgeq(vc, cpu_env, va, vb);
+ gen_helper_cmpgeq(vc, tcg_env, va, vb);
break;
case 0x26:
/* CMPGLT */
REQUIRE_FEN;
- gen_helper_cmpglt(vc, cpu_env, va, vb);
+ gen_helper_cmpglt(vc, tcg_env, va, vb);
break;
case 0x27:
/* CMPGLE */
REQUIRE_FEN;
- gen_helper_cmpgle(vc, cpu_env, va, vb);
+ gen_helper_cmpgle(vc, tcg_env, va, vb);
break;
case 0x2C:
/* CVTGF */
REQUIRE_REG_31(ra);
REQUIRE_FEN;
- gen_helper_cvtgf(vc, cpu_env, vb);
+ gen_helper_cvtgf(vc, tcg_env, vb);
break;
case 0x2D:
/* CVTGD -- TODO */
/* CVTGQ */
REQUIRE_REG_31(ra);
REQUIRE_FEN;
- gen_helper_cvtgq(vc, cpu_env, vb);
+ gen_helper_cvtgq(vc, tcg_env, vb);
break;
case 0x3C:
/* CVTQF */
REQUIRE_REG_31(ra);
REQUIRE_FEN;
- gen_helper_cvtqf(vc, cpu_env, vb);
+ gen_helper_cvtqf(vc, tcg_env, vb);
break;
case 0x3E:
/* CVTQG */
REQUIRE_REG_31(ra);
REQUIRE_FEN;
- gen_helper_cvtqg(vc, cpu_env, vb);
+ gen_helper_cvtqg(vc, tcg_env, vb);
break;
default:
goto invalid_opc;
/* MT_FPCR */
REQUIRE_FEN;
va = load_fpr(ctx, ra);
- gen_helper_store_fpcr(cpu_env, va);
+ gen_helper_store_fpcr(tcg_env, va);
if (ctx->tb_rm == QUAL_RM_D) {
/* Re-do the copy of the rounding mode to fp_status
the next time we use dynamic rounding. */
/* MF_FPCR */
REQUIRE_FEN;
va = dest_fpr(ctx, ra);
- gen_helper_load_fpcr(va, cpu_env);
+ gen_helper_load_fpcr(va, tcg_env);
break;
case 0x02A:
/* FCMOVEQ */
REQUIRE_FEN;
vc = dest_fpr(ctx, rc);
vb = load_fpr(ctx, rb);
- gen_helper_cvtql(vc, cpu_env, vb);
+ gen_helper_cvtql(vc, tcg_env, vb);
gen_fp_exc_raise(rc, fn11);
break;
default:
if (translator_io_start(&ctx->base)) {
ret = DISAS_PC_STALE;
}
- gen_helper_load_pcc(va, cpu_env);
+ gen_helper_load_pcc(va, tcg_env);
break;
case 0xE000:
/* RC */
address from EXC_ADDR. This turns out to be useful for our
emulation PALcode, so continue to accept it. */
vb = dest_sink(ctx);
- tcg_gen_ld_i64(vb, cpu_env, offsetof(CPUAlphaState, exc_addr));
+ tcg_gen_ld_i64(vb, tcg_env, offsetof(CPUAlphaState, exc_addr));
} else {
vb = load_gpr(ctx, rb);
}
static inline TCGv_i32 load_cpu_offset(int offset)
{
TCGv_i32 tmp = tcg_temp_new_i32();
- tcg_gen_ld_i32(tmp, cpu_env, offset);
+ tcg_gen_ld_i32(tmp, tcg_env, offset);
return tmp;
}
{
int i;
- cpu_pc = tcg_global_mem_new_i64(cpu_env,
+ cpu_pc = tcg_global_mem_new_i64(tcg_env,
offsetof(CPUARMState, pc),
"pc");
for (i = 0; i < 32; i++) {
- cpu_X[i] = tcg_global_mem_new_i64(cpu_env,
+ cpu_X[i] = tcg_global_mem_new_i64(tcg_env,
offsetof(CPUARMState, xregs[i]),
regnames[i]);
}
- cpu_exclusive_high = tcg_global_mem_new_i64(cpu_env,
+ cpu_exclusive_high = tcg_global_mem_new_i64(tcg_env,
offsetof(CPUARMState, exclusive_high), "exclusive_high");
}
static void set_btype_raw(int val)
{
- tcg_gen_st_i32(tcg_constant_i32(val), cpu_env,
+ tcg_gen_st_i32(tcg_constant_i32(val), tcg_env,
offsetof(CPUARMState, btype));
}
static void gen_probe_access(DisasContext *s, TCGv_i64 ptr,
MMUAccessType acc, int log2_size)
{
- gen_helper_probe_access(cpu_env, ptr,
+ gen_helper_probe_access(tcg_env, ptr,
tcg_constant_i32(acc),
tcg_constant_i32(get_mem_index(s)),
tcg_constant_i32(1 << log2_size));
desc = FIELD_DP32(desc, MTEDESC, SIZEM1, memop_size(memop) - 1);
ret = tcg_temp_new_i64();
- gen_helper_mte_check(ret, cpu_env, tcg_constant_i32(desc), addr);
+ gen_helper_mte_check(ret, tcg_env, tcg_constant_i32(desc), addr);
return ret;
}
desc = FIELD_DP32(desc, MTEDESC, SIZEM1, total_size - 1);
ret = tcg_temp_new_i64();
- gen_helper_mte_check(ret, cpu_env, tcg_constant_i32(desc), addr);
+ gen_helper_mte_check(ret, tcg_env, tcg_constant_i32(desc), addr);
return ret;
}
type = is_write ? MMU_DATA_STORE : MMU_DATA_LOAD,
mmu_idx = get_mem_index(s);
- gen_helper_unaligned_access(cpu_env, addr, tcg_constant_i32(type),
+ gen_helper_unaligned_access(tcg_env, addr, tcg_constant_i32(type),
tcg_constant_i32(mmu_idx));
gen_set_label(over_label);
static void gen_rebuild_hflags(DisasContext *s)
{
- gen_helper_rebuild_hflags_a64(cpu_env, tcg_constant_i32(s->current_el));
+ gen_helper_rebuild_hflags_a64(tcg_env, tcg_constant_i32(s->current_el));
}
static void gen_exception_internal(int excp)
{
assert(excp_is_internal(excp));
- gen_helper_exception_internal(cpu_env, tcg_constant_i32(excp));
+ gen_helper_exception_internal(tcg_env, tcg_constant_i32(excp));
}
static void gen_exception_internal_insn(DisasContext *s, int excp)
static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syndrome)
{
gen_a64_update_pc(s, 0);
- gen_helper_exception_bkpt_insn(cpu_env, tcg_constant_i32(syndrome));
+ gen_helper_exception_bkpt_insn(tcg_env, tcg_constant_i32(syndrome));
s->base.is_jmp = DISAS_NORETURN;
}
{
TCGv_i64 v = tcg_temp_new_i64();
- tcg_gen_ld_i64(v, cpu_env, fp_reg_offset(s, reg, MO_64));
+ tcg_gen_ld_i64(v, tcg_env, fp_reg_offset(s, reg, MO_64));
return v;
}
{
TCGv_i32 v = tcg_temp_new_i32();
- tcg_gen_ld_i32(v, cpu_env, fp_reg_offset(s, reg, MO_32));
+ tcg_gen_ld_i32(v, tcg_env, fp_reg_offset(s, reg, MO_32));
return v;
}
{
TCGv_i32 v = tcg_temp_new_i32();
- tcg_gen_ld16u_i32(v, cpu_env, fp_reg_offset(s, reg, MO_16));
+ tcg_gen_ld16u_i32(v, tcg_env, fp_reg_offset(s, reg, MO_16));
return v;
}
{
unsigned ofs = fp_reg_offset(s, reg, MO_64);
- tcg_gen_st_i64(v, cpu_env, ofs);
+ tcg_gen_st_i64(v, tcg_env, ofs);
clear_vec_high(s, false, reg);
}
{
TCGv_ptr qc_ptr = tcg_temp_new_ptr();
- tcg_gen_addi_ptr(qc_ptr, cpu_env, offsetof(CPUARMState, vfp.qc));
+ tcg_gen_addi_ptr(qc_ptr, tcg_env, offsetof(CPUARMState, vfp.qc));
tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd),
vec_full_reg_offset(s, rn),
vec_full_reg_offset(s, rm), qc_ptr,
/* This writes the bottom N bits of a 128 bit wide vector to memory */
TCGv_i64 tmplo = tcg_temp_new_i64();
- tcg_gen_ld_i64(tmplo, cpu_env, fp_reg_offset(s, srcidx, MO_64));
+ tcg_gen_ld_i64(tmplo, tcg_env, fp_reg_offset(s, srcidx, MO_64));
if ((mop & MO_SIZE) < MO_128) {
tcg_gen_qemu_st_i64(tmplo, tcg_addr, get_mem_index(s), mop);
TCGv_i64 tmphi = tcg_temp_new_i64();
TCGv_i128 t16 = tcg_temp_new_i128();
- tcg_gen_ld_i64(tmphi, cpu_env, fp_reg_hi_offset(s, srcidx));
+ tcg_gen_ld_i64(tmphi, tcg_env, fp_reg_hi_offset(s, srcidx));
tcg_gen_concat_i64_i128(t16, tmplo, tmphi);
tcg_gen_qemu_st_i128(t16, tcg_addr, get_mem_index(s), mop);
tcg_gen_extr_i128_i64(tmplo, tmphi, t16);
}
- tcg_gen_st_i64(tmplo, cpu_env, fp_reg_offset(s, destidx, MO_64));
+ tcg_gen_st_i64(tmplo, tcg_env, fp_reg_offset(s, destidx, MO_64));
if (tmphi) {
- tcg_gen_st_i64(tmphi, cpu_env, fp_reg_hi_offset(s, destidx));
+ tcg_gen_st_i64(tmphi, tcg_env, fp_reg_hi_offset(s, destidx));
}
clear_vec_high(s, tmphi != NULL, destidx);
}
int vect_off = vec_reg_offset(s, srcidx, element, memop & MO_SIZE);
switch ((unsigned)memop) {
case MO_8:
- tcg_gen_ld8u_i64(tcg_dest, cpu_env, vect_off);
+ tcg_gen_ld8u_i64(tcg_dest, tcg_env, vect_off);
break;
case MO_16:
- tcg_gen_ld16u_i64(tcg_dest, cpu_env, vect_off);
+ tcg_gen_ld16u_i64(tcg_dest, tcg_env, vect_off);
break;
case MO_32:
- tcg_gen_ld32u_i64(tcg_dest, cpu_env, vect_off);
+ tcg_gen_ld32u_i64(tcg_dest, tcg_env, vect_off);
break;
case MO_8|MO_SIGN:
- tcg_gen_ld8s_i64(tcg_dest, cpu_env, vect_off);
+ tcg_gen_ld8s_i64(tcg_dest, tcg_env, vect_off);
break;
case MO_16|MO_SIGN:
- tcg_gen_ld16s_i64(tcg_dest, cpu_env, vect_off);
+ tcg_gen_ld16s_i64(tcg_dest, tcg_env, vect_off);
break;
case MO_32|MO_SIGN:
- tcg_gen_ld32s_i64(tcg_dest, cpu_env, vect_off);
+ tcg_gen_ld32s_i64(tcg_dest, tcg_env, vect_off);
break;
case MO_64:
case MO_64|MO_SIGN:
- tcg_gen_ld_i64(tcg_dest, cpu_env, vect_off);
+ tcg_gen_ld_i64(tcg_dest, tcg_env, vect_off);
break;
default:
g_assert_not_reached();
int vect_off = vec_reg_offset(s, srcidx, element, memop & MO_SIZE);
switch (memop) {
case MO_8:
- tcg_gen_ld8u_i32(tcg_dest, cpu_env, vect_off);
+ tcg_gen_ld8u_i32(tcg_dest, tcg_env, vect_off);
break;
case MO_16:
- tcg_gen_ld16u_i32(tcg_dest, cpu_env, vect_off);
+ tcg_gen_ld16u_i32(tcg_dest, tcg_env, vect_off);
break;
case MO_8|MO_SIGN:
- tcg_gen_ld8s_i32(tcg_dest, cpu_env, vect_off);
+ tcg_gen_ld8s_i32(tcg_dest, tcg_env, vect_off);
break;
case MO_16|MO_SIGN:
- tcg_gen_ld16s_i32(tcg_dest, cpu_env, vect_off);
+ tcg_gen_ld16s_i32(tcg_dest, tcg_env, vect_off);
break;
case MO_32:
case MO_32|MO_SIGN:
- tcg_gen_ld_i32(tcg_dest, cpu_env, vect_off);
+ tcg_gen_ld_i32(tcg_dest, tcg_env, vect_off);
break;
default:
g_assert_not_reached();
int vect_off = vec_reg_offset(s, destidx, element, memop & MO_SIZE);
switch (memop) {
case MO_8:
- tcg_gen_st8_i64(tcg_src, cpu_env, vect_off);
+ tcg_gen_st8_i64(tcg_src, tcg_env, vect_off);
break;
case MO_16:
- tcg_gen_st16_i64(tcg_src, cpu_env, vect_off);
+ tcg_gen_st16_i64(tcg_src, tcg_env, vect_off);
break;
case MO_32:
- tcg_gen_st32_i64(tcg_src, cpu_env, vect_off);
+ tcg_gen_st32_i64(tcg_src, tcg_env, vect_off);
break;
case MO_64:
- tcg_gen_st_i64(tcg_src, cpu_env, vect_off);
+ tcg_gen_st_i64(tcg_src, tcg_env, vect_off);
break;
default:
g_assert_not_reached();
int vect_off = vec_reg_offset(s, destidx, element, memop & MO_SIZE);
switch (memop) {
case MO_8:
- tcg_gen_st8_i32(tcg_src, cpu_env, vect_off);
+ tcg_gen_st8_i32(tcg_src, tcg_env, vect_off);
break;
case MO_16:
- tcg_gen_st16_i32(tcg_src, cpu_env, vect_off);
+ tcg_gen_st16_i32(tcg_src, tcg_env, vect_off);
break;
case MO_32:
- tcg_gen_st_i32(tcg_src, cpu_env, vect_off);
+ tcg_gen_st_i32(tcg_src, tcg_env, vect_off);
break;
default:
g_assert_not_reached();
truedst = tcg_temp_new_i64();
if (use_key_a) {
- gen_helper_autia_combined(truedst, cpu_env, dst, modifier);
+ gen_helper_autia_combined(truedst, tcg_env, dst, modifier);
} else {
- gen_helper_autib_combined(truedst, cpu_env, dst, modifier);
+ gen_helper_autib_combined(truedst, tcg_env, dst, modifier);
}
return truedst;
}
return true;
}
dst = tcg_temp_new_i64();
- tcg_gen_ld_i64(dst, cpu_env,
+ tcg_gen_ld_i64(dst, tcg_env,
offsetof(CPUARMState, elr_el[s->current_el]));
translator_io_start(&s->base);
- gen_helper_exception_return(cpu_env, dst);
+ gen_helper_exception_return(tcg_env, dst);
/* Must exit loop to check un-masked IRQs */
s->base.is_jmp = DISAS_EXIT;
return true;
return true;
}
dst = tcg_temp_new_i64();
- tcg_gen_ld_i64(dst, cpu_env,
+ tcg_gen_ld_i64(dst, tcg_env,
offsetof(CPUARMState, elr_el[s->current_el]));
dst = auth_branch_target(s, dst, cpu_X[31], !a->m);
translator_io_start(&s->base);
- gen_helper_exception_return(cpu_env, dst);
+ gen_helper_exception_return(tcg_env, dst);
/* Must exit loop to check un-masked IRQs */
s->base.is_jmp = DISAS_EXIT;
return true;
static bool trans_XPACLRI(DisasContext *s, arg_XPACLRI *a)
{
if (s->pauth_active) {
- gen_helper_xpaci(cpu_X[30], cpu_env, cpu_X[30]);
+ gen_helper_xpaci(cpu_X[30], tcg_env, cpu_X[30]);
}
return true;
}
static bool trans_PACIA1716(DisasContext *s, arg_PACIA1716 *a)
{
if (s->pauth_active) {
- gen_helper_pacia(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]);
+ gen_helper_pacia(cpu_X[17], tcg_env, cpu_X[17], cpu_X[16]);
}
return true;
}
static bool trans_PACIB1716(DisasContext *s, arg_PACIB1716 *a)
{
if (s->pauth_active) {
- gen_helper_pacib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]);
+ gen_helper_pacib(cpu_X[17], tcg_env, cpu_X[17], cpu_X[16]);
}
return true;
}
static bool trans_AUTIA1716(DisasContext *s, arg_AUTIA1716 *a)
{
if (s->pauth_active) {
- gen_helper_autia(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]);
+ gen_helper_autia(cpu_X[17], tcg_env, cpu_X[17], cpu_X[16]);
}
return true;
}
static bool trans_AUTIB1716(DisasContext *s, arg_AUTIB1716 *a)
{
if (s->pauth_active) {
- gen_helper_autib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]);
+ gen_helper_autib(cpu_X[17], tcg_env, cpu_X[17], cpu_X[16]);
}
return true;
}
* Test for EL2 present, and defer test for SEL2 to runtime.
*/
if (s->current_el <= 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) {
- gen_helper_vesb(cpu_env);
+ gen_helper_vesb(tcg_env);
}
}
return true;
static bool trans_PACIAZ(DisasContext *s, arg_PACIAZ *a)
{
if (s->pauth_active) {
- gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], tcg_constant_i64(0));
+ gen_helper_pacia(cpu_X[30], tcg_env, cpu_X[30], tcg_constant_i64(0));
}
return true;
}
static bool trans_PACIASP(DisasContext *s, arg_PACIASP *a)
{
if (s->pauth_active) {
- gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]);
+ gen_helper_pacia(cpu_X[30], tcg_env, cpu_X[30], cpu_X[31]);
}
return true;
}
static bool trans_PACIBZ(DisasContext *s, arg_PACIBZ *a)
{
if (s->pauth_active) {
- gen_helper_pacib(cpu_X[30], cpu_env, cpu_X[30], tcg_constant_i64(0));
+ gen_helper_pacib(cpu_X[30], tcg_env, cpu_X[30], tcg_constant_i64(0));
}
return true;
}
static bool trans_PACIBSP(DisasContext *s, arg_PACIBSP *a)
{
if (s->pauth_active) {
- gen_helper_pacib(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]);
+ gen_helper_pacib(cpu_X[30], tcg_env, cpu_X[30], cpu_X[31]);
}
return true;
}
static bool trans_AUTIAZ(DisasContext *s, arg_AUTIAZ *a)
{
if (s->pauth_active) {
- gen_helper_autia(cpu_X[30], cpu_env, cpu_X[30], tcg_constant_i64(0));
+ gen_helper_autia(cpu_X[30], tcg_env, cpu_X[30], tcg_constant_i64(0));
}
return true;
}
static bool trans_AUTIASP(DisasContext *s, arg_AUTIASP *a)
{
if (s->pauth_active) {
- gen_helper_autia(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]);
+ gen_helper_autia(cpu_X[30], tcg_env, cpu_X[30], cpu_X[31]);
}
return true;
}
static bool trans_AUTIBZ(DisasContext *s, arg_AUTIBZ *a)
{
if (s->pauth_active) {
- gen_helper_autib(cpu_X[30], cpu_env, cpu_X[30], tcg_constant_i64(0));
+ gen_helper_autib(cpu_X[30], tcg_env, cpu_X[30], tcg_constant_i64(0));
}
return true;
}
static bool trans_AUTIBSP(DisasContext *s, arg_AUTIBSP *a)
{
if (s->pauth_active) {
- gen_helper_autib(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]);
+ gen_helper_autib(cpu_X[30], tcg_env, cpu_X[30], cpu_X[31]);
}
return true;
}
if (s->current_el == 0) {
return false;
}
- gen_helper_msr_i_spsel(cpu_env, tcg_constant_i32(a->imm & PSTATE_SP));
+ gen_helper_msr_i_spsel(tcg_env, tcg_constant_i32(a->imm & PSTATE_SP));
s->base.is_jmp = DISAS_TOO_MANY;
return true;
}
static bool trans_MSR_i_DAIFSET(DisasContext *s, arg_i *a)
{
- gen_helper_msr_i_daifset(cpu_env, tcg_constant_i32(a->imm));
+ gen_helper_msr_i_daifset(tcg_env, tcg_constant_i32(a->imm));
s->base.is_jmp = DISAS_TOO_MANY;
return true;
}
static bool trans_MSR_i_DAIFCLEAR(DisasContext *s, arg_i *a)
{
- gen_helper_msr_i_daifclear(cpu_env, tcg_constant_i32(a->imm));
+ gen_helper_msr_i_daifclear(tcg_env, tcg_constant_i32(a->imm));
/* Exit the cpu loop to re-evaluate pending IRQs. */
s->base.is_jmp = DISAS_UPDATE_EXIT;
return true;
if ((old ^ new) & a->mask) {
/* At least one bit changes. */
- gen_helper_set_svcr(cpu_env, tcg_constant_i32(new),
+ gen_helper_set_svcr(tcg_env, tcg_constant_i32(new),
tcg_constant_i32(a->mask));
s->base.is_jmp = DISAS_TOO_MANY;
}
switch (s->current_el) {
case 0:
if (dc_isar_feature(aa64_tidcp1, s)) {
- gen_helper_tidcp_el0(cpu_env, tcg_constant_i32(syndrome));
+ gen_helper_tidcp_el0(tcg_env, tcg_constant_i32(syndrome));
}
break;
case 1:
- gen_helper_tidcp_el1(cpu_env, tcg_constant_i32(syndrome));
+ gen_helper_tidcp_el1(tcg_env, tcg_constant_i32(syndrome));
break;
}
}
syndrome = syn_aa64_sysregtrap(op0, op1, op2, crn, crm, rt, isread);
gen_a64_update_pc(s, 0);
tcg_ri = tcg_temp_new_ptr();
- gen_helper_access_check_cp_reg(tcg_ri, cpu_env,
+ gen_helper_access_check_cp_reg(tcg_ri, tcg_env,
tcg_constant_i32(key),
tcg_constant_i32(syndrome),
tcg_constant_i32(isread));
desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
tcg_rt = tcg_temp_new_i64();
- gen_helper_mte_check_zva(tcg_rt, cpu_env,
+ gen_helper_mte_check_zva(tcg_rt, tcg_env,
tcg_constant_i32(desc), cpu_reg(s, rt));
} else {
tcg_rt = clean_data_tbi(s, cpu_reg(s, rt));
}
- gen_helper_dc_zva(cpu_env, tcg_rt);
+ gen_helper_dc_zva(tcg_env, tcg_rt);
return;
case ARM_CP_DC_GVA:
{
/* Extract the tag from the register to match STZGM. */
tag = tcg_temp_new_i64();
tcg_gen_shri_i64(tag, tcg_rt, 56);
- gen_helper_stzgm_tags(cpu_env, clean_addr, tag);
+ gen_helper_stzgm_tags(tcg_env, clean_addr, tag);
}
}
return;
/* For DC_GZVA, we can rely on DC_ZVA for the proper fault. */
tcg_rt = cpu_reg(s, rt);
clean_addr = clean_data_tbi(s, tcg_rt);
- gen_helper_dc_zva(cpu_env, clean_addr);
+ gen_helper_dc_zva(tcg_env, clean_addr);
if (s->ata[0]) {
/* Extract the tag from the register to match STZGM. */
tag = tcg_temp_new_i64();
tcg_gen_shri_i64(tag, tcg_rt, 56);
- gen_helper_stzgm_tags(cpu_env, clean_addr, tag);
+ gen_helper_stzgm_tags(tcg_env, clean_addr, tag);
}
}
return;
if (!tcg_ri) {
tcg_ri = gen_lookup_cp_reg(key);
}
- gen_helper_get_cp_reg64(tcg_rt, cpu_env, tcg_ri);
+ gen_helper_get_cp_reg64(tcg_rt, tcg_env, tcg_ri);
} else {
- tcg_gen_ld_i64(tcg_rt, cpu_env, ri->fieldoffset);
+ tcg_gen_ld_i64(tcg_rt, tcg_env, ri->fieldoffset);
}
} else {
if (ri->type & ARM_CP_CONST) {
if (!tcg_ri) {
tcg_ri = gen_lookup_cp_reg(key);
}
- gen_helper_set_cp_reg64(cpu_env, tcg_ri, tcg_rt);
+ gen_helper_set_cp_reg64(tcg_env, tcg_ri, tcg_rt);
} else {
- tcg_gen_st_i64(tcg_rt, cpu_env, ri->fieldoffset);
+ tcg_gen_st_i64(tcg_rt, tcg_env, ri->fieldoffset);
}
}
* as an undefined insn by runtime configuration.
*/
gen_a64_update_pc(s, 0);
- gen_helper_pre_hvc(cpu_env);
+ gen_helper_pre_hvc(tcg_env);
/* Architecture requires ss advance before we do the actual work */
gen_ss_advance(s);
gen_exception_insn_el(s, 4, EXCP_HVC, syn_aa64_hvc(a->imm), 2);
return true;
}
gen_a64_update_pc(s, 0);
- gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa64_smc(a->imm)));
+ gen_helper_pre_smc(tcg_env, tcg_constant_i32(syn_aa64_smc(a->imm)));
/* Architecture requires ss advance before we do the actual work */
gen_ss_advance(s);
gen_exception_insn_el(s, 4, EXCP_SMC, syn_aa64_smc(a->imm), 3);
/* Perform the tag store, if tag access enabled. */
if (s->ata[0]) {
if (tb_cflags(s->base.tb) & CF_PARALLEL) {
- gen_helper_stg_parallel(cpu_env, dirty_addr, dirty_addr);
+ gen_helper_stg_parallel(tcg_env, dirty_addr, dirty_addr);
} else {
- gen_helper_stg(cpu_env, dirty_addr, dirty_addr);
+ gen_helper_stg(tcg_env, dirty_addr, dirty_addr);
}
}
if (s->pauth_active) {
if (!a->m) {
- gen_helper_autda_combined(dirty_addr, cpu_env, dirty_addr,
+ gen_helper_autda_combined(dirty_addr, tcg_env, dirty_addr,
tcg_constant_i64(0));
} else {
- gen_helper_autdb_combined(dirty_addr, cpu_env, dirty_addr,
+ gen_helper_autdb_combined(dirty_addr, tcg_env, dirty_addr,
tcg_constant_i64(0));
}
}
tcg_rt = cpu_reg(s, a->rt);
if (s->ata[0]) {
- gen_helper_stzgm_tags(cpu_env, addr, tcg_rt);
+ gen_helper_stzgm_tags(tcg_env, addr, tcg_rt);
}
/*
* The non-tags portion of STZGM is mostly like DC_ZVA,
*/
clean_addr = clean_data_tbi(s, addr);
tcg_gen_andi_i64(clean_addr, clean_addr, -size);
- gen_helper_dc_zva(cpu_env, clean_addr);
+ gen_helper_dc_zva(tcg_env, clean_addr);
return true;
}
tcg_rt = cpu_reg(s, a->rt);
if (s->ata[0]) {
- gen_helper_stgm(cpu_env, addr, tcg_rt);
+ gen_helper_stgm(tcg_env, addr, tcg_rt);
} else {
MMUAccessType acc = MMU_DATA_STORE;
int size = 4 << s->gm_blocksize;
tcg_rt = cpu_reg(s, a->rt);
if (s->ata[0]) {
- gen_helper_ldgm(tcg_rt, cpu_env, addr);
+ gen_helper_ldgm(tcg_rt, tcg_env, addr);
} else {
MMUAccessType acc = MMU_DATA_LOAD;
int size = 4 << s->gm_blocksize;
tcg_gen_andi_i64(addr, addr, -TAG_GRANULE);
tcg_rt = cpu_reg(s, a->rt);
if (s->ata[0]) {
- gen_helper_ldg(tcg_rt, cpu_env, addr, tcg_rt);
+ gen_helper_ldg(tcg_rt, tcg_env, addr, tcg_rt);
} else {
/*
* Tag access disabled: we must check for aborts on the load
* at least for system mode; user-only won't enforce alignment.
*/
if (is_pair) {
- gen_helper_st2g_stub(cpu_env, addr);
+ gen_helper_st2g_stub(tcg_env, addr);
} else {
- gen_helper_stg_stub(cpu_env, addr);
+ gen_helper_stg_stub(tcg_env, addr);
}
} else if (tb_cflags(s->base.tb) & CF_PARALLEL) {
if (is_pair) {
- gen_helper_st2g_parallel(cpu_env, addr, tcg_rt);
+ gen_helper_st2g_parallel(tcg_env, addr, tcg_rt);
} else {
- gen_helper_stg_parallel(cpu_env, addr, tcg_rt);
+ gen_helper_stg_parallel(tcg_env, addr, tcg_rt);
}
} else {
if (is_pair) {
- gen_helper_st2g(cpu_env, addr, tcg_rt);
+ gen_helper_st2g(tcg_env, addr, tcg_rt);
} else {
- gen_helper_stg(cpu_env, addr, tcg_rt);
+ gen_helper_stg(tcg_env, addr, tcg_rt);
}
}
* the syndrome anyway, we let it extract them from there rather
* than passing in an extra three integer arguments.
*/
- fn(cpu_env, tcg_constant_i32(syndrome), tcg_constant_i32(desc));
+ fn(tcg_env, tcg_constant_i32(syndrome), tcg_constant_i32(desc));
return true;
}
* the syndrome anyway, we let it extract them from there rather
* than passing in an extra three integer arguments.
*/
- fn(cpu_env, tcg_constant_i32(syndrome), tcg_constant_i32(wdesc),
+ fn(tcg_env, tcg_constant_i32(syndrome), tcg_constant_i32(wdesc),
tcg_constant_i32(rdesc));
return true;
}
tcg_rd = cpu_reg_sp(s, a->rd);
if (s->ata[0]) {
- gen_helper_addsubg(tcg_rd, cpu_env, tcg_rn,
+ gen_helper_addsubg(tcg_rd, tcg_env, tcg_rn,
tcg_constant_i32(imm),
tcg_constant_i32(a->uimm4));
} else {
case MAP(1, 0x01, 0x00): /* PACIA */
if (s->pauth_active) {
tcg_rd = cpu_reg(s, rd);
- gen_helper_pacia(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn));
+ gen_helper_pacia(tcg_rd, tcg_env, tcg_rd, cpu_reg_sp(s, rn));
} else if (!dc_isar_feature(aa64_pauth, s)) {
goto do_unallocated;
}
case MAP(1, 0x01, 0x01): /* PACIB */
if (s->pauth_active) {
tcg_rd = cpu_reg(s, rd);
- gen_helper_pacib(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn));
+ gen_helper_pacib(tcg_rd, tcg_env, tcg_rd, cpu_reg_sp(s, rn));
} else if (!dc_isar_feature(aa64_pauth, s)) {
goto do_unallocated;
}
case MAP(1, 0x01, 0x02): /* PACDA */
if (s->pauth_active) {
tcg_rd = cpu_reg(s, rd);
- gen_helper_pacda(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn));
+ gen_helper_pacda(tcg_rd, tcg_env, tcg_rd, cpu_reg_sp(s, rn));
} else if (!dc_isar_feature(aa64_pauth, s)) {
goto do_unallocated;
}
case MAP(1, 0x01, 0x03): /* PACDB */
if (s->pauth_active) {
tcg_rd = cpu_reg(s, rd);
- gen_helper_pacdb(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn));
+ gen_helper_pacdb(tcg_rd, tcg_env, tcg_rd, cpu_reg_sp(s, rn));
} else if (!dc_isar_feature(aa64_pauth, s)) {
goto do_unallocated;
}
case MAP(1, 0x01, 0x04): /* AUTIA */
if (s->pauth_active) {
tcg_rd = cpu_reg(s, rd);
- gen_helper_autia(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn));
+ gen_helper_autia(tcg_rd, tcg_env, tcg_rd, cpu_reg_sp(s, rn));
} else if (!dc_isar_feature(aa64_pauth, s)) {
goto do_unallocated;
}
case MAP(1, 0x01, 0x05): /* AUTIB */
if (s->pauth_active) {
tcg_rd = cpu_reg(s, rd);
- gen_helper_autib(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn));
+ gen_helper_autib(tcg_rd, tcg_env, tcg_rd, cpu_reg_sp(s, rn));
} else if (!dc_isar_feature(aa64_pauth, s)) {
goto do_unallocated;
}
case MAP(1, 0x01, 0x06): /* AUTDA */
if (s->pauth_active) {
tcg_rd = cpu_reg(s, rd);
- gen_helper_autda(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn));
+ gen_helper_autda(tcg_rd, tcg_env, tcg_rd, cpu_reg_sp(s, rn));
} else if (!dc_isar_feature(aa64_pauth, s)) {
goto do_unallocated;
}
case MAP(1, 0x01, 0x07): /* AUTDB */
if (s->pauth_active) {
tcg_rd = cpu_reg(s, rd);
- gen_helper_autdb(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn));
+ gen_helper_autdb(tcg_rd, tcg_env, tcg_rd, cpu_reg_sp(s, rn));
} else if (!dc_isar_feature(aa64_pauth, s)) {
goto do_unallocated;
}
goto do_unallocated;
} else if (s->pauth_active) {
tcg_rd = cpu_reg(s, rd);
- gen_helper_pacia(tcg_rd, cpu_env, tcg_rd, tcg_constant_i64(0));
+ gen_helper_pacia(tcg_rd, tcg_env, tcg_rd, tcg_constant_i64(0));
}
break;
case MAP(1, 0x01, 0x09): /* PACIZB */
goto do_unallocated;
} else if (s->pauth_active) {
tcg_rd = cpu_reg(s, rd);
- gen_helper_pacib(tcg_rd, cpu_env, tcg_rd, tcg_constant_i64(0));
+ gen_helper_pacib(tcg_rd, tcg_env, tcg_rd, tcg_constant_i64(0));
}
break;
case MAP(1, 0x01, 0x0a): /* PACDZA */
goto do_unallocated;
} else if (s->pauth_active) {
tcg_rd = cpu_reg(s, rd);
- gen_helper_pacda(tcg_rd, cpu_env, tcg_rd, tcg_constant_i64(0));
+ gen_helper_pacda(tcg_rd, tcg_env, tcg_rd, tcg_constant_i64(0));
}
break;
case MAP(1, 0x01, 0x0b): /* PACDZB */
goto do_unallocated;
} else if (s->pauth_active) {
tcg_rd = cpu_reg(s, rd);
- gen_helper_pacdb(tcg_rd, cpu_env, tcg_rd, tcg_constant_i64(0));
+ gen_helper_pacdb(tcg_rd, tcg_env, tcg_rd, tcg_constant_i64(0));
}
break;
case MAP(1, 0x01, 0x0c): /* AUTIZA */
goto do_unallocated;
} else if (s->pauth_active) {
tcg_rd = cpu_reg(s, rd);
- gen_helper_autia(tcg_rd, cpu_env, tcg_rd, tcg_constant_i64(0));
+ gen_helper_autia(tcg_rd, tcg_env, tcg_rd, tcg_constant_i64(0));
}
break;
case MAP(1, 0x01, 0x0d): /* AUTIZB */
goto do_unallocated;
} else if (s->pauth_active) {
tcg_rd = cpu_reg(s, rd);
- gen_helper_autib(tcg_rd, cpu_env, tcg_rd, tcg_constant_i64(0));
+ gen_helper_autib(tcg_rd, tcg_env, tcg_rd, tcg_constant_i64(0));
}
break;
case MAP(1, 0x01, 0x0e): /* AUTDZA */
goto do_unallocated;
} else if (s->pauth_active) {
tcg_rd = cpu_reg(s, rd);
- gen_helper_autda(tcg_rd, cpu_env, tcg_rd, tcg_constant_i64(0));
+ gen_helper_autda(tcg_rd, tcg_env, tcg_rd, tcg_constant_i64(0));
}
break;
case MAP(1, 0x01, 0x0f): /* AUTDZB */
goto do_unallocated;
} else if (s->pauth_active) {
tcg_rd = cpu_reg(s, rd);
- gen_helper_autdb(tcg_rd, cpu_env, tcg_rd, tcg_constant_i64(0));
+ gen_helper_autdb(tcg_rd, tcg_env, tcg_rd, tcg_constant_i64(0));
}
break;
case MAP(1, 0x01, 0x10): /* XPACI */
goto do_unallocated;
} else if (s->pauth_active) {
tcg_rd = cpu_reg(s, rd);
- gen_helper_xpaci(tcg_rd, cpu_env, tcg_rd);
+ gen_helper_xpaci(tcg_rd, tcg_env, tcg_rd);
}
break;
case MAP(1, 0x01, 0x11): /* XPACD */
goto do_unallocated;
} else if (s->pauth_active) {
tcg_rd = cpu_reg(s, rd);
- gen_helper_xpacd(tcg_rd, cpu_env, tcg_rd);
+ gen_helper_xpacd(tcg_rd, tcg_env, tcg_rd);
}
break;
default:
goto do_unallocated;
}
if (s->ata[0]) {
- gen_helper_irg(cpu_reg_sp(s, rd), cpu_env,
+ gen_helper_irg(cpu_reg_sp(s, rd), tcg_env,
cpu_reg_sp(s, rn), cpu_reg(s, rm));
} else {
gen_address_with_allocation_tag0(cpu_reg_sp(s, rd),
if (sf == 0 || !dc_isar_feature(aa64_pauth, s)) {
goto do_unallocated;
}
- gen_helper_pacga(cpu_reg(s, rd), cpu_env,
+ gen_helper_pacga(cpu_reg(s, rd), tcg_env,
cpu_reg(s, rn), cpu_reg_sp(s, rm));
break;
case 16:
gen_helper_vfp_negs(tcg_res, tcg_op);
goto done;
case 0x3: /* FSQRT */
- gen_helper_vfp_sqrts(tcg_res, tcg_op, cpu_env);
+ gen_helper_vfp_sqrts(tcg_res, tcg_op, tcg_env);
goto done;
case 0x6: /* BFCVT */
gen_fpst = gen_helper_bfcvt;
gen_helper_vfp_negd(tcg_res, tcg_op);
goto done;
case 0x3: /* FSQRT */
- gen_helper_vfp_sqrtd(tcg_res, tcg_op, cpu_env);
+ gen_helper_vfp_sqrtd(tcg_res, tcg_op, tcg_env);
goto done;
case 0x8: /* FRINTN */
case 0x9: /* FRINTP */
if (dtype == 1) {
/* Single to double */
TCGv_i64 tcg_rd = tcg_temp_new_i64();
- gen_helper_vfp_fcvtds(tcg_rd, tcg_rn, cpu_env);
+ gen_helper_vfp_fcvtds(tcg_rd, tcg_rn, tcg_env);
write_fp_dreg(s, rd, tcg_rd);
} else {
/* Single to half */
TCGv_i32 tcg_rd = tcg_temp_new_i32();
if (dtype == 0) {
/* Double to single */
- gen_helper_vfp_fcvtsd(tcg_rd, tcg_rn, cpu_env);
+ gen_helper_vfp_fcvtsd(tcg_rd, tcg_rn, tcg_env);
} else {
TCGv_ptr fpst = fpstatus_ptr(FPST_FPCR);
TCGv_i32 ahp = get_ahp_flag();
break;
case 2:
/* 64 bit to top half. */
- tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_hi_offset(s, rd));
+ tcg_gen_st_i64(tcg_rn, tcg_env, fp_reg_hi_offset(s, rd));
clear_vec_high(s, true, rd);
break;
case 3:
switch (type) {
case 0:
/* 32 bit */
- tcg_gen_ld32u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_32));
+ tcg_gen_ld32u_i64(tcg_rd, tcg_env, fp_reg_offset(s, rn, MO_32));
break;
case 1:
/* 64 bit */
- tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_64));
+ tcg_gen_ld_i64(tcg_rd, tcg_env, fp_reg_offset(s, rn, MO_64));
break;
case 2:
/* 64 bits from top half */
- tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_hi_offset(s, rn));
+ tcg_gen_ld_i64(tcg_rd, tcg_env, fp_reg_hi_offset(s, rn));
break;
case 3:
/* 16 bit */
- tcg_gen_ld16u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_16));
+ tcg_gen_ld16u_i64(tcg_rd, tcg_env, fp_reg_offset(s, rn, MO_16));
break;
default:
g_assert_not_reached();
}
tcg_gen_gvec_2_ptr(vec_full_reg_offset(s, rd),
- vec_full_reg_offset(s, rm), cpu_env,
+ vec_full_reg_offset(s, rm), tcg_env,
is_q ? 16 : 8, vec_full_reg_size(s),
(len << 6) | (is_tbx << 5) | rn,
gen_helper_simd_tblx);
read_vec_element(s, tcg_rn, rn, i, ldop);
handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round,
false, is_u_shift, size+1, shift);
- narrowfn(tcg_rd_narrowed, cpu_env, tcg_rd);
+ narrowfn(tcg_rd_narrowed, tcg_env, tcg_rd);
tcg_gen_extu_i32_i64(tcg_rd, tcg_rd_narrowed);
if (i == 0) {
tcg_gen_mov_i64(tcg_final, tcg_rd);
TCGv_i64 tcg_op = tcg_temp_new_i64();
read_vec_element(s, tcg_op, rn, pass, MO_64);
- genfn(tcg_op, cpu_env, tcg_op, tcg_shift);
+ genfn(tcg_op, tcg_env, tcg_op, tcg_shift);
write_vec_element(s, tcg_op, rd, pass, MO_64);
}
clear_vec_high(s, is_q, rd);
TCGv_i32 tcg_op = tcg_temp_new_i32();
read_vec_element_i32(s, tcg_op, rn, pass, memop);
- genfn(tcg_op, cpu_env, tcg_op, tcg_shift);
+ genfn(tcg_op, tcg_env, tcg_op, tcg_shift);
if (scalar) {
switch (size) {
case 0:
read_vec_element(s, tcg_op2, rm, 0, MO_32 | MO_SIGN);
tcg_gen_mul_i64(tcg_res, tcg_op1, tcg_op2);
- gen_helper_neon_addl_saturate_s64(tcg_res, cpu_env, tcg_res, tcg_res);
+ gen_helper_neon_addl_saturate_s64(tcg_res, tcg_env, tcg_res, tcg_res);
switch (opcode) {
case 0xd: /* SQDMULL, SQDMULL2 */
/* fall through */
case 0x9: /* SQDMLAL, SQDMLAL2 */
read_vec_element(s, tcg_op1, rd, 0, MO_64);
- gen_helper_neon_addl_saturate_s64(tcg_res, cpu_env,
+ gen_helper_neon_addl_saturate_s64(tcg_res, tcg_env,
tcg_res, tcg_op1);
break;
default:
TCGv_i64 tcg_res = tcg_temp_new_i64();
gen_helper_neon_mull_s16(tcg_res, tcg_op1, tcg_op2);
- gen_helper_neon_addl_saturate_s32(tcg_res, cpu_env, tcg_res, tcg_res);
+ gen_helper_neon_addl_saturate_s32(tcg_res, tcg_env, tcg_res, tcg_res);
switch (opcode) {
case 0xd: /* SQDMULL, SQDMULL2 */
{
TCGv_i64 tcg_op3 = tcg_temp_new_i64();
read_vec_element(s, tcg_op3, rd, 0, MO_32);
- gen_helper_neon_addl_saturate_s32(tcg_res, cpu_env,
+ gen_helper_neon_addl_saturate_s32(tcg_res, tcg_env,
tcg_res, tcg_op3);
break;
}
switch (opcode) {
case 0x1: /* SQADD */
if (u) {
- gen_helper_neon_qadd_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm);
+ gen_helper_neon_qadd_u64(tcg_rd, tcg_env, tcg_rn, tcg_rm);
} else {
- gen_helper_neon_qadd_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm);
+ gen_helper_neon_qadd_s64(tcg_rd, tcg_env, tcg_rn, tcg_rm);
}
break;
case 0x5: /* SQSUB */
if (u) {
- gen_helper_neon_qsub_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm);
+ gen_helper_neon_qsub_u64(tcg_rd, tcg_env, tcg_rn, tcg_rm);
} else {
- gen_helper_neon_qsub_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm);
+ gen_helper_neon_qsub_s64(tcg_rd, tcg_env, tcg_rn, tcg_rm);
}
break;
case 0x6: /* CMGT, CMHI */
break;
case 0x9: /* SQSHL, UQSHL */
if (u) {
- gen_helper_neon_qshl_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm);
+ gen_helper_neon_qshl_u64(tcg_rd, tcg_env, tcg_rn, tcg_rm);
} else {
- gen_helper_neon_qshl_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm);
+ gen_helper_neon_qshl_s64(tcg_rd, tcg_env, tcg_rn, tcg_rm);
}
break;
case 0xa: /* SRSHL, URSHL */
break;
case 0xb: /* SQRSHL, UQRSHL */
if (u) {
- gen_helper_neon_qrshl_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm);
+ gen_helper_neon_qrshl_u64(tcg_rd, tcg_env, tcg_rn, tcg_rm);
} else {
- gen_helper_neon_qrshl_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm);
+ gen_helper_neon_qrshl_s64(tcg_rd, tcg_env, tcg_rn, tcg_rm);
}
break;
case 0x10: /* ADD, SUB */
g_assert_not_reached();
}
- genenvfn(tcg_rd32, cpu_env, tcg_rn, tcg_rm);
+ genenvfn(tcg_rd32, tcg_env, tcg_rn, tcg_rm);
tcg_gen_extu_i32_i64(tcg_rd, tcg_rd32);
}
switch (opcode) {
case 0x0: /* SQRDMLAH */
if (size == 1) {
- gen_helper_neon_qrdmlah_s16(ele3, cpu_env, ele1, ele2, ele3);
+ gen_helper_neon_qrdmlah_s16(ele3, tcg_env, ele1, ele2, ele3);
} else {
- gen_helper_neon_qrdmlah_s32(ele3, cpu_env, ele1, ele2, ele3);
+ gen_helper_neon_qrdmlah_s32(ele3, tcg_env, ele1, ele2, ele3);
}
break;
case 0x1: /* SQRDMLSH */
if (size == 1) {
- gen_helper_neon_qrdmlsh_s16(ele3, cpu_env, ele1, ele2, ele3);
+ gen_helper_neon_qrdmlsh_s16(ele3, tcg_env, ele1, ele2, ele3);
} else {
- gen_helper_neon_qrdmlsh_s32(ele3, cpu_env, ele1, ele2, ele3);
+ gen_helper_neon_qrdmlsh_s32(ele3, tcg_env, ele1, ele2, ele3);
}
break;
default:
break;
case 0x7: /* SQABS, SQNEG */
if (u) {
- gen_helper_neon_qneg_s64(tcg_rd, cpu_env, tcg_rn);
+ gen_helper_neon_qneg_s64(tcg_rd, tcg_env, tcg_rn);
} else {
- gen_helper_neon_qabs_s64(tcg_rd, cpu_env, tcg_rn);
+ gen_helper_neon_qabs_s64(tcg_rd, tcg_env, tcg_rn);
}
break;
case 0xa: /* CMLT */
gen_helper_vfp_negd(tcg_rd, tcg_rn);
break;
case 0x7f: /* FSQRT */
- gen_helper_vfp_sqrtd(tcg_rd, tcg_rn, cpu_env);
+ gen_helper_vfp_sqrtd(tcg_rd, tcg_rn, tcg_env);
break;
case 0x1a: /* FCVTNS */
case 0x1b: /* FCVTMS */
case 0x16: /* FCVTN, FCVTN2 */
/* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
if (size == 2) {
- gen_helper_vfp_fcvtsd(tcg_res[pass], tcg_op, cpu_env);
+ gen_helper_vfp_fcvtsd(tcg_res[pass], tcg_op, tcg_env);
} else {
TCGv_i32 tcg_lo = tcg_temp_new_i32();
TCGv_i32 tcg_hi = tcg_temp_new_i32();
* with von Neumann rounding (round to odd)
*/
assert(size == 2);
- gen_helper_fcvtx_f64_to_f32(tcg_res[pass], tcg_op, cpu_env);
+ gen_helper_fcvtx_f64_to_f32(tcg_res[pass], tcg_op, tcg_env);
break;
default:
g_assert_not_reached();
if (genfn) {
genfn(tcg_res[pass], tcg_op);
} else if (genenvfn) {
- genenvfn(tcg_res[pass], cpu_env, tcg_op);
+ genenvfn(tcg_res[pass], tcg_env, tcg_op);
}
}
read_vec_element(s, tcg_rd, rd, pass, MO_64);
if (is_u) { /* USQADD */
- gen_helper_neon_uqadd_s64(tcg_rd, cpu_env, tcg_rn, tcg_rd);
+ gen_helper_neon_uqadd_s64(tcg_rd, tcg_env, tcg_rn, tcg_rd);
} else { /* SUQADD */
- gen_helper_neon_sqadd_u64(tcg_rd, cpu_env, tcg_rn, tcg_rd);
+ gen_helper_neon_sqadd_u64(tcg_rd, tcg_env, tcg_rn, tcg_rd);
}
write_vec_element(s, tcg_rd, rd, pass, MO_64);
}
if (is_u) { /* USQADD */
switch (size) {
case 0:
- gen_helper_neon_uqadd_s8(tcg_rd, cpu_env, tcg_rn, tcg_rd);
+ gen_helper_neon_uqadd_s8(tcg_rd, tcg_env, tcg_rn, tcg_rd);
break;
case 1:
- gen_helper_neon_uqadd_s16(tcg_rd, cpu_env, tcg_rn, tcg_rd);
+ gen_helper_neon_uqadd_s16(tcg_rd, tcg_env, tcg_rn, tcg_rd);
break;
case 2:
- gen_helper_neon_uqadd_s32(tcg_rd, cpu_env, tcg_rn, tcg_rd);
+ gen_helper_neon_uqadd_s32(tcg_rd, tcg_env, tcg_rn, tcg_rd);
break;
default:
g_assert_not_reached();
} else { /* SUQADD */
switch (size) {
case 0:
- gen_helper_neon_sqadd_u8(tcg_rd, cpu_env, tcg_rn, tcg_rd);
+ gen_helper_neon_sqadd_u8(tcg_rd, tcg_env, tcg_rn, tcg_rd);
break;
case 1:
- gen_helper_neon_sqadd_u16(tcg_rd, cpu_env, tcg_rn, tcg_rd);
+ gen_helper_neon_sqadd_u16(tcg_rd, tcg_env, tcg_rn, tcg_rd);
break;
case 2:
- gen_helper_neon_sqadd_u32(tcg_rd, cpu_env, tcg_rn, tcg_rd);
+ gen_helper_neon_sqadd_u32(tcg_rd, tcg_env, tcg_rn, tcg_rd);
break;
default:
g_assert_not_reached();
{ gen_helper_neon_qabs_s32, gen_helper_neon_qneg_s32 },
};
genfn = fns[size][u];
- genfn(tcg_rd, cpu_env, tcg_rn);
+ genfn(tcg_rd, tcg_env, tcg_rn);
break;
}
case 0x1a: /* FCVTNS */
case 11: /* SQDMLSL, SQDMLSL2 */
case 13: /* SQDMULL, SQDMULL2 */
tcg_gen_mul_i64(tcg_passres, tcg_op1, tcg_op2);
- gen_helper_neon_addl_saturate_s64(tcg_passres, cpu_env,
+ gen_helper_neon_addl_saturate_s64(tcg_passres, tcg_env,
tcg_passres, tcg_passres);
break;
default:
if (accop < 0) {
tcg_gen_neg_i64(tcg_passres, tcg_passres);
}
- gen_helper_neon_addl_saturate_s64(tcg_res[pass], cpu_env,
+ gen_helper_neon_addl_saturate_s64(tcg_res[pass], tcg_env,
tcg_res[pass], tcg_passres);
} else if (accop > 0) {
tcg_gen_add_i64(tcg_res[pass], tcg_res[pass], tcg_passres);
case 13: /* SQDMULL, SQDMULL2 */
assert(size == 1);
gen_helper_neon_mull_s16(tcg_passres, tcg_op1, tcg_op2);
- gen_helper_neon_addl_saturate_s32(tcg_passres, cpu_env,
+ gen_helper_neon_addl_saturate_s32(tcg_passres, tcg_env,
tcg_passres, tcg_passres);
break;
default:
if (accop < 0) {
gen_helper_neon_negl_u32(tcg_passres, tcg_passres);
}
- gen_helper_neon_addl_saturate_s32(tcg_res[pass], cpu_env,
+ gen_helper_neon_addl_saturate_s32(tcg_res[pass], tcg_env,
tcg_res[pass],
tcg_passres);
} else {
int data = (is_2 << 1) | is_s;
tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd),
vec_full_reg_offset(s, rn),
- vec_full_reg_offset(s, rm), cpu_env,
+ vec_full_reg_offset(s, rm), tcg_env,
is_q ? 16 : 8, vec_full_reg_size(s),
data, gen_helper_gvec_fmlal_a64);
}
}
if (genenvfn) {
- genenvfn(tcg_res, cpu_env, tcg_op1, tcg_op2);
+ genenvfn(tcg_res, tcg_env, tcg_op1, tcg_op2);
} else {
genfn(tcg_res, tcg_op1, tcg_op2);
}
tcg_res[pass] = tcg_temp_new_i64();
read_vec_element_i32(s, tcg_op, rn, srcelt + pass, MO_32);
- gen_helper_vfp_fcvtds(tcg_res[pass], tcg_op, cpu_env);
+ gen_helper_vfp_fcvtds(tcg_res[pass], tcg_op, tcg_env);
}
for (pass = 0; pass < 2; pass++) {
write_vec_element(s, tcg_res[pass], rd, pass, MO_64);
break;
case 0x7: /* SQABS, SQNEG */
if (u) {
- gen_helper_neon_qneg_s32(tcg_res, cpu_env, tcg_op);
+ gen_helper_neon_qneg_s32(tcg_res, tcg_env, tcg_op);
} else {
- gen_helper_neon_qabs_s32(tcg_res, cpu_env, tcg_op);
+ gen_helper_neon_qabs_s32(tcg_res, tcg_env, tcg_op);
}
break;
case 0x2f: /* FABS */
gen_helper_vfp_negs(tcg_res, tcg_op);
break;
case 0x7f: /* FSQRT */
- gen_helper_vfp_sqrts(tcg_res, tcg_op, cpu_env);
+ gen_helper_vfp_sqrts(tcg_res, tcg_op, tcg_env);
break;
case 0x1a: /* FCVTNS */
case 0x1b: /* FCVTMS */
{ gen_helper_neon_qabs_s16, gen_helper_neon_qneg_s16 },
};
genfn = fns[size][u];
- genfn(tcg_res, cpu_env, tcg_op);
+ genfn(tcg_res, tcg_env, tcg_op);
break;
}
case 0x4: /* CLS, CLZ */
return;
}
size = MO_16;
- /* is_fp, but we pass cpu_env not fp_status. */
+ /* is_fp, but we pass tcg_env not fp_status. */
break;
default:
unallocated_encoding(s);
int data = (index << 2) | (is_2 << 1) | is_s;
tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd),
vec_full_reg_offset(s, rn),
- vec_full_reg_offset(s, rm), cpu_env,
+ vec_full_reg_offset(s, rm), tcg_env,
is_q ? 16 : 8, vec_full_reg_size(s),
data, gen_helper_gvec_fmlal_idx_a64);
}
break;
case 0x0c: /* SQDMULH */
if (size == 1) {
- gen_helper_neon_qdmulh_s16(tcg_res, cpu_env,
+ gen_helper_neon_qdmulh_s16(tcg_res, tcg_env,
tcg_op, tcg_idx);
} else {
- gen_helper_neon_qdmulh_s32(tcg_res, cpu_env,
+ gen_helper_neon_qdmulh_s32(tcg_res, tcg_env,
tcg_op, tcg_idx);
}
break;
case 0x0d: /* SQRDMULH */
if (size == 1) {
- gen_helper_neon_qrdmulh_s16(tcg_res, cpu_env,
+ gen_helper_neon_qrdmulh_s16(tcg_res, tcg_env,
tcg_op, tcg_idx);
} else {
- gen_helper_neon_qrdmulh_s32(tcg_res, cpu_env,
+ gen_helper_neon_qrdmulh_s32(tcg_res, tcg_env,
tcg_op, tcg_idx);
}
break;
read_vec_element_i32(s, tcg_res, rd, pass,
is_scalar ? size : MO_32);
if (size == 1) {
- gen_helper_neon_qrdmlah_s16(tcg_res, cpu_env,
+ gen_helper_neon_qrdmlah_s16(tcg_res, tcg_env,
tcg_op, tcg_idx, tcg_res);
} else {
- gen_helper_neon_qrdmlah_s32(tcg_res, cpu_env,
+ gen_helper_neon_qrdmlah_s32(tcg_res, tcg_env,
tcg_op, tcg_idx, tcg_res);
}
break;
read_vec_element_i32(s, tcg_res, rd, pass,
is_scalar ? size : MO_32);
if (size == 1) {
- gen_helper_neon_qrdmlsh_s16(tcg_res, cpu_env,
+ gen_helper_neon_qrdmlsh_s16(tcg_res, tcg_env,
tcg_op, tcg_idx, tcg_res);
} else {
- gen_helper_neon_qrdmlsh_s32(tcg_res, cpu_env,
+ gen_helper_neon_qrdmlsh_s32(tcg_res, tcg_env,
tcg_op, tcg_idx, tcg_res);
}
break;
if (satop) {
/* saturating, doubling */
- gen_helper_neon_addl_saturate_s64(tcg_passres, cpu_env,
+ gen_helper_neon_addl_saturate_s64(tcg_passres, tcg_env,
tcg_passres, tcg_passres);
}
tcg_gen_neg_i64(tcg_passres, tcg_passres);
/* fall through */
case 0x3: /* SQDMLAL, SQDMLAL2 */
- gen_helper_neon_addl_saturate_s64(tcg_res[pass], cpu_env,
+ gen_helper_neon_addl_saturate_s64(tcg_res[pass], tcg_env,
tcg_res[pass],
tcg_passres);
break;
gen_helper_neon_mull_u16(tcg_passres, tcg_op, tcg_idx);
}
if (satop) {
- gen_helper_neon_addl_saturate_s32(tcg_passres, cpu_env,
+ gen_helper_neon_addl_saturate_s32(tcg_passres, tcg_env,
tcg_passres, tcg_passres);
}
gen_helper_neon_negl_u32(tcg_passres, tcg_passres);
/* fall through */
case 0x3: /* SQDMLAL, SQDMLAL2 */
- gen_helper_neon_addl_saturate_s32(tcg_res[pass], cpu_env,
+ gen_helper_neon_addl_saturate_s32(tcg_res[pass], tcg_env,
tcg_res[pass],
tcg_passres);
break;
* start of the TB.
*/
assert(s->base.num_insns == 1);
- gen_helper_exception_pc_alignment(cpu_env, tcg_constant_tl(pc));
+ gen_helper_exception_pc_alignment(tcg_env, tcg_constant_tl(pc));
s->base.is_jmp = DISAS_NORETURN;
s->base.pc_next = QEMU_ALIGN_UP(pc, 4);
return;
break;
case DISAS_WFE:
gen_a64_update_pc(dc, 4);
- gen_helper_wfe(cpu_env);
+ gen_helper_wfe(tcg_env);
break;
case DISAS_YIELD:
gen_a64_update_pc(dc, 4);
- gen_helper_yield(cpu_env);
+ gen_helper_yield(tcg_env);
break;
case DISAS_WFI:
/*
* the CPU if trying to debug across a WFI.
*/
gen_a64_update_pc(dc, 4);
- gen_helper_wfi(cpu_env, tcg_constant_i32(4));
+ gen_helper_wfi(tcg_env, tcg_constant_i32(4));
/*
* The helper doesn't necessarily throw an exception, but we
* must go back to the main loop to check for interrupts anyway.
static inline TCGv_ptr vec_full_reg_ptr(DisasContext *s, int regno)
{
TCGv_ptr ret = tcg_temp_new_ptr();
- tcg_gen_addi_ptr(ret, cpu_env, vec_full_reg_offset(s, regno));
+ tcg_gen_addi_ptr(ret, tcg_env, vec_full_reg_offset(s, regno));
return ret;
}
static inline TCGv_ptr pred_full_reg_ptr(DisasContext *s, int regno)
{
TCGv_ptr ret = tcg_temp_new_ptr();
- tcg_gen_addi_ptr(ret, cpu_env, pred_full_reg_offset(s, regno));
+ tcg_gen_addi_ptr(ret, tcg_env, pred_full_reg_offset(s, regno));
return ret;
}
fptr = load_reg(s, a->rn);
if (a->l) {
- gen_helper_v7m_vlldm(cpu_env, fptr);
+ gen_helper_v7m_vlldm(tcg_env, fptr);
} else {
- gen_helper_v7m_vlstm(cpu_env, fptr);
+ gen_helper_v7m_vlstm(tcg_env, fptr);
}
clear_eci_state(s);
switch (regno) {
case ARM_VFP_FPSCR:
tmp = loadfn(s, opaque, true);
- gen_helper_vfp_set_fpscr(cpu_env, tmp);
+ gen_helper_vfp_set_fpscr(tcg_env, tmp);
gen_lookup_tb(s);
break;
case ARM_VFP_FPSCR_NZCVQC:
R_V7M_CONTROL_SFPA_SHIFT, 1);
store_cpu_field(control, v7m.control[M_REG_S]);
tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK);
- gen_helper_vfp_set_fpscr(cpu_env, tmp);
+ gen_helper_vfp_set_fpscr(tcg_env, tmp);
s->base.is_jmp = DISAS_UPDATE_NOCHAIN;
break;
}
switch (regno) {
case ARM_VFP_FPSCR:
tmp = tcg_temp_new_i32();
- gen_helper_vfp_get_fpscr(tmp, cpu_env);
+ gen_helper_vfp_get_fpscr(tmp, tcg_env);
storefn(s, opaque, tmp, true);
break;
case ARM_VFP_FPSCR_NZCVQC:
tmp = tcg_temp_new_i32();
- gen_helper_vfp_get_fpscr(tmp, cpu_env);
+ gen_helper_vfp_get_fpscr(tmp, tcg_env);
tcg_gen_andi_i32(tmp, tmp, FPCR_NZCVQC_MASK);
storefn(s, opaque, tmp, true);
break;
/* Bits [27:0] from FPSCR, bit [31] from CONTROL.SFPA */
tmp = tcg_temp_new_i32();
sfpa = tcg_temp_new_i32();
- gen_helper_vfp_get_fpscr(tmp, cpu_env);
+ gen_helper_vfp_get_fpscr(tmp, tcg_env);
tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK);
control = load_cpu_field(v7m.control[M_REG_S]);
tcg_gen_andi_i32(sfpa, control, R_V7M_CONTROL_SFPA_MASK);
tcg_gen_andi_i32(control, control, ~R_V7M_CONTROL_SFPA_MASK);
store_cpu_field(control, v7m.control[M_REG_S]);
fpscr = load_cpu_field(v7m.fpdscr[M_REG_NS]);
- gen_helper_vfp_set_fpscr(cpu_env, fpscr);
+ gen_helper_vfp_set_fpscr(tcg_env, fpscr);
lookup_tb = true;
break;
}
tmp = tcg_temp_new_i32();
sfpa = tcg_temp_new_i32();
fpscr = tcg_temp_new_i32();
- gen_helper_vfp_get_fpscr(fpscr, cpu_env);
+ gen_helper_vfp_get_fpscr(fpscr, tcg_env);
tcg_gen_andi_i32(tmp, fpscr, ~FPCR_NZCV_MASK);
control = load_cpu_field(v7m.control[M_REG_S]);
tcg_gen_andi_i32(sfpa, control, R_V7M_CONTROL_SFPA_MASK);
fpdscr = load_cpu_field(v7m.fpdscr[M_REG_NS]);
tcg_gen_movcond_i32(TCG_COND_EQ, fpscr, sfpa, tcg_constant_i32(0),
fpdscr, fpscr);
- gen_helper_vfp_set_fpscr(cpu_env, fpscr);
+ gen_helper_vfp_set_fpscr(tcg_env, fpscr);
break;
}
case ARM_VFP_VPR:
}
if (s->v8m_stackcheck && a->rn == 13 && a->w) {
- gen_helper_v8m_stackcheck(cpu_env, addr);
+ gen_helper_v8m_stackcheck(tcg_env, addr);
}
if (do_access) {
}
if (s->v8m_stackcheck && a->rn == 13 && a->w) {
- gen_helper_v8m_stackcheck(cpu_env, addr);
+ gen_helper_v8m_stackcheck(tcg_env, addr);
}
if (do_access) {
static TCGv_ptr mve_qreg_ptr(unsigned reg)
{
TCGv_ptr ret = tcg_temp_new_ptr();
- tcg_gen_addi_ptr(ret, cpu_env, mve_qreg_offset(reg));
+ tcg_gen_addi_ptr(ret, tcg_env, mve_qreg_offset(reg));
return ret;
}
}
qreg = mve_qreg_ptr(a->qd);
- fn(cpu_env, qreg, addr);
+ fn(tcg_env, qreg, addr);
/*
* Writeback always happens after the last beat of the insn,
qd = mve_qreg_ptr(a->qd);
qm = mve_qreg_ptr(a->qm);
- fn(cpu_env, qd, qm, addr);
+ fn(tcg_env, qd, qm, addr);
mve_update_eci(s);
return true;
}
qd = mve_qreg_ptr(a->qd);
qm = mve_qreg_ptr(a->qm);
- fn(cpu_env, qd, qm, tcg_constant_i32(offset));
+ fn(tcg_env, qd, qm, tcg_constant_i32(offset));
mve_update_eci(s);
return true;
}
* We pass the index of Qd, not a pointer, because the helper must
* access multiple Q registers starting at Qd and working up.
*/
- fn(cpu_env, tcg_constant_i32(a->qd), rn);
+ fn(tcg_env, tcg_constant_i32(a->qd), rn);
if (a->w) {
tcg_gen_addi_i32(rn, rn, addrinc);
} else {
qd = mve_qreg_ptr(a->qd);
tcg_gen_dup_i32(a->size, rt, rt);
- gen_helper_mve_vdup(cpu_env, qd, rt);
+ gen_helper_mve_vdup(tcg_env, qd, rt);
}
mve_update_eci(s);
return true;
} else {
qd = mve_qreg_ptr(a->qd);
qm = mve_qreg_ptr(a->qm);
- fn(cpu_env, qd, qm);
+ fn(tcg_env, qd, qm);
}
mve_update_eci(s);
return true;
qd = mve_qreg_ptr(a->qd);
qm = mve_qreg_ptr(a->qm);
- fn(cpu_env, qd, qm, tcg_constant_i32(arm_rmode_to_sf(rmode)));
+ fn(tcg_env, qd, qm, tcg_constant_i32(arm_rmode_to_sf(rmode)));
mve_update_eci(s);
return true;
}
qd = mve_qreg_ptr(a->qd);
qn = mve_qreg_ptr(a->qn);
qm = mve_qreg_ptr(a->qm);
- fn(cpu_env, qd, qn, qm);
+ fn(tcg_env, qd, qn, qm);
}
mve_update_eci(s);
return true;
qd = mve_qreg_ptr(a->qd);
qn = mve_qreg_ptr(a->qn);
rm = load_reg(s, a->rm);
- fn(cpu_env, qd, qn, rm);
+ fn(tcg_env, qd, qn, rm);
mve_update_eci(s);
return true;
}
rda_i = tcg_constant_i64(0);
}
- fn(rda_o, cpu_env, qn, qm, rda_i);
+ fn(rda_o, tcg_env, qn, qm, rda_i);
rdalo = tcg_temp_new_i32();
rdahi = tcg_temp_new_i32();
rda_o = tcg_temp_new_i32();
}
- fn(rda_o, cpu_env, qn, qm, rda_i);
+ fn(rda_o, tcg_env, qn, qm, rda_i);
store_reg(s, a->rda, rda_o);
mve_update_eci(s);
return true;
}
- gen_helper_mve_vpnot(cpu_env);
+ gen_helper_mve_vpnot(tcg_env);
/* This insn updates predication bits */
s->base.is_jmp = DISAS_UPDATE_NOCHAIN;
mve_update_eci(s);
}
qm = mve_qreg_ptr(a->qm);
- fns[a->size][a->u](rda_o, cpu_env, qm, rda_i);
+ fns[a->size][a->u](rda_o, tcg_env, qm, rda_i);
store_reg(s, a->rda, rda_o);
mve_update_eci(s);
qm = mve_qreg_ptr(a->qm);
if (a->u) {
- gen_helper_mve_vaddlv_u(rda_o, cpu_env, qm, rda_i);
+ gen_helper_mve_vaddlv_u(rda_o, tcg_env, qm, rda_i);
} else {
- gen_helper_mve_vaddlv_s(rda_o, cpu_env, qm, rda_i);
+ gen_helper_mve_vaddlv_s(rda_o, tcg_env, qm, rda_i);
}
rdalo = tcg_temp_new_i32();
imm, 16, 16);
} else {
qd = mve_qreg_ptr(a->qd);
- fn(cpu_env, qd, tcg_constant_i64(imm));
+ fn(tcg_env, qd, tcg_constant_i64(imm));
}
mve_update_eci(s);
return true;
} else {
qd = mve_qreg_ptr(a->qd);
qm = mve_qreg_ptr(a->qm);
- fn(cpu_env, qd, qm, tcg_constant_i32(shift));
+ fn(tcg_env, qd, qm, tcg_constant_i32(shift));
}
mve_update_eci(s);
return true;
qda = mve_qreg_ptr(a->qda);
rm = load_reg(s, a->rm);
- fn(cpu_env, qda, qda, rm);
+ fn(tcg_env, qda, qda, rm);
mve_update_eci(s);
return true;
}
qd = mve_qreg_ptr(a->qd);
rdm = load_reg(s, a->rdm);
- gen_helper_mve_vshlc(rdm, cpu_env, qd, rdm, tcg_constant_i32(a->imm));
+ gen_helper_mve_vshlc(rdm, tcg_env, qd, rdm, tcg_constant_i32(a->imm));
store_reg(s, a->rdm, rdm);
mve_update_eci(s);
return true;
qd = mve_qreg_ptr(a->qd);
rn = load_reg(s, a->rn);
- fn(rn, cpu_env, qd, rn, tcg_constant_i32(a->imm));
+ fn(rn, tcg_env, qd, rn, tcg_constant_i32(a->imm));
store_reg(s, a->rn, rn);
mve_update_eci(s);
return true;
qd = mve_qreg_ptr(a->qd);
rn = load_reg(s, a->rn);
rm = load_reg(s, a->rm);
- fn(rn, cpu_env, qd, rn, rm, tcg_constant_i32(a->imm));
+ fn(rn, tcg_env, qd, rn, rm, tcg_constant_i32(a->imm));
store_reg(s, a->rn, rn);
mve_update_eci(s);
return true;
qn = mve_qreg_ptr(a->qn);
qm = mve_qreg_ptr(a->qm);
- fn(cpu_env, qn, qm);
+ fn(tcg_env, qn, qm);
if (a->mask) {
/* VPT */
gen_vpst(s, a->mask);
} else {
rm = load_reg(s, a->rm);
}
- fn(cpu_env, qn, rm);
+ fn(tcg_env, qn, rm);
if (a->mask) {
/* VPT */
gen_vpst(s, a->mask);
qm = mve_qreg_ptr(a->qm);
rda = load_reg(s, a->rda);
- fn(rda, cpu_env, qm, rda);
+ fn(rda, tcg_env, qm, rda);
store_reg(s, a->rda, rda);
mve_update_eci(s);
return true;
qm = mve_qreg_ptr(a->qm);
qn = mve_qreg_ptr(a->qn);
rda = load_reg(s, a->rda);
- fn(rda, cpu_env, qn, qm, rda);
+ fn(rda, tcg_env, qn, qm, rda);
store_reg(s, a->rda, rda);
mve_update_eci(s);
return true;
static TCGv_ptr vfp_reg_ptr(bool dp, int reg)
{
TCGv_ptr ret = tcg_temp_new_ptr();
- tcg_gen_addi_ptr(ret, cpu_env, vfp_reg_offset(dp, reg));
+ tcg_gen_addi_ptr(ret, tcg_env, vfp_reg_offset(dp, reg));
return ret;
}
switch (mop) {
case MO_UB:
- tcg_gen_ld8u_i32(var, cpu_env, offset);
+ tcg_gen_ld8u_i32(var, tcg_env, offset);
break;
case MO_UW:
- tcg_gen_ld16u_i32(var, cpu_env, offset);
+ tcg_gen_ld16u_i32(var, tcg_env, offset);
break;
case MO_UL:
- tcg_gen_ld_i32(var, cpu_env, offset);
+ tcg_gen_ld_i32(var, tcg_env, offset);
break;
default:
g_assert_not_reached();
switch (mop) {
case MO_UB:
- tcg_gen_ld8u_i64(var, cpu_env, offset);
+ tcg_gen_ld8u_i64(var, tcg_env, offset);
break;
case MO_UW:
- tcg_gen_ld16u_i64(var, cpu_env, offset);
+ tcg_gen_ld16u_i64(var, tcg_env, offset);
break;
case MO_UL:
- tcg_gen_ld32u_i64(var, cpu_env, offset);
+ tcg_gen_ld32u_i64(var, tcg_env, offset);
break;
case MO_UQ:
- tcg_gen_ld_i64(var, cpu_env, offset);
+ tcg_gen_ld_i64(var, tcg_env, offset);
break;
default:
g_assert_not_reached();
switch (size) {
case MO_8:
- tcg_gen_st8_i32(var, cpu_env, offset);
+ tcg_gen_st8_i32(var, tcg_env, offset);
break;
case MO_16:
- tcg_gen_st16_i32(var, cpu_env, offset);
+ tcg_gen_st16_i32(var, tcg_env, offset);
break;
case MO_32:
- tcg_gen_st_i32(var, cpu_env, offset);
+ tcg_gen_st_i32(var, tcg_env, offset);
break;
default:
g_assert_not_reached();
switch (size) {
case MO_8:
- tcg_gen_st8_i64(var, cpu_env, offset);
+ tcg_gen_st8_i64(var, tcg_env, offset);
break;
case MO_16:
- tcg_gen_st16_i64(var, cpu_env, offset);
+ tcg_gen_st16_i64(var, tcg_env, offset);
break;
case MO_32:
- tcg_gen_st32_i64(var, cpu_env, offset);
+ tcg_gen_st32_i64(var, tcg_env, offset);
break;
case MO_64:
- tcg_gen_st_i64(var, cpu_env, offset);
+ tcg_gen_st_i64(var, tcg_env, offset);
break;
default:
g_assert_not_reached();
tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
vfp_reg_offset(a->q, a->vn),
vfp_reg_offset(a->q, a->vm),
- cpu_env, opr_sz, opr_sz, a->s, /* is_2 == 0 */
+ tcg_env, opr_sz, opr_sz, a->s, /* is_2 == 0 */
gen_helper_gvec_fmlal_a32);
return true;
}
tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
vfp_reg_offset(a->q, a->vn),
vfp_reg_offset(a->q, a->rm),
- cpu_env, opr_sz, opr_sz,
+ tcg_env, opr_sz, opr_sz,
(a->index << 2) | a->s, /* is_2 == 0 */
gen_helper_gvec_fmlal_idx_a32);
return true;
#define DO_3SAME_64_ENV(INSN, FUNC) \
static void gen_##INSN##_elt(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m) \
{ \
- FUNC(d, cpu_env, n, m); \
+ FUNC(d, tcg_env, n, m); \
} \
DO_3SAME_64(INSN, gen_##INSN##_elt)
}
/*
- * Some helper functions need to be passed the cpu_env. In order
+ * Some helper functions need to be passed the tcg_env. In order
* to use those with the gvec APIs like tcg_gen_gvec_3() we need
* to create wrapper functions whose prototype is a NeonGenTwoOpFn()
* and which call a NeonGenTwoOpEnvFn().
#define WRAP_ENV_FN(WRAPNAME, FUNC) \
static void WRAPNAME(TCGv_i32 d, TCGv_i32 n, TCGv_i32 m) \
{ \
- FUNC(d, cpu_env, n, m); \
+ FUNC(d, tcg_env, n, m); \
}
#define DO_3SAME_32_ENV(INSN, FUNC) \
{
/*
* 2-reg-and-shift operations, size == 3 case, where the
- * function needs to be passed cpu_env.
+ * function needs to be passed tcg_env.
*/
TCGv_i64 constimm;
int pass;
TCGv_i64 tmp = tcg_temp_new_i64();
read_neon_element64(tmp, a->vm, pass, MO_64);
- fn(tmp, cpu_env, tmp, constimm);
+ fn(tmp, tcg_env, tmp, constimm);
write_neon_element64(tmp, a->vd, pass, MO_64);
}
return true;
{
/*
* 2-reg-and-shift operations, size < 3 case, where the
- * helper needs to be passed cpu_env.
+ * helper needs to be passed tcg_env.
*/
TCGv_i32 constimm, tmp;
int pass;
for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
read_neon_element32(tmp, a->vm, pass, MO_32);
- fn(tmp, cpu_env, tmp, constimm);
+ fn(tmp, tcg_env, tmp, constimm);
write_neon_element32(tmp, a->vd, pass, MO_32);
}
return true;
read_neon_element64(rm2, a->vm, 1, MO_64);
shiftfn(rm1, rm1, constimm);
- narrowfn(rd, cpu_env, rm1);
+ narrowfn(rd, tcg_env, rm1);
write_neon_element32(rd, a->vd, 0, MO_32);
shiftfn(rm2, rm2, constimm);
- narrowfn(rd, cpu_env, rm2);
+ narrowfn(rd, tcg_env, rm2);
write_neon_element32(rd, a->vd, 1, MO_32);
return true;
tcg_gen_concat_i32_i64(rtmp, rm1, rm2);
- narrowfn(rm1, cpu_env, rtmp);
+ narrowfn(rm1, tcg_env, rtmp);
write_neon_element32(rm1, a->vd, 0, MO_32);
shiftfn(rm3, rm3, constimm);
tcg_gen_concat_i32_i64(rtmp, rm3, rm4);
- narrowfn(rm3, cpu_env, rtmp);
+ narrowfn(rm3, tcg_env, rtmp);
write_neon_element32(rm3, a->vd, 1, MO_32);
return true;
}
static void gen_VQDMULL_16(TCGv_i64 rd, TCGv_i32 rn, TCGv_i32 rm)
{
gen_helper_neon_mull_s16(rd, rn, rm);
- gen_helper_neon_addl_saturate_s32(rd, cpu_env, rd, rd);
+ gen_helper_neon_addl_saturate_s32(rd, tcg_env, rd, rd);
}
static void gen_VQDMULL_32(TCGv_i64 rd, TCGv_i32 rn, TCGv_i32 rm)
{
gen_mull_s32(rd, rn, rm);
- gen_helper_neon_addl_saturate_s64(rd, cpu_env, rd, rd);
+ gen_helper_neon_addl_saturate_s64(rd, tcg_env, rd, rd);
}
static bool trans_VQDMULL_3d(DisasContext *s, arg_3diff *a)
static void gen_VQDMLAL_acc_16(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm)
{
- gen_helper_neon_addl_saturate_s32(rd, cpu_env, rn, rm);
+ gen_helper_neon_addl_saturate_s32(rd, tcg_env, rn, rm);
}
static void gen_VQDMLAL_acc_32(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm)
{
- gen_helper_neon_addl_saturate_s64(rd, cpu_env, rn, rm);
+ gen_helper_neon_addl_saturate_s64(rd, tcg_env, rn, rm);
}
static bool trans_VQDMLAL_3d(DisasContext *s, arg_3diff *a)
static void gen_VQDMLSL_acc_16(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm)
{
gen_helper_neon_negl_u32(rm, rm);
- gen_helper_neon_addl_saturate_s32(rd, cpu_env, rn, rm);
+ gen_helper_neon_addl_saturate_s32(rd, tcg_env, rn, rm);
}
static void gen_VQDMLSL_acc_32(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm)
{
tcg_gen_neg_i64(rm, rm);
- gen_helper_neon_addl_saturate_s64(rd, cpu_env, rn, rm);
+ gen_helper_neon_addl_saturate_s64(rd, tcg_env, rn, rm);
}
static bool trans_VQDMLSL_3d(DisasContext *s, arg_3diff *a)
for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
read_neon_element32(rn, a->vn, pass, MO_32);
read_neon_element32(rd, a->vd, pass, MO_32);
- opfn(rd, cpu_env, rn, scalar, rd);
+ opfn(rd, tcg_env, rn, scalar, rd);
write_neon_element32(rd, a->vd, pass, MO_32);
}
return true;
val = tcg_temp_new_i64();
read_neon_element64(val, a->vm, 0, MO_64);
- gen_helper_neon_tbl(val, cpu_env, desc, val, def);
+ gen_helper_neon_tbl(val, tcg_env, desc, val, def);
write_neon_element64(val, a->vd, 0, MO_64);
return true;
}
rd1 = tcg_temp_new_i32();
read_neon_element64(rm, a->vm, 0, MO_64);
- narrowfn(rd0, cpu_env, rm);
+ narrowfn(rd0, tcg_env, rm);
read_neon_element64(rm, a->vm, 1, MO_64);
- narrowfn(rd1, cpu_env, rm);
+ narrowfn(rd1, tcg_env, rm);
write_neon_element32(rd0, a->vd, 0, MO_32);
write_neon_element32(rd1, a->vd, 1, MO_32);
return true;
#define WRAP_1OP_ENV_FN(WRAPNAME, FUNC) \
static void WRAPNAME(TCGv_i32 d, TCGv_i32 m) \
{ \
- FUNC(d, cpu_env, m); \
+ FUNC(d, tcg_env, m); \
}
WRAP_1OP_ENV_FN(gen_VQABS_s8, gen_helper_neon_qabs_s8)
/* Add the byte offset to env to produce the final pointer. */
addr = tcg_temp_new_ptr();
tcg_gen_ext_i32_ptr(addr, tmp);
- tcg_gen_add_ptr(addr, addr, cpu_env);
+ tcg_gen_add_ptr(addr, addr, tcg_env);
return addr;
}
offset = tile * sizeof(ARMVectorReg) + offsetof(CPUARMState, zarray);
- tcg_gen_addi_ptr(addr, cpu_env, offset);
+ tcg_gen_addi_ptr(addr, tcg_env, offset);
return addr;
}
return false;
}
if (sme_za_enabled_check(s)) {
- gen_helper_sme_zero(cpu_env, tcg_constant_i32(a->imm),
+ gen_helper_sme_zero(tcg_env, tcg_constant_i32(a->imm),
tcg_constant_i32(streaming_vec_reg_size(s)));
}
return true;
svl = streaming_vec_reg_size(s);
desc = simd_desc(svl, svl, desc);
- fns[a->esz][be][a->v][mte][a->st](cpu_env, t_za, t_pg, addr,
+ fns[a->esz][be][a->v][mte][a->st](tcg_env, t_za, t_pg, addr,
tcg_constant_i32(desc));
return true;
}
TCGv_ptr gptr = tcg_temp_new_ptr();
TCGv_i32 t = tcg_temp_new_i32();
- tcg_gen_addi_ptr(dptr, cpu_env, dofs);
- tcg_gen_addi_ptr(gptr, cpu_env, gofs);
+ tcg_gen_addi_ptr(dptr, tcg_env, dofs);
+ tcg_gen_addi_ptr(gptr, tcg_env, gofs);
gen_helper_sve_predtest(t, dptr, gptr, tcg_constant_i32(words));
t_zn = tcg_temp_new_ptr();
t_pg = tcg_temp_new_ptr();
- tcg_gen_addi_ptr(t_zn, cpu_env, vec_full_reg_offset(s, a->rn));
- tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->pg));
+ tcg_gen_addi_ptr(t_zn, tcg_env, vec_full_reg_offset(s, a->rn));
+ tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, a->pg));
fn(temp, t_zn, t_pg, desc);
write_fp_dreg(s, a->rd, temp);
desc = tcg_constant_i32(simd_desc(vsz, vsz, 0));
t_zd = tcg_temp_new_ptr();
- tcg_gen_addi_ptr(t_zd, cpu_env, vec_full_reg_offset(s, rd));
+ tcg_gen_addi_ptr(t_zd, tcg_env, vec_full_reg_offset(s, rd));
if (esz == 3) {
gen_helper_sve_index_d(t_zd, start, incr, desc);
} else {
TCGv_i64 pm = tcg_temp_new_i64();
TCGv_i64 pg = tcg_temp_new_i64();
- tcg_gen_ld_i64(pn, cpu_env, nofs);
- tcg_gen_ld_i64(pm, cpu_env, mofs);
- tcg_gen_ld_i64(pg, cpu_env, gofs);
+ tcg_gen_ld_i64(pn, tcg_env, nofs);
+ tcg_gen_ld_i64(pm, tcg_env, mofs);
+ tcg_gen_ld_i64(pg, tcg_env, gofs);
gvec_op->fni8(pd, pn, pm, pg);
- tcg_gen_st_i64(pd, cpu_env, dofs);
+ tcg_gen_st_i64(pd, tcg_env, dofs);
do_predtest1(pd, pg);
} else {
TCGv_i64 pn = tcg_temp_new_i64();
TCGv_i64 pg = tcg_temp_new_i64();
- tcg_gen_ld_i64(pn, cpu_env, nofs);
- tcg_gen_ld_i64(pg, cpu_env, gofs);
+ tcg_gen_ld_i64(pn, tcg_env, nofs);
+ tcg_gen_ld_i64(pg, tcg_env, gofs);
do_predtest1(pn, pg);
} else {
do_predtest(s, nofs, gofs, words);
t = tcg_temp_new_i64();
if (fullsz <= 64) {
tcg_gen_movi_i64(t, lastword);
- tcg_gen_st_i64(t, cpu_env, ofs);
+ tcg_gen_st_i64(t, tcg_env, ofs);
goto done;
}
tcg_gen_movi_i64(t, word);
for (i = 0; i < QEMU_ALIGN_DOWN(setsz, 8); i += 8) {
- tcg_gen_st_i64(t, cpu_env, ofs + i);
+ tcg_gen_st_i64(t, tcg_env, ofs + i);
}
if (lastword != word) {
tcg_gen_movi_i64(t, lastword);
- tcg_gen_st_i64(t, cpu_env, ofs + i);
+ tcg_gen_st_i64(t, tcg_env, ofs + i);
i += 8;
}
if (i < fullsz) {
tcg_gen_movi_i64(t, 0);
for (; i < fullsz; i += 8) {
- tcg_gen_st_i64(t, cpu_env, ofs + i);
+ tcg_gen_st_i64(t, tcg_env, ofs + i);
}
}
desc = FIELD_DP32(desc, PREDDESC, OPRSZ, pred_full_reg_size(s));
desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz);
- tcg_gen_addi_ptr(t_pd, cpu_env, pred_full_reg_offset(s, a->rd));
- tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->rn));
+ tcg_gen_addi_ptr(t_pd, tcg_env, pred_full_reg_offset(s, a->rd));
+ tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, a->rn));
t = tcg_temp_new_i32();
gen_fn(t, t_pd, t_pg, tcg_constant_i32(desc));
dptr = tcg_temp_new_ptr();
nptr = tcg_temp_new_ptr();
- tcg_gen_addi_ptr(dptr, cpu_env, vec_full_reg_offset(s, rd));
- tcg_gen_addi_ptr(nptr, cpu_env, vec_full_reg_offset(s, rn));
+ tcg_gen_addi_ptr(dptr, tcg_env, vec_full_reg_offset(s, rd));
+ tcg_gen_addi_ptr(nptr, tcg_env, vec_full_reg_offset(s, rn));
desc = tcg_constant_i32(simd_desc(vsz, vsz, 0));
switch (esz) {
TCGv_ptr t_zn = tcg_temp_new_ptr();
TCGv_ptr t_pg = tcg_temp_new_ptr();
- tcg_gen_addi_ptr(t_zd, cpu_env, vec_full_reg_offset(s, rd));
- tcg_gen_addi_ptr(t_zn, cpu_env, vec_full_reg_offset(s, rn));
- tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg));
+ tcg_gen_addi_ptr(t_zd, tcg_env, vec_full_reg_offset(s, rd));
+ tcg_gen_addi_ptr(t_zn, tcg_env, vec_full_reg_offset(s, rn));
+ tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, pg));
fns[esz](t_zd, t_zn, t_pg, val, desc);
}
TCGv_ptr t_zd = tcg_temp_new_ptr();
TCGv_ptr t_zn = tcg_temp_new_ptr();
- tcg_gen_addi_ptr(t_zd, cpu_env, vec_full_reg_offset(s, a->rd));
- tcg_gen_addi_ptr(t_zn, cpu_env, vec_full_reg_offset(s, a->rn));
+ tcg_gen_addi_ptr(t_zd, tcg_env, vec_full_reg_offset(s, a->rd));
+ tcg_gen_addi_ptr(t_zn, tcg_env, vec_full_reg_offset(s, a->rn));
fns[a->esz](t_zd, t_zn, val, desc);
}
}
if (sve_access_check(s)) {
TCGv_i64 t = tcg_temp_new_i64();
- tcg_gen_ld_i64(t, cpu_env, vec_reg_offset(s, a->rm, 0, MO_64));
+ tcg_gen_ld_i64(t, tcg_env, vec_reg_offset(s, a->rm, 0, MO_64));
do_insr_i64(s, a, t);
}
return true;
desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz);
desc = FIELD_DP32(desc, PREDDESC, DATA, high_odd);
- tcg_gen_addi_ptr(t_d, cpu_env, pred_full_reg_offset(s, a->rd));
- tcg_gen_addi_ptr(t_n, cpu_env, pred_full_reg_offset(s, a->rn));
- tcg_gen_addi_ptr(t_m, cpu_env, pred_full_reg_offset(s, a->rm));
+ tcg_gen_addi_ptr(t_d, tcg_env, pred_full_reg_offset(s, a->rd));
+ tcg_gen_addi_ptr(t_n, tcg_env, pred_full_reg_offset(s, a->rn));
+ tcg_gen_addi_ptr(t_m, tcg_env, pred_full_reg_offset(s, a->rm));
fn(t_d, t_n, t_m, tcg_constant_i32(desc));
return true;
TCGv_ptr t_n = tcg_temp_new_ptr();
uint32_t desc = 0;
- tcg_gen_addi_ptr(t_d, cpu_env, pred_full_reg_offset(s, a->rd));
- tcg_gen_addi_ptr(t_n, cpu_env, pred_full_reg_offset(s, a->rn));
+ tcg_gen_addi_ptr(t_d, tcg_env, pred_full_reg_offset(s, a->rd));
+ tcg_gen_addi_ptr(t_n, tcg_env, pred_full_reg_offset(s, a->rn));
desc = FIELD_DP32(desc, PREDDESC, OPRSZ, vsz);
desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz);
desc = FIELD_DP32(desc, PREDDESC, OPRSZ, pred_full_reg_size(s));
desc = FIELD_DP32(desc, PREDDESC, ESZ, esz);
- tcg_gen_addi_ptr(t_p, cpu_env, pred_full_reg_offset(s, pg));
+ tcg_gen_addi_ptr(t_p, tcg_env, pred_full_reg_offset(s, pg));
gen_helper_sve_last_active_element(ret, t_p, tcg_constant_i32(desc));
}
}
#endif
tcg_gen_ext_i32_ptr(p, last);
- tcg_gen_add_ptr(p, p, cpu_env);
+ tcg_gen_add_ptr(p, p, tcg_env);
return load_esz(p, vec_full_reg_offset(s, rm), esz);
}
}
/* The conceit here is that while last < 0 indicates not found, after
- * adjusting for cpu_env->vfp.zregs[rm], it is still a valid address
+ * adjusting for tcg_env->vfp.zregs[rm], it is still a valid address
* from which we can load garbage. We then discard the garbage with
* a conditional move.
*/
if (sve_access_check(s)) {
int esz = a->esz;
int ofs = vec_reg_offset(s, a->rd, 0, esz);
- TCGv_i64 reg = load_esz(cpu_env, ofs, esz);
+ TCGv_i64 reg = load_esz(tcg_env, ofs, esz);
do_clast_scalar(s, esz, a->pg, a->rn, before, reg);
write_fp_dreg(s, a->rd, reg);
}
if (sve_access_check(s)) {
int ofs = vec_reg_offset(s, a->rn, 0, a->esz);
- TCGv_i64 t = load_esz(cpu_env, ofs, a->esz);
+ TCGv_i64 t = load_esz(tcg_env, ofs, a->esz);
do_cpy_m(s, a->esz, a->rd, a->rd, a->pg, t);
}
return true;
zm = tcg_temp_new_ptr();
pg = tcg_temp_new_ptr();
- tcg_gen_addi_ptr(pd, cpu_env, pred_full_reg_offset(s, a->rd));
- tcg_gen_addi_ptr(zn, cpu_env, vec_full_reg_offset(s, a->rn));
- tcg_gen_addi_ptr(zm, cpu_env, vec_full_reg_offset(s, a->rm));
- tcg_gen_addi_ptr(pg, cpu_env, pred_full_reg_offset(s, a->pg));
+ tcg_gen_addi_ptr(pd, tcg_env, pred_full_reg_offset(s, a->rd));
+ tcg_gen_addi_ptr(zn, tcg_env, vec_full_reg_offset(s, a->rn));
+ tcg_gen_addi_ptr(zm, tcg_env, vec_full_reg_offset(s, a->rm));
+ tcg_gen_addi_ptr(pg, tcg_env, pred_full_reg_offset(s, a->pg));
gen_fn(t, pd, zn, zm, pg, tcg_constant_i32(simd_desc(vsz, vsz, 0)));
zn = tcg_temp_new_ptr();
pg = tcg_temp_new_ptr();
- tcg_gen_addi_ptr(pd, cpu_env, pred_full_reg_offset(s, a->rd));
- tcg_gen_addi_ptr(zn, cpu_env, vec_full_reg_offset(s, a->rn));
- tcg_gen_addi_ptr(pg, cpu_env, pred_full_reg_offset(s, a->pg));
+ tcg_gen_addi_ptr(pd, tcg_env, pred_full_reg_offset(s, a->rd));
+ tcg_gen_addi_ptr(zn, tcg_env, vec_full_reg_offset(s, a->rn));
+ tcg_gen_addi_ptr(pg, tcg_env, pred_full_reg_offset(s, a->pg));
gen_fn(t, pd, zn, pg, tcg_constant_i32(simd_desc(vsz, vsz, a->imm)));
TCGv_ptr g = tcg_temp_new_ptr();
TCGv_i32 desc = tcg_constant_i32(FIELD_DP32(0, PREDDESC, OPRSZ, vsz));
- tcg_gen_addi_ptr(d, cpu_env, pred_full_reg_offset(s, a->rd));
- tcg_gen_addi_ptr(n, cpu_env, pred_full_reg_offset(s, a->rn));
- tcg_gen_addi_ptr(m, cpu_env, pred_full_reg_offset(s, a->rm));
- tcg_gen_addi_ptr(g, cpu_env, pred_full_reg_offset(s, a->pg));
+ tcg_gen_addi_ptr(d, tcg_env, pred_full_reg_offset(s, a->rd));
+ tcg_gen_addi_ptr(n, tcg_env, pred_full_reg_offset(s, a->rn));
+ tcg_gen_addi_ptr(m, tcg_env, pred_full_reg_offset(s, a->rm));
+ tcg_gen_addi_ptr(g, tcg_env, pred_full_reg_offset(s, a->pg));
if (a->s) {
TCGv_i32 t = tcg_temp_new_i32();
TCGv_ptr g = tcg_temp_new_ptr();
TCGv_i32 desc = tcg_constant_i32(FIELD_DP32(0, PREDDESC, OPRSZ, vsz));
- tcg_gen_addi_ptr(d, cpu_env, pred_full_reg_offset(s, a->rd));
- tcg_gen_addi_ptr(n, cpu_env, pred_full_reg_offset(s, a->rn));
- tcg_gen_addi_ptr(g, cpu_env, pred_full_reg_offset(s, a->pg));
+ tcg_gen_addi_ptr(d, tcg_env, pred_full_reg_offset(s, a->rd));
+ tcg_gen_addi_ptr(n, tcg_env, pred_full_reg_offset(s, a->rn));
+ tcg_gen_addi_ptr(g, tcg_env, pred_full_reg_offset(s, a->pg));
if (a->s) {
TCGv_i32 t = tcg_temp_new_i32();
if (psz <= 8) {
uint64_t psz_mask;
- tcg_gen_ld_i64(val, cpu_env, pred_full_reg_offset(s, pn));
+ tcg_gen_ld_i64(val, tcg_env, pred_full_reg_offset(s, pn));
if (pn != pg) {
TCGv_i64 g = tcg_temp_new_i64();
- tcg_gen_ld_i64(g, cpu_env, pred_full_reg_offset(s, pg));
+ tcg_gen_ld_i64(g, tcg_env, pred_full_reg_offset(s, pg));
tcg_gen_and_i64(val, val, g);
}
desc = FIELD_DP32(desc, PREDDESC, OPRSZ, psz);
desc = FIELD_DP32(desc, PREDDESC, ESZ, esz);
- tcg_gen_addi_ptr(t_pn, cpu_env, pred_full_reg_offset(s, pn));
- tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg));
+ tcg_gen_addi_ptr(t_pn, tcg_env, pred_full_reg_offset(s, pn));
+ tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, pg));
gen_helper_sve_cntp(val, t_pn, t_pg, tcg_constant_i32(desc));
}
desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz);
ptr = tcg_temp_new_ptr();
- tcg_gen_addi_ptr(ptr, cpu_env, pred_full_reg_offset(s, a->rd));
+ tcg_gen_addi_ptr(ptr, tcg_env, pred_full_reg_offset(s, a->rd));
if (a->lt) {
gen_helper_sve_whilel(t2, ptr, t2, tcg_constant_i32(desc));
desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz);
ptr = tcg_temp_new_ptr();
- tcg_gen_addi_ptr(ptr, cpu_env, pred_full_reg_offset(s, a->rd));
+ tcg_gen_addi_ptr(ptr, tcg_env, pred_full_reg_offset(s, a->rd));
gen_helper_sve_whilel(t2, ptr, t2, tcg_constant_i32(desc));
do_pred_flags(t2);
t_zn = tcg_temp_new_ptr();
t_pg = tcg_temp_new_ptr();
- tcg_gen_addi_ptr(t_zn, cpu_env, vec_full_reg_offset(s, a->rn));
- tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->pg));
+ tcg_gen_addi_ptr(t_zn, tcg_env, vec_full_reg_offset(s, a->rn));
+ tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, a->pg));
status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
fn(temp, t_zn, t_pg, status, t_desc);
return true;
}
- t_val = load_esz(cpu_env, vec_reg_offset(s, a->rn, 0, a->esz), a->esz);
+ t_val = load_esz(tcg_env, vec_reg_offset(s, a->rn, 0, a->esz), a->esz);
t_rm = tcg_temp_new_ptr();
t_pg = tcg_temp_new_ptr();
- tcg_gen_addi_ptr(t_rm, cpu_env, vec_full_reg_offset(s, a->rm));
- tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->pg));
+ tcg_gen_addi_ptr(t_rm, tcg_env, vec_full_reg_offset(s, a->rm));
+ tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, a->pg));
t_fpst = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
t_desc = tcg_constant_i32(simd_desc(vsz, vsz, 0));
t_zd = tcg_temp_new_ptr();
t_zn = tcg_temp_new_ptr();
t_pg = tcg_temp_new_ptr();
- tcg_gen_addi_ptr(t_zd, cpu_env, vec_full_reg_offset(s, zd));
- tcg_gen_addi_ptr(t_zn, cpu_env, vec_full_reg_offset(s, zn));
- tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg));
+ tcg_gen_addi_ptr(t_zd, tcg_env, vec_full_reg_offset(s, zd));
+ tcg_gen_addi_ptr(t_zn, tcg_env, vec_full_reg_offset(s, zn));
+ tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, pg));
status = fpstatus_ptr(is_fp16 ? FPST_FPCR_F16 : FPST_FPCR);
desc = tcg_constant_i32(simd_desc(vsz, vsz, 0));
/*
* Predicate register loads can be any multiple of 2.
- * Note that we still store the entire 64-bit unit into cpu_env.
+ * Note that we still store the entire 64-bit unit into tcg_env.
*/
if (len_remain >= 8) {
t0 = tcg_temp_new_i64();
if (sve_access_check(s)) {
int size = vec_full_reg_size(s);
int off = vec_full_reg_offset(s, a->rd);
- gen_sve_ldr(s, cpu_env, off, size, a->rn, a->imm * size);
+ gen_sve_ldr(s, tcg_env, off, size, a->rn, a->imm * size);
}
return true;
}
if (sve_access_check(s)) {
int size = pred_full_reg_size(s);
int off = pred_full_reg_offset(s, a->rd);
- gen_sve_ldr(s, cpu_env, off, size, a->rn, a->imm * size);
+ gen_sve_ldr(s, tcg_env, off, size, a->rn, a->imm * size);
}
return true;
}
if (sve_access_check(s)) {
int size = vec_full_reg_size(s);
int off = vec_full_reg_offset(s, a->rd);
- gen_sve_str(s, cpu_env, off, size, a->rn, a->imm * size);
+ gen_sve_str(s, tcg_env, off, size, a->rn, a->imm * size);
}
return true;
}
if (sve_access_check(s)) {
int size = pred_full_reg_size(s);
int off = pred_full_reg_offset(s, a->rd);
- gen_sve_str(s, cpu_env, off, size, a->rn, a->imm * size);
+ gen_sve_str(s, tcg_env, off, size, a->rn, a->imm * size);
}
return true;
}
desc = simd_desc(vsz, vsz, zt | desc);
t_pg = tcg_temp_new_ptr();
- tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg));
- fn(cpu_env, t_pg, addr, tcg_constant_i32(desc));
+ tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, pg));
+ fn(tcg_env, t_pg, addr, tcg_constant_i32(desc));
}
/* Indexed by [mte][be][dtype][nreg] */
#if HOST_BIG_ENDIAN
poff += 6;
#endif
- tcg_gen_ld16u_i64(tmp, cpu_env, poff);
+ tcg_gen_ld16u_i64(tmp, tcg_env, poff);
poff = offsetof(CPUARMState, vfp.preg_tmp);
- tcg_gen_st_i64(tmp, cpu_env, poff);
+ tcg_gen_st_i64(tmp, tcg_env, poff);
}
t_pg = tcg_temp_new_ptr();
- tcg_gen_addi_ptr(t_pg, cpu_env, poff);
+ tcg_gen_addi_ptr(t_pg, tcg_env, poff);
gen_helper_gvec_mem *fn
= ldr_fns[s->mte_active[0]][s->be_data == MO_BE][dtype][0];
- fn(cpu_env, t_pg, addr, tcg_constant_i32(simd_desc(16, 16, zt)));
+ fn(tcg_env, t_pg, addr, tcg_constant_i32(simd_desc(16, 16, zt)));
/* Replicate that first quadword. */
if (vsz > 16) {
#if HOST_BIG_ENDIAN
poff += 4;
#endif
- tcg_gen_ld32u_i64(tmp, cpu_env, poff);
+ tcg_gen_ld32u_i64(tmp, tcg_env, poff);
poff = offsetof(CPUARMState, vfp.preg_tmp);
- tcg_gen_st_i64(tmp, cpu_env, poff);
+ tcg_gen_st_i64(tmp, tcg_env, poff);
}
t_pg = tcg_temp_new_ptr();
- tcg_gen_addi_ptr(t_pg, cpu_env, poff);
+ tcg_gen_addi_ptr(t_pg, tcg_env, poff);
gen_helper_gvec_mem *fn
= ldr_fns[s->mte_active[0]][s->be_data == MO_BE][dtype][0];
- fn(cpu_env, t_pg, addr, tcg_constant_i32(simd_desc(32, 32, zt)));
+ fn(tcg_env, t_pg, addr, tcg_constant_i32(simd_desc(32, 32, zt)));
/*
* Replicate that first octaword.
*/
uint64_t psz_mask = MAKE_64BIT_MASK(0, psz * 8);
temp = tcg_temp_new_i64();
- tcg_gen_ld_i64(temp, cpu_env, pred_full_reg_offset(s, a->pg));
+ tcg_gen_ld_i64(temp, tcg_env, pred_full_reg_offset(s, a->pg));
tcg_gen_andi_i64(temp, temp, pred_esz_masks[esz] & psz_mask);
tcg_gen_brcondi_i64(TCG_COND_EQ, temp, 0, over);
} else {
}
desc = simd_desc(vsz, vsz, desc | scale);
- tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg));
- tcg_gen_addi_ptr(t_zm, cpu_env, vec_full_reg_offset(s, zm));
- tcg_gen_addi_ptr(t_zt, cpu_env, vec_full_reg_offset(s, zt));
- fn(cpu_env, t_zt, t_pg, t_zm, scalar, tcg_constant_i32(desc));
+ tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, pg));
+ tcg_gen_addi_ptr(t_zm, tcg_env, vec_full_reg_offset(s, zm));
+ tcg_gen_addi_ptr(t_zt, tcg_env, vec_full_reg_offset(s, zt));
+ fn(tcg_env, t_zt, t_pg, t_zm, scalar, tcg_constant_i32(desc));
}
/* Indexed by [mte][be][ff][xs][u][msz]. */
{
return gen_gvec_ptr_zzzz(s, gen_helper_sve2_fmlal_zzzw_s,
a->rd, a->rn, a->rm, a->ra,
- (sel << 1) | sub, cpu_env);
+ (sel << 1) | sub, tcg_env);
}
TRANS_FEAT(FMLALB_zzzw, aa64_sve2, do_FMLAL_zzzw, a, false, false)
{
return gen_gvec_ptr_zzzz(s, gen_helper_sve2_fmlal_zzxw_s,
a->rd, a->rn, a->rm, a->ra,
- (a->index << 2) | (sel << 1) | sub, cpu_env);
+ (a->index << 2) | (sel << 1) | sub, tcg_env);
}
TRANS_FEAT(FMLALB_zzxw, aa64_sve2, do_FMLAL_zzxw, a, false, false)
/* Load the predicate word. */
tcg_gen_trunc_i64_ptr(ptr, didx);
- tcg_gen_add_ptr(ptr, ptr, cpu_env);
+ tcg_gen_add_ptr(ptr, ptr, tcg_env);
tcg_gen_ld8u_i64(tmp, ptr, pred_full_reg_offset(s, a->pm));
/* Extract the predicate bit and replicate to MO_64. */
static inline void vfp_load_reg64(TCGv_i64 var, int reg)
{
- tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(true, reg));
+ tcg_gen_ld_i64(var, tcg_env, vfp_reg_offset(true, reg));
}
static inline void vfp_store_reg64(TCGv_i64 var, int reg)
{
- tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(true, reg));
+ tcg_gen_st_i64(var, tcg_env, vfp_reg_offset(true, reg));
}
static inline void vfp_load_reg32(TCGv_i32 var, int reg)
{
- tcg_gen_ld_i32(var, cpu_env, vfp_reg_offset(false, reg));
+ tcg_gen_ld_i32(var, tcg_env, vfp_reg_offset(false, reg));
}
static inline void vfp_store_reg32(TCGv_i32 var, int reg)
{
- tcg_gen_st_i32(var, cpu_env, vfp_reg_offset(false, reg));
+ tcg_gen_st_i32(var, tcg_env, vfp_reg_offset(false, reg));
}
/*
if (translator_io_start(&s->base)) {
s->base.is_jmp = DISAS_UPDATE_EXIT;
}
- gen_helper_v7m_preserve_fp_state(cpu_env);
+ gen_helper_v7m_preserve_fp_state(tcg_env);
/*
* If the preserve_fp_state helper doesn't throw an exception
* then it will clear LSPACT; we don't need to repeat this for
uint32_t bits = R_V7M_CONTROL_FPCA_MASK;
fpscr = load_cpu_field(v7m.fpdscr[s->v8m_secure]);
- gen_helper_vfp_set_fpscr(cpu_env, fpscr);
+ gen_helper_vfp_set_fpscr(tcg_env, fpscr);
if (dc_isar_feature(aa32_mve, s)) {
store_cpu_field(tcg_constant_i32(0), v7m.vpr);
}
if (s->current_el == 1) {
gen_set_condexec(s);
gen_update_pc(s, 0);
- gen_helper_check_hcr_el2_trap(cpu_env,
+ gen_helper_check_hcr_el2_trap(tcg_env,
tcg_constant_i32(a->rt),
tcg_constant_i32(a->reg));
}
tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK);
} else {
tmp = tcg_temp_new_i32();
- gen_helper_vfp_get_fpscr(tmp, cpu_env);
+ gen_helper_vfp_get_fpscr(tmp, tcg_env);
}
break;
default:
break;
case ARM_VFP_FPSCR:
tmp = load_reg(s, a->rt);
- gen_helper_vfp_set_fpscr(cpu_env, tmp);
+ gen_helper_vfp_set_fpscr(tcg_env, tmp);
gen_lookup_tb(s);
break;
case ARM_VFP_FPEXC:
* value is above, it is UNKNOWN whether the limit check
* triggers; we choose to trigger.
*/
- gen_helper_v8m_stackcheck(cpu_env, addr);
+ gen_helper_v8m_stackcheck(tcg_env, addr);
}
offset = 4;
* value is above, it is UNKNOWN whether the limit check
* triggers; we choose to trigger.
*/
- gen_helper_v8m_stackcheck(cpu_env, addr);
+ gen_helper_v8m_stackcheck(tcg_env, addr);
}
offset = 8;
static void gen_VSQRT_hp(TCGv_i32 vd, TCGv_i32 vm)
{
- gen_helper_vfp_sqrth(vd, vm, cpu_env);
+ gen_helper_vfp_sqrth(vd, vm, tcg_env);
}
static void gen_VSQRT_sp(TCGv_i32 vd, TCGv_i32 vm)
{
- gen_helper_vfp_sqrts(vd, vm, cpu_env);
+ gen_helper_vfp_sqrts(vd, vm, tcg_env);
}
static void gen_VSQRT_dp(TCGv_i64 vd, TCGv_i64 vm)
{
- gen_helper_vfp_sqrtd(vd, vm, cpu_env);
+ gen_helper_vfp_sqrtd(vd, vm, tcg_env);
}
DO_VFP_2OP(VSQRT, hp, gen_VSQRT_hp, aa32_fp16_arith)
}
if (a->e) {
- gen_helper_vfp_cmpeh(vd, vm, cpu_env);
+ gen_helper_vfp_cmpeh(vd, vm, tcg_env);
} else {
- gen_helper_vfp_cmph(vd, vm, cpu_env);
+ gen_helper_vfp_cmph(vd, vm, tcg_env);
}
return true;
}
}
if (a->e) {
- gen_helper_vfp_cmpes(vd, vm, cpu_env);
+ gen_helper_vfp_cmpes(vd, vm, tcg_env);
} else {
- gen_helper_vfp_cmps(vd, vm, cpu_env);
+ gen_helper_vfp_cmps(vd, vm, tcg_env);
}
return true;
}
}
if (a->e) {
- gen_helper_vfp_cmped(vd, vm, cpu_env);
+ gen_helper_vfp_cmped(vd, vm, tcg_env);
} else {
- gen_helper_vfp_cmpd(vd, vm, cpu_env);
+ gen_helper_vfp_cmpd(vd, vm, tcg_env);
}
return true;
}
ahp_mode = get_ahp_flag();
tmp = tcg_temp_new_i32();
/* The T bit tells us if we want the low or high 16 bits of Vm */
- tcg_gen_ld16u_i32(tmp, cpu_env, vfp_f16_offset(a->vm, a->t));
+ tcg_gen_ld16u_i32(tmp, tcg_env, vfp_f16_offset(a->vm, a->t));
gen_helper_vfp_fcvt_f16_to_f32(tmp, tmp, fpst, ahp_mode);
vfp_store_reg32(tmp, a->vd);
return true;
ahp_mode = get_ahp_flag();
tmp = tcg_temp_new_i32();
/* The T bit tells us if we want the low or high 16 bits of Vm */
- tcg_gen_ld16u_i32(tmp, cpu_env, vfp_f16_offset(a->vm, a->t));
+ tcg_gen_ld16u_i32(tmp, tcg_env, vfp_f16_offset(a->vm, a->t));
vd = tcg_temp_new_i64();
gen_helper_vfp_fcvt_f16_to_f64(vd, tmp, fpst, ahp_mode);
vfp_store_reg64(vd, a->vd);
vfp_load_reg32(tmp, a->vm);
gen_helper_bfcvt(tmp, tmp, fpst);
- tcg_gen_st16_i32(tmp, cpu_env, vfp_f16_offset(a->vd, a->t));
+ tcg_gen_st16_i32(tmp, tcg_env, vfp_f16_offset(a->vd, a->t));
return true;
}
vfp_load_reg32(tmp, a->vm);
gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp_mode);
- tcg_gen_st16_i32(tmp, cpu_env, vfp_f16_offset(a->vd, a->t));
+ tcg_gen_st16_i32(tmp, tcg_env, vfp_f16_offset(a->vd, a->t));
return true;
}
vfp_load_reg64(vm, a->vm);
gen_helper_vfp_fcvt_f64_to_f16(tmp, vm, fpst, ahp_mode);
- tcg_gen_st16_i32(tmp, cpu_env, vfp_f16_offset(a->vd, a->t));
+ tcg_gen_st16_i32(tmp, tcg_env, vfp_f16_offset(a->vd, a->t));
return true;
}
vm = tcg_temp_new_i32();
vd = tcg_temp_new_i64();
vfp_load_reg32(vm, a->vm);
- gen_helper_vfp_fcvtds(vd, vm, cpu_env);
+ gen_helper_vfp_fcvtds(vd, vm, tcg_env);
vfp_store_reg64(vd, a->vd);
return true;
}
vd = tcg_temp_new_i32();
vm = tcg_temp_new_i64();
vfp_load_reg64(vm, a->vm);
- gen_helper_vfp_fcvtsd(vd, vm, cpu_env);
+ gen_helper_vfp_fcvtsd(vd, vm, tcg_env);
vfp_store_reg32(vd, a->vd);
return true;
}
vm = tcg_temp_new_i64();
vd = tcg_temp_new_i32();
vfp_load_reg64(vm, a->vm);
- gen_helper_vjcvt(vd, vm, cpu_env);
+ gen_helper_vjcvt(vd, vm, tcg_env);
vfp_store_reg32(vd, a->vd);
return true;
}
int i;
for (i = 0; i < 16; i++) {
- cpu_R[i] = tcg_global_mem_new_i32(cpu_env,
+ cpu_R[i] = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUARMState, regs[i]),
regnames[i]);
}
- cpu_CF = tcg_global_mem_new_i32(cpu_env, offsetof(CPUARMState, CF), "CF");
- cpu_NF = tcg_global_mem_new_i32(cpu_env, offsetof(CPUARMState, NF), "NF");
- cpu_VF = tcg_global_mem_new_i32(cpu_env, offsetof(CPUARMState, VF), "VF");
- cpu_ZF = tcg_global_mem_new_i32(cpu_env, offsetof(CPUARMState, ZF), "ZF");
+ cpu_CF = tcg_global_mem_new_i32(tcg_env, offsetof(CPUARMState, CF), "CF");
+ cpu_NF = tcg_global_mem_new_i32(tcg_env, offsetof(CPUARMState, NF), "NF");
+ cpu_VF = tcg_global_mem_new_i32(tcg_env, offsetof(CPUARMState, VF), "VF");
+ cpu_ZF = tcg_global_mem_new_i32(tcg_env, offsetof(CPUARMState, ZF), "ZF");
- cpu_exclusive_addr = tcg_global_mem_new_i64(cpu_env,
+ cpu_exclusive_addr = tcg_global_mem_new_i64(tcg_env,
offsetof(CPUARMState, exclusive_addr), "exclusive_addr");
- cpu_exclusive_val = tcg_global_mem_new_i64(cpu_env,
+ cpu_exclusive_val = tcg_global_mem_new_i64(tcg_env,
offsetof(CPUARMState, exclusive_val), "exclusive_val");
a64_translate_init();
{
switch (size) {
case 1:
- tcg_gen_st8_i32(var, cpu_env, offset);
+ tcg_gen_st8_i32(var, tcg_env, offset);
break;
case 4:
- tcg_gen_st_i32(var, cpu_env, offset);
+ tcg_gen_st_i32(var, tcg_env, offset);
break;
default:
g_assert_not_reached();
{
#ifndef CONFIG_USER_ONLY
if (s->v8m_stackcheck) {
- gen_helper_v8m_stackcheck(cpu_env, var);
+ gen_helper_v8m_stackcheck(tcg_env, var);
}
#endif
store_reg(s, 13, var);
void gen_set_cpsr(TCGv_i32 var, uint32_t mask)
{
- gen_helper_cpsr_write(cpu_env, var, tcg_constant_i32(mask));
+ gen_helper_cpsr_write(tcg_env, var, tcg_constant_i32(mask));
}
static void gen_rebuild_hflags(DisasContext *s, bool new_el)
if (new_el) {
if (m_profile) {
- gen_helper_rebuild_hflags_m32_newel(cpu_env);
+ gen_helper_rebuild_hflags_m32_newel(tcg_env);
} else {
- gen_helper_rebuild_hflags_a32_newel(cpu_env);
+ gen_helper_rebuild_hflags_a32_newel(tcg_env);
}
} else {
TCGv_i32 tcg_el = tcg_constant_i32(s->current_el);
if (m_profile) {
- gen_helper_rebuild_hflags_m32(cpu_env, tcg_el);
+ gen_helper_rebuild_hflags_m32(tcg_env, tcg_el);
} else {
- gen_helper_rebuild_hflags_a32(cpu_env, tcg_el);
+ gen_helper_rebuild_hflags_a32(tcg_env, tcg_el);
}
}
}
static void gen_exception_internal(int excp)
{
assert(excp_is_internal(excp));
- gen_helper_exception_internal(cpu_env, tcg_constant_i32(excp));
+ gen_helper_exception_internal(tcg_env, tcg_constant_i32(excp));
}
static void gen_singlestep_exception(DisasContext *s)
{
if (flags) {
switch (shiftop) {
- case 0: gen_helper_shl_cc(var, cpu_env, var, shift); break;
- case 1: gen_helper_shr_cc(var, cpu_env, var, shift); break;
- case 2: gen_helper_sar_cc(var, cpu_env, var, shift); break;
- case 3: gen_helper_ror_cc(var, cpu_env, var, shift); break;
+ case 0: gen_helper_shl_cc(var, tcg_env, var, shift); break;
+ case 1: gen_helper_shr_cc(var, tcg_env, var, shift); break;
+ case 2: gen_helper_sar_cc(var, tcg_env, var, shift); break;
+ case 3: gen_helper_ror_cc(var, tcg_env, var, shift); break;
}
} else {
switch (shiftop) {
* is correct in the non-UNPREDICTABLE cases, and we can choose
* "zeroes the IT bits" as our UNPREDICTABLE behaviour otherwise.
*/
- gen_helper_v7m_bxns(cpu_env, var);
+ gen_helper_v7m_bxns(tcg_env, var);
s->base.is_jmp = DISAS_EXIT;
}
* The blxns helper may throw an exception.
*/
gen_update_pc(s, curr_insn_len(s));
- gen_helper_v7m_blxns(cpu_env, var);
+ gen_helper_v7m_blxns(tcg_env, var);
s->base.is_jmp = DISAS_EXIT;
}
* the insn really executes).
*/
gen_update_pc(s, 0);
- gen_helper_pre_hvc(cpu_env);
+ gen_helper_pre_hvc(tcg_env);
/* Otherwise we will treat this as a real exception which
* happens after execution of the insn. (The distinction matters
* for the PC value reported to the exception handler and also
* the insn executes.
*/
gen_update_pc(s, 0);
- gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa32_smc()));
+ gen_helper_pre_smc(tcg_env, tcg_constant_i32(syn_aa32_smc()));
gen_update_pc(s, curr_insn_len(s));
s->base.is_jmp = DISAS_SMC;
}
static void gen_exception_el_v(int excp, uint32_t syndrome, TCGv_i32 tcg_el)
{
- gen_helper_exception_with_syndrome_el(cpu_env, tcg_constant_i32(excp),
+ gen_helper_exception_with_syndrome_el(tcg_env, tcg_constant_i32(excp),
tcg_constant_i32(syndrome), tcg_el);
}
static void gen_exception(int excp, uint32_t syndrome)
{
- gen_helper_exception_with_syndrome(cpu_env, tcg_constant_i32(excp),
+ gen_helper_exception_with_syndrome(tcg_env, tcg_constant_i32(excp),
tcg_constant_i32(syndrome));
}
{
gen_set_condexec(s);
gen_update_pc(s, 0);
- gen_helper_exception_bkpt_insn(cpu_env, tcg_constant_i32(syn));
+ gen_helper_exception_bkpt_insn(tcg_env, tcg_constant_i32(syn));
s->base.is_jmp = DISAS_NORETURN;
}
switch (memop) {
case MO_SB:
- tcg_gen_ld8s_i32(dest, cpu_env, off);
+ tcg_gen_ld8s_i32(dest, tcg_env, off);
break;
case MO_UB:
- tcg_gen_ld8u_i32(dest, cpu_env, off);
+ tcg_gen_ld8u_i32(dest, tcg_env, off);
break;
case MO_SW:
- tcg_gen_ld16s_i32(dest, cpu_env, off);
+ tcg_gen_ld16s_i32(dest, tcg_env, off);
break;
case MO_UW:
- tcg_gen_ld16u_i32(dest, cpu_env, off);
+ tcg_gen_ld16u_i32(dest, tcg_env, off);
break;
case MO_UL:
case MO_SL:
- tcg_gen_ld_i32(dest, cpu_env, off);
+ tcg_gen_ld_i32(dest, tcg_env, off);
break;
default:
g_assert_not_reached();
switch (memop) {
case MO_SL:
- tcg_gen_ld32s_i64(dest, cpu_env, off);
+ tcg_gen_ld32s_i64(dest, tcg_env, off);
break;
case MO_UL:
- tcg_gen_ld32u_i64(dest, cpu_env, off);
+ tcg_gen_ld32u_i64(dest, tcg_env, off);
break;
case MO_UQ:
- tcg_gen_ld_i64(dest, cpu_env, off);
+ tcg_gen_ld_i64(dest, tcg_env, off);
break;
default:
g_assert_not_reached();
switch (memop) {
case MO_8:
- tcg_gen_st8_i32(src, cpu_env, off);
+ tcg_gen_st8_i32(src, tcg_env, off);
break;
case MO_16:
- tcg_gen_st16_i32(src, cpu_env, off);
+ tcg_gen_st16_i32(src, tcg_env, off);
break;
case MO_32:
- tcg_gen_st_i32(src, cpu_env, off);
+ tcg_gen_st_i32(src, tcg_env, off);
break;
default:
g_assert_not_reached();
switch (memop) {
case MO_32:
- tcg_gen_st32_i64(src, cpu_env, off);
+ tcg_gen_st32_i64(src, tcg_env, off);
break;
case MO_64:
- tcg_gen_st_i64(src, cpu_env, off);
+ tcg_gen_st_i64(src, tcg_env, off);
break;
default:
g_assert_not_reached();
static inline void iwmmxt_load_reg(TCGv_i64 var, int reg)
{
- tcg_gen_ld_i64(var, cpu_env, offsetof(CPUARMState, iwmmxt.regs[reg]));
+ tcg_gen_ld_i64(var, tcg_env, offsetof(CPUARMState, iwmmxt.regs[reg]));
}
static inline void iwmmxt_store_reg(TCGv_i64 var, int reg)
{
- tcg_gen_st_i64(var, cpu_env, offsetof(CPUARMState, iwmmxt.regs[reg]));
+ tcg_gen_st_i64(var, tcg_env, offsetof(CPUARMState, iwmmxt.regs[reg]));
}
static inline TCGv_i32 iwmmxt_load_creg(int reg)
{
TCGv_i32 var = tcg_temp_new_i32();
- tcg_gen_ld_i32(var, cpu_env, offsetof(CPUARMState, iwmmxt.cregs[reg]));
+ tcg_gen_ld_i32(var, tcg_env, offsetof(CPUARMState, iwmmxt.cregs[reg]));
return var;
}
static inline void iwmmxt_store_creg(int reg, TCGv_i32 var)
{
- tcg_gen_st_i32(var, cpu_env, offsetof(CPUARMState, iwmmxt.cregs[reg]));
+ tcg_gen_st_i32(var, tcg_env, offsetof(CPUARMState, iwmmxt.cregs[reg]));
}
static inline void gen_op_iwmmxt_movq_wRn_M0(int rn)
static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
{ \
iwmmxt_load_reg(cpu_V1, rn); \
- gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0, cpu_V1); \
+ gen_helper_iwmmxt_##name(cpu_M0, tcg_env, cpu_M0, cpu_V1); \
}
#define IWMMXT_OP_ENV_SIZE(name) \
#define IWMMXT_OP_ENV1(name) \
static inline void gen_op_iwmmxt_##name##_M0(void) \
{ \
- gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0); \
+ gen_helper_iwmmxt_##name(cpu_M0, tcg_env, cpu_M0); \
}
IWMMXT_OP(maddsq)
}
switch ((insn >> 22) & 3) {
case 1:
- gen_helper_iwmmxt_srlw(cpu_M0, cpu_env, cpu_M0, tmp);
+ gen_helper_iwmmxt_srlw(cpu_M0, tcg_env, cpu_M0, tmp);
break;
case 2:
- gen_helper_iwmmxt_srll(cpu_M0, cpu_env, cpu_M0, tmp);
+ gen_helper_iwmmxt_srll(cpu_M0, tcg_env, cpu_M0, tmp);
break;
case 3:
- gen_helper_iwmmxt_srlq(cpu_M0, cpu_env, cpu_M0, tmp);
+ gen_helper_iwmmxt_srlq(cpu_M0, tcg_env, cpu_M0, tmp);
break;
}
gen_op_iwmmxt_movq_wRn_M0(wrd);
}
switch ((insn >> 22) & 3) {
case 1:
- gen_helper_iwmmxt_sraw(cpu_M0, cpu_env, cpu_M0, tmp);
+ gen_helper_iwmmxt_sraw(cpu_M0, tcg_env, cpu_M0, tmp);
break;
case 2:
- gen_helper_iwmmxt_sral(cpu_M0, cpu_env, cpu_M0, tmp);
+ gen_helper_iwmmxt_sral(cpu_M0, tcg_env, cpu_M0, tmp);
break;
case 3:
- gen_helper_iwmmxt_sraq(cpu_M0, cpu_env, cpu_M0, tmp);
+ gen_helper_iwmmxt_sraq(cpu_M0, tcg_env, cpu_M0, tmp);
break;
}
gen_op_iwmmxt_movq_wRn_M0(wrd);
}
switch ((insn >> 22) & 3) {
case 1:
- gen_helper_iwmmxt_sllw(cpu_M0, cpu_env, cpu_M0, tmp);
+ gen_helper_iwmmxt_sllw(cpu_M0, tcg_env, cpu_M0, tmp);
break;
case 2:
- gen_helper_iwmmxt_slll(cpu_M0, cpu_env, cpu_M0, tmp);
+ gen_helper_iwmmxt_slll(cpu_M0, tcg_env, cpu_M0, tmp);
break;
case 3:
- gen_helper_iwmmxt_sllq(cpu_M0, cpu_env, cpu_M0, tmp);
+ gen_helper_iwmmxt_sllq(cpu_M0, tcg_env, cpu_M0, tmp);
break;
}
gen_op_iwmmxt_movq_wRn_M0(wrd);
if (gen_iwmmxt_shift(insn, 0xf, tmp)) {
return 1;
}
- gen_helper_iwmmxt_rorw(cpu_M0, cpu_env, cpu_M0, tmp);
+ gen_helper_iwmmxt_rorw(cpu_M0, tcg_env, cpu_M0, tmp);
break;
case 2:
if (gen_iwmmxt_shift(insn, 0x1f, tmp)) {
return 1;
}
- gen_helper_iwmmxt_rorl(cpu_M0, cpu_env, cpu_M0, tmp);
+ gen_helper_iwmmxt_rorl(cpu_M0, tcg_env, cpu_M0, tmp);
break;
case 3:
if (gen_iwmmxt_shift(insn, 0x3f, tmp)) {
return 1;
}
- gen_helper_iwmmxt_rorq(cpu_M0, cpu_env, cpu_M0, tmp);
+ gen_helper_iwmmxt_rorq(cpu_M0, tcg_env, cpu_M0, tmp);
break;
}
gen_op_iwmmxt_movq_wRn_M0(wrd);
rd0 = (insn >> 16) & 0xf;
gen_op_iwmmxt_movq_M0_wRn(rd0);
tmp = tcg_constant_i32(((insn >> 16) & 0xf0) | (insn & 0x0f));
- gen_helper_iwmmxt_shufh(cpu_M0, cpu_env, cpu_M0, tmp);
+ gen_helper_iwmmxt_shufh(cpu_M0, tcg_env, cpu_M0, tmp);
gen_op_iwmmxt_movq_wRn_M0(wrd);
gen_op_iwmmxt_set_mup();
gen_op_iwmmxt_set_cup();
gen_set_condexec(s);
gen_update_pc(s, 0);
tcg_reg = load_reg(s, rn);
- gen_helper_msr_banked(cpu_env, tcg_reg,
+ gen_helper_msr_banked(tcg_env, tcg_reg,
tcg_constant_i32(tgtmode),
tcg_constant_i32(regno));
s->base.is_jmp = DISAS_UPDATE_EXIT;
gen_set_condexec(s);
gen_update_pc(s, 0);
tcg_reg = tcg_temp_new_i32();
- gen_helper_mrs_banked(tcg_reg, cpu_env,
+ gen_helper_mrs_banked(tcg_reg, tcg_env,
tcg_constant_i32(tgtmode),
tcg_constant_i32(regno));
store_reg(s, rn, tcg_reg);
* be called after storing the new PC.
*/
translator_io_start(&s->base);
- gen_helper_cpsr_write_eret(cpu_env, cpsr);
+ gen_helper_cpsr_write_eret(tcg_env, cpsr);
/* Must exit loop to check un-masked IRQs */
s->base.is_jmp = DISAS_EXIT;
}
{
TCGv_ptr qc_ptr = tcg_temp_new_ptr();
- tcg_gen_addi_ptr(qc_ptr, cpu_env, offsetof(CPUARMState, vfp.qc));
+ tcg_gen_addi_ptr(qc_ptr, tcg_env, offsetof(CPUARMState, vfp.qc));
tcg_gen_gvec_3_ptr(rd_ofs, rn_ofs, rm_ofs, qc_ptr,
opr_sz, max_sz, 0, fn);
}
case 0:
if (arm_dc_feature(s, ARM_FEATURE_AARCH64)
&& dc_isar_feature(aa64_tidcp1, s)) {
- gen_helper_tidcp_el0(cpu_env, tcg_constant_i32(syndrome));
+ gen_helper_tidcp_el0(tcg_env, tcg_constant_i32(syndrome));
}
break;
case 1:
- gen_helper_tidcp_el1(cpu_env, tcg_constant_i32(syndrome));
+ gen_helper_tidcp_el1(tcg_env, tcg_constant_i32(syndrome));
break;
}
}
gen_set_condexec(s);
gen_update_pc(s, 0);
tcg_ri = tcg_temp_new_ptr();
- gen_helper_access_check_cp_reg(tcg_ri, cpu_env,
+ gen_helper_access_check_cp_reg(tcg_ri, tcg_env,
tcg_constant_i32(key),
tcg_constant_i32(syndrome),
tcg_constant_i32(isread));
tcg_ri = gen_lookup_cp_reg(key);
}
tmp64 = tcg_temp_new_i64();
- gen_helper_get_cp_reg64(tmp64, cpu_env, tcg_ri);
+ gen_helper_get_cp_reg64(tmp64, tcg_env, tcg_ri);
} else {
tmp64 = tcg_temp_new_i64();
- tcg_gen_ld_i64(tmp64, cpu_env, ri->fieldoffset);
+ tcg_gen_ld_i64(tmp64, tcg_env, ri->fieldoffset);
}
tmp = tcg_temp_new_i32();
tcg_gen_extrl_i64_i32(tmp, tmp64);
tcg_ri = gen_lookup_cp_reg(key);
}
tmp = tcg_temp_new_i32();
- gen_helper_get_cp_reg(tmp, cpu_env, tcg_ri);
+ gen_helper_get_cp_reg(tmp, tcg_env, tcg_ri);
} else {
tmp = load_cpu_offset(ri->fieldoffset);
}
if (!tcg_ri) {
tcg_ri = gen_lookup_cp_reg(key);
}
- gen_helper_set_cp_reg64(cpu_env, tcg_ri, tmp64);
+ gen_helper_set_cp_reg64(tcg_env, tcg_ri, tmp64);
} else {
- tcg_gen_st_i64(tmp64, cpu_env, ri->fieldoffset);
+ tcg_gen_st_i64(tmp64, tcg_env, ri->fieldoffset);
}
} else {
TCGv_i32 tmp = load_reg(s, rt);
if (!tcg_ri) {
tcg_ri = gen_lookup_cp_reg(key);
}
- gen_helper_set_cp_reg(cpu_env, tcg_ri, tmp);
+ gen_helper_set_cp_reg(tcg_env, tcg_ri, tmp);
} else {
store_cpu_offset(tmp, ri->fieldoffset, 4);
}
/* get_r13_banked() will raise an exception if called from System mode */
gen_set_condexec(s);
gen_update_pc(s, 0);
- gen_helper_get_r13_banked(addr, cpu_env, tcg_constant_i32(mode));
+ gen_helper_get_r13_banked(addr, tcg_env, tcg_constant_i32(mode));
switch (amode) {
case 0: /* DA */
offset = -4;
g_assert_not_reached();
}
tcg_gen_addi_i32(addr, addr, offset);
- gen_helper_set_r13_banked(cpu_env, tcg_constant_i32(mode), addr);
+ gen_helper_set_r13_banked(tcg_env, tcg_constant_i32(mode), addr);
}
s->base.is_jmp = DISAS_UPDATE_EXIT;
}
static void gen_mve_sqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift)
{
- gen_helper_mve_sqshll(r, cpu_env, n, tcg_constant_i32(shift));
+ gen_helper_mve_sqshll(r, tcg_env, n, tcg_constant_i32(shift));
}
static bool trans_SQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a)
static void gen_mve_uqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift)
{
- gen_helper_mve_uqshll(r, cpu_env, n, tcg_constant_i32(shift));
+ gen_helper_mve_uqshll(r, tcg_env, n, tcg_constant_i32(shift));
}
static bool trans_UQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a)
tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
/* The helper takes care of the sign-extension of the low 8 bits of Rm */
- fn(rda, cpu_env, rda, cpu_R[a->rm]);
+ fn(rda, tcg_env, rda, cpu_R[a->rm]);
tcg_gen_extrl_i64_i32(rdalo, rda);
tcg_gen_extrh_i64_i32(rdahi, rda);
static void gen_mve_sqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift)
{
- gen_helper_mve_sqshl(r, cpu_env, n, tcg_constant_i32(shift));
+ gen_helper_mve_sqshl(r, tcg_env, n, tcg_constant_i32(shift));
}
static bool trans_SQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
static void gen_mve_uqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift)
{
- gen_helper_mve_uqshl(r, cpu_env, n, tcg_constant_i32(shift));
+ gen_helper_mve_uqshl(r, tcg_env, n, tcg_constant_i32(shift));
}
static bool trans_UQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
}
/* The helper takes care of the sign-extension of the low 8 bits of Rm */
- fn(cpu_R[a->rda], cpu_env, cpu_R[a->rda], cpu_R[a->rm]);
+ fn(cpu_R[a->rda], tcg_env, cpu_R[a->rda], cpu_R[a->rm]);
return true;
}
t0 = load_reg(s, a->rm);
t1 = load_reg(s, a->rn);
if (doub) {
- gen_helper_add_saturate(t1, cpu_env, t1, t1);
+ gen_helper_add_saturate(t1, tcg_env, t1, t1);
}
if (add) {
- gen_helper_add_saturate(t0, cpu_env, t0, t1);
+ gen_helper_add_saturate(t0, tcg_env, t0, t1);
} else {
- gen_helper_sub_saturate(t0, cpu_env, t0, t1);
+ gen_helper_sub_saturate(t0, tcg_env, t0, t1);
}
store_reg(s, a->rd, t0);
return true;
break;
case 1:
t1 = load_reg(s, a->ra);
- gen_helper_add_setq(t0, cpu_env, t0, t1);
+ gen_helper_add_setq(t0, tcg_env, t0, t1);
store_reg(s, a->rd, t0);
break;
case 2:
tcg_gen_muls2_i32(t0, t1, t0, t1);
if (add) {
t0 = load_reg(s, a->ra);
- gen_helper_add_setq(t1, cpu_env, t1, t0);
+ gen_helper_add_setq(t1, tcg_env, t1, t0);
}
store_reg(s, a->rd, t1);
return true;
* Test for EL2 present, and defer test for SEL2 to runtime.
*/
if (s->current_el <= 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) {
- gen_helper_vesb(cpu_env);
+ gen_helper_vesb(tcg_env);
}
}
return true;
tmp = load_cpu_field(spsr);
} else {
tmp = tcg_temp_new_i32();
- gen_helper_cpsr_read(tmp, cpu_env);
+ gen_helper_cpsr_read(tmp, tcg_env);
}
store_reg(s, a->rd, tmp);
return true;
return false;
}
tmp = tcg_temp_new_i32();
- gen_helper_v7m_mrs(tmp, cpu_env, tcg_constant_i32(a->sysm));
+ gen_helper_v7m_mrs(tmp, tcg_env, tcg_constant_i32(a->sysm));
store_reg(s, a->rd, tmp);
return true;
}
}
addr = tcg_constant_i32((a->mask << 10) | a->sysm);
reg = load_reg(s, a->rn);
- gen_helper_v7m_msr(cpu_env, addr, reg);
+ gen_helper_v7m_msr(tcg_env, addr, reg);
/* If we wrote to CONTROL, the EL might have changed */
gen_rebuild_hflags(s, true);
gen_lookup_tb(s);
if (!arm_dc_feature(s, ARM_FEATURE_V8) &&
arm_dc_feature(s, ARM_FEATURE_EL2) &&
s->current_el < 2 && s->ns) {
- gen_helper_check_bxj_trap(cpu_env, tcg_constant_i32(a->rm));
+ gen_helper_check_bxj_trap(tcg_env, tcg_constant_i32(a->rm));
}
/* Trivial implementation equivalent to bx. */
gen_bx(s, load_reg(s, a->rm));
addr = load_reg(s, a->rn);
tmp = tcg_temp_new_i32();
- gen_helper_v7m_tt(tmp, cpu_env, addr, tcg_constant_i32((a->A << 1) | a->T));
+ gen_helper_v7m_tt(tmp, tcg_env, addr, tcg_constant_i32((a->A << 1) | a->T));
store_reg(s, a->rd, tmp);
return true;
}
TCGv_i32 addr = load_reg(s, a->rn);
if (s->v8m_stackcheck && a->rn == 13 && a->w) {
- gen_helper_v8m_stackcheck(cpu_env, addr);
+ gen_helper_v8m_stackcheck(tcg_env, addr);
}
if (a->p) {
if (!a->u) {
TCGv_i32 newsp = tcg_temp_new_i32();
tcg_gen_addi_i32(newsp, cpu_R[13], ofs);
- gen_helper_v8m_stackcheck(cpu_env, newsp);
+ gen_helper_v8m_stackcheck(tcg_env, newsp);
} else {
- gen_helper_v8m_stackcheck(cpu_env, cpu_R[13]);
+ gen_helper_v8m_stackcheck(tcg_env, cpu_R[13]);
}
}
t1 = load_reg(s, a->rm);
ge = tcg_temp_new_ptr();
- tcg_gen_addi_ptr(ge, cpu_env, offsetof(CPUARMState, GE));
+ tcg_gen_addi_ptr(ge, tcg_env, offsetof(CPUARMState, GE));
gen(t0, t0, t1, ge);
store_reg(s, a->rd, t0);
tcg_gen_shli_i32(tmp, tmp, shift);
}
- gen(tmp, cpu_env, tmp, tcg_constant_i32(a->satimm));
+ gen(tmp, tcg_env, tmp, tcg_constant_i32(a->satimm));
store_reg(s, a->rd, tmp);
return true;
t1 = load_reg(s, a->rn);
t2 = load_reg(s, a->rm);
t3 = tcg_temp_new_i32();
- tcg_gen_ld_i32(t3, cpu_env, offsetof(CPUARMState, GE));
+ tcg_gen_ld_i32(t3, tcg_env, offsetof(CPUARMState, GE));
gen_helper_sel_flags(t1, t3, t1, t2);
store_reg(s, a->rd, t1);
return true;
if (a->ra != 15) {
t2 = load_reg(s, a->ra);
- gen_helper_add_setq(t1, cpu_env, t1, t2);
+ gen_helper_add_setq(t1, tcg_env, t1, t2);
}
} else if (a->ra == 15) {
/* Single saturation-checking addition */
- gen_helper_add_setq(t1, cpu_env, t1, t2);
+ gen_helper_add_setq(t1, tcg_env, t1, t2);
} else {
/*
* We need to add the products and Ra together and then
t1 = load_reg(s, a->rn);
t2 = load_reg(s, a->rm);
if (u) {
- gen_helper_udiv(t1, cpu_env, t1, t2);
+ gen_helper_udiv(t1, tcg_env, t1, t2);
} else {
- gen_helper_sdiv(t1, cpu_env, t1, t2);
+ gen_helper_sdiv(t1, tcg_env, t1, t2);
}
store_reg(s, a->rd, t1);
return true;
* either the original SP (if incrementing) or our
* final SP (if decrementing), so that's what we check.
*/
- gen_helper_v8m_stackcheck(cpu_env, addr);
+ gen_helper_v8m_stackcheck(tcg_env, addr);
}
return addr;
if (user && i != 15) {
tmp = tcg_temp_new_i32();
- gen_helper_get_user_reg(tmp, cpu_env, tcg_constant_i32(i));
+ gen_helper_get_user_reg(tmp, tcg_env, tcg_constant_i32(i));
} else {
tmp = load_reg(s, i);
}
tmp = tcg_temp_new_i32();
gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
if (user) {
- gen_helper_set_user_reg(cpu_env, tcg_constant_i32(i), tmp);
+ gen_helper_set_user_reg(tcg_env, tcg_constant_i32(i), tmp);
} else if (i == a->rn) {
loaded_var = tmp;
loaded_base = true;
/* Restore CPSR from SPSR. */
tmp = load_cpu_field(spsr);
translator_io_start(&s->base);
- gen_helper_cpsr_write_eret(cpu_env, tmp);
+ gen_helper_cpsr_write_eret(tcg_env, tmp);
/* Must exit loop to check un-masked IRQs */
s->base.is_jmp = DISAS_EXIT;
}
* Clear APSR (by calling the MSR helper with the same argument
* as for "MSR APSR_nzcvqg, Rn": mask = 0b1100, SYSM=0)
*/
- gen_helper_v7m_msr(cpu_env, tcg_constant_i32(0xc00), zero);
+ gen_helper_v7m_msr(tcg_env, tcg_constant_i32(0xc00), zero);
}
clear_eci_state(s);
return true;
tcg_gen_movcond_i32(TCG_COND_LEU, masklen,
masklen, tcg_constant_i32(1 << (4 - a->size)),
rn_shifted, tcg_constant_i32(16));
- gen_helper_mve_vctp(cpu_env, masklen);
+ gen_helper_mve_vctp(tcg_env, masklen);
/* This insn updates predication bits */
s->base.is_jmp = DISAS_UPDATE_NOCHAIN;
mve_update_eci(s);
/* FAULTMASK */
if (a->F) {
addr = tcg_constant_i32(19);
- gen_helper_v7m_msr(cpu_env, addr, tmp);
+ gen_helper_v7m_msr(tcg_env, addr, tmp);
}
/* PRIMASK */
if (a->I) {
addr = tcg_constant_i32(16);
- gen_helper_v7m_msr(cpu_env, addr, tmp);
+ gen_helper_v7m_msr(tcg_env, addr, tmp);
}
gen_rebuild_hflags(s, false);
gen_lookup_tb(s);
return false;
}
if (a->E != (s->be_data == MO_BE)) {
- gen_helper_setend(cpu_env);
+ gen_helper_setend(tcg_env);
s->base.is_jmp = DISAS_UPDATE_EXIT;
}
return true;
* be possible after an indirect branch, at the start of the TB.
*/
assert(dc->base.num_insns == 1);
- gen_helper_exception_pc_alignment(cpu_env, tcg_constant_tl(pc));
+ gen_helper_exception_pc_alignment(tcg_env, tcg_constant_tl(pc));
dc->base.is_jmp = DISAS_NORETURN;
dc->base.pc_next = QEMU_ALIGN_UP(pc, 4);
return;
/* nothing more to generate */
break;
case DISAS_WFI:
- gen_helper_wfi(cpu_env, tcg_constant_i32(curr_insn_len(dc)));
+ gen_helper_wfi(tcg_env, tcg_constant_i32(curr_insn_len(dc)));
/*
* The helper doesn't necessarily throw an exception, but we
* must go back to the main loop to check for interrupts anyway.
tcg_gen_exit_tb(NULL, 0);
break;
case DISAS_WFE:
- gen_helper_wfe(cpu_env);
+ gen_helper_wfe(tcg_env);
break;
case DISAS_YIELD:
- gen_helper_yield(cpu_env);
+ gen_helper_yield(tcg_env);
break;
case DISAS_SWI:
gen_exception(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb));
{
TCGv_i32 ret = tcg_temp_new_i32();
- tcg_gen_ld_i32(ret, cpu_env,
+ tcg_gen_ld_i32(ret, tcg_env,
offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPSCR]));
tcg_gen_extract_i32(ret, ret, 26, 1);
tcg_debug_assert(!(bits & CACHED_PSTATE_BITS));
- tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate));
+ tcg_gen_ld_i32(p, tcg_env, offsetof(CPUARMState, pstate));
tcg_gen_ori_i32(p, p, bits);
- tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate));
+ tcg_gen_st_i32(p, tcg_env, offsetof(CPUARMState, pstate));
}
/* Clear bits within PSTATE. */
tcg_debug_assert(!(bits & CACHED_PSTATE_BITS));
- tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate));
+ tcg_gen_ld_i32(p, tcg_env, offsetof(CPUARMState, pstate));
tcg_gen_andi_i32(p, p, ~bits);
- tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate));
+ tcg_gen_st_i32(p, tcg_env, offsetof(CPUARMState, pstate));
}
/* If the singlestep state is Active-not-pending, advance to Active-pending. */
{
/* Fill in the same_el field of the syndrome in the helper. */
uint32_t syn = syn_swstep(false, isv, ex);
- gen_helper_exception_swstep(cpu_env, tcg_constant_i32(syn));
+ gen_helper_exception_swstep(tcg_env, tcg_constant_i32(syn));
}
/*
default:
g_assert_not_reached();
}
- tcg_gen_addi_ptr(statusptr, cpu_env, offset);
+ tcg_gen_addi_ptr(statusptr, tcg_env, offset);
return statusptr;
}
static inline TCGv_ptr gen_lookup_cp_reg(uint32_t key)
{
TCGv_ptr ret = tcg_temp_new_ptr();
- gen_helper_lookup_cp_reg(ret, cpu_env, tcg_constant_i32(key));
+ gen_helper_lookup_cp_reg(ret, tcg_env, tcg_constant_i32(key));
return ret;
}
int i;
#define AVR_REG_OFFS(x) offsetof(CPUAVRState, x)
- cpu_pc = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(pc_w), "pc");
- cpu_Cf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregC), "Cf");
- cpu_Zf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregZ), "Zf");
- cpu_Nf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregN), "Nf");
- cpu_Vf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregV), "Vf");
- cpu_Sf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregS), "Sf");
- cpu_Hf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregH), "Hf");
- cpu_Tf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregT), "Tf");
- cpu_If = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregI), "If");
- cpu_rampD = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampD), "rampD");
- cpu_rampX = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampX), "rampX");
- cpu_rampY = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampY), "rampY");
- cpu_rampZ = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampZ), "rampZ");
- cpu_eind = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(eind), "eind");
- cpu_sp = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sp), "sp");
- cpu_skip = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(skip), "skip");
+ cpu_pc = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(pc_w), "pc");
+ cpu_Cf = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(sregC), "Cf");
+ cpu_Zf = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(sregZ), "Zf");
+ cpu_Nf = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(sregN), "Nf");
+ cpu_Vf = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(sregV), "Vf");
+ cpu_Sf = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(sregS), "Sf");
+ cpu_Hf = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(sregH), "Hf");
+ cpu_Tf = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(sregT), "Tf");
+ cpu_If = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(sregI), "If");
+ cpu_rampD = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(rampD), "rampD");
+ cpu_rampX = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(rampX), "rampX");
+ cpu_rampY = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(rampY), "rampY");
+ cpu_rampZ = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(rampZ), "rampZ");
+ cpu_eind = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(eind), "eind");
+ cpu_sp = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(sp), "sp");
+ cpu_skip = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(skip), "skip");
for (i = 0; i < NUMBER_OF_CPU_REGISTERS; i++) {
- cpu_r[i] = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(r[i]),
+ cpu_r[i] = tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(r[i]),
reg_names[i]);
}
#undef AVR_REG_OFFS
static bool avr_have_feature(DisasContext *ctx, int feature)
{
if (!avr_feature(ctx->env, feature)) {
- gen_helper_unsupported(cpu_env);
+ gen_helper_unsupported(tcg_env);
ctx->base.is_jmp = DISAS_NORETURN;
return false;
}
TCGv data = tcg_temp_new_i32();
TCGv port = tcg_constant_i32(a->reg);
- gen_helper_inb(data, cpu_env, port);
+ gen_helper_inb(data, tcg_env, port);
tcg_gen_andi_tl(data, data, 1 << a->bit);
ctx->skip_cond = TCG_COND_EQ;
ctx->skip_var0 = data;
TCGv data = tcg_temp_new_i32();
TCGv port = tcg_constant_i32(a->reg);
- gen_helper_inb(data, cpu_env, port);
+ gen_helper_inb(data, tcg_env, port);
tcg_gen_andi_tl(data, data, 1 << a->bit);
ctx->skip_cond = TCG_COND_NE;
ctx->skip_var0 = data;
static void gen_data_store(DisasContext *ctx, TCGv data, TCGv addr)
{
if (ctx->base.tb->flags & TB_FLAGS_FULL_ACCESS) {
- gen_helper_fullwr(cpu_env, data, addr);
+ gen_helper_fullwr(tcg_env, data, addr);
} else {
tcg_gen_qemu_st_tl(data, addr, MMU_DATA_IDX, MO_UB);
}
static void gen_data_load(DisasContext *ctx, TCGv data, TCGv addr)
{
if (ctx->base.tb->flags & TB_FLAGS_FULL_ACCESS) {
- gen_helper_fullrd(data, cpu_env, addr);
+ gen_helper_fullrd(data, tcg_env, addr);
} else {
tcg_gen_qemu_ld_tl(data, addr, MMU_DATA_IDX, MO_UB);
}
TCGv Rd = cpu_r[a->rd];
TCGv port = tcg_constant_i32(a->imm);
- gen_helper_inb(Rd, cpu_env, port);
+ gen_helper_inb(Rd, tcg_env, port);
return true;
}
TCGv Rd = cpu_r[a->rd];
TCGv port = tcg_constant_i32(a->imm);
- gen_helper_outb(cpu_env, port, Rd);
+ gen_helper_outb(tcg_env, port, Rd);
return true;
}
TCGv data = tcg_temp_new_i32();
TCGv port = tcg_constant_i32(a->reg);
- gen_helper_inb(data, cpu_env, port);
+ gen_helper_inb(data, tcg_env, port);
tcg_gen_ori_tl(data, data, 1 << a->bit);
- gen_helper_outb(cpu_env, port, data);
+ gen_helper_outb(tcg_env, port, data);
return true;
}
TCGv data = tcg_temp_new_i32();
TCGv port = tcg_constant_i32(a->reg);
- gen_helper_inb(data, cpu_env, port);
+ gen_helper_inb(data, tcg_env, port);
tcg_gen_andi_tl(data, data, ~(1 << a->bit));
- gen_helper_outb(cpu_env, port, data);
+ gen_helper_outb(tcg_env, port, data);
return true;
}
#ifdef BREAKPOINT_ON_BREAK
tcg_gen_movi_tl(cpu_pc, ctx->npc - 1);
- gen_helper_debug(cpu_env);
+ gen_helper_debug(tcg_env);
ctx->base.is_jmp = DISAS_EXIT;
#else
/* NOP */
*/
static bool trans_SLEEP(DisasContext *ctx, arg_SLEEP *a)
{
- gen_helper_sleep(cpu_env);
+ gen_helper_sleep(tcg_env);
ctx->base.is_jmp = DISAS_NORETURN;
return true;
}
*/
static bool trans_WDR(DisasContext *ctx, arg_WDR *a)
{
- gen_helper_wdr(cpu_env);
+ gen_helper_wdr(tcg_env);
return true;
}
uint32_t opcode = next_word(ctx);
if (!decode_insn(ctx, opcode)) {
- gen_helper_unsupported(cpu_env);
+ gen_helper_unsupported(tcg_env);
ctx->base.is_jmp = DISAS_NORETURN;
}
}
};
#define t_gen_mov_TN_env(tn, member) \
- tcg_gen_ld_tl(tn, cpu_env, offsetof(CPUCRISState, member))
+ tcg_gen_ld_tl(tn, tcg_env, offsetof(CPUCRISState, member))
#define t_gen_mov_env_TN(member, tn) \
- tcg_gen_st_tl(tn, cpu_env, offsetof(CPUCRISState, member))
+ tcg_gen_st_tl(tn, tcg_env, offsetof(CPUCRISState, member))
#define t_gen_movi_env_TN(member, c) \
t_gen_mov_env_TN(member, tcg_constant_tl(c))
tcg_gen_andi_tl(cpu_PR[r], tn, 3);
} else {
if (r == PR_PID) {
- gen_helper_tlb_flush_pid(cpu_env, tn);
+ gen_helper_tlb_flush_pid(tcg_env, tn);
}
if (dc->tb_flags & S_FLAG && r == PR_SPC) {
- gen_helper_spc_write(cpu_env, tn);
+ gen_helper_spc_write(tcg_env, tn);
} else if (r == PR_CCS) {
dc->cpustate_changed = 1;
}
static inline void t_gen_raise_exception(uint32_t index)
{
- gen_helper_raise_exception(cpu_env, tcg_constant_i32(index));
+ gen_helper_raise_exception(tcg_env, tcg_constant_i32(index));
}
static void t_gen_lsl(TCGv d, TCGv a, TCGv b)
switch (dc->cc_op) {
case CC_OP_MCP:
- gen_helper_evaluate_flags_mcp(cpu_PR[PR_CCS], cpu_env,
+ gen_helper_evaluate_flags_mcp(cpu_PR[PR_CCS], tcg_env,
cpu_PR[PR_CCS], cc_src,
cc_dest, cc_result);
break;
case CC_OP_MULS:
- gen_helper_evaluate_flags_muls(cpu_PR[PR_CCS], cpu_env,
+ gen_helper_evaluate_flags_muls(cpu_PR[PR_CCS], tcg_env,
cpu_PR[PR_CCS], cc_result,
cpu_PR[PR_MOF]);
break;
case CC_OP_MULU:
- gen_helper_evaluate_flags_mulu(cpu_PR[PR_CCS], cpu_env,
+ gen_helper_evaluate_flags_mulu(cpu_PR[PR_CCS], tcg_env,
cpu_PR[PR_CCS], cc_result,
cpu_PR[PR_MOF]);
break;
switch (dc->cc_size) {
case 4:
gen_helper_evaluate_flags_move_4(cpu_PR[PR_CCS],
- cpu_env, cpu_PR[PR_CCS], cc_result);
+ tcg_env, cpu_PR[PR_CCS], cc_result);
break;
case 2:
gen_helper_evaluate_flags_move_2(cpu_PR[PR_CCS],
- cpu_env, cpu_PR[PR_CCS], cc_result);
+ tcg_env, cpu_PR[PR_CCS], cc_result);
break;
default:
- gen_helper_evaluate_flags(cpu_env);
+ gen_helper_evaluate_flags(tcg_env);
break;
}
break;
case CC_OP_SUB:
case CC_OP_CMP:
if (dc->cc_size == 4) {
- gen_helper_evaluate_flags_sub_4(cpu_PR[PR_CCS], cpu_env,
+ gen_helper_evaluate_flags_sub_4(cpu_PR[PR_CCS], tcg_env,
cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
} else {
- gen_helper_evaluate_flags(cpu_env);
+ gen_helper_evaluate_flags(tcg_env);
}
break;
default:
switch (dc->cc_size) {
case 4:
- gen_helper_evaluate_flags_alu_4(cpu_PR[PR_CCS], cpu_env,
+ gen_helper_evaluate_flags_alu_4(cpu_PR[PR_CCS], tcg_env,
cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
break;
default:
- gen_helper_evaluate_flags(cpu_env);
+ gen_helper_evaluate_flags(tcg_env);
break;
}
break;
cris_cc_mask(dc, CC_MASK_NZ);
c = tcg_constant_tl(dc->op1);
cris_evaluate_flags(dc);
- gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2],
+ gen_helper_btst(cpu_PR[PR_CCS], tcg_env, cpu_R[dc->op2],
c, cpu_PR[PR_CCS]);
cris_alu(dc, CC_OP_MOVE,
cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZ);
cris_evaluate_flags(dc);
- gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2],
+ gen_helper_btst(cpu_PR[PR_CCS], tcg_env, cpu_R[dc->op2],
cpu_R[dc->op1], cpu_PR[PR_CCS]);
cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2],
cpu_R[dc->op2], cpu_R[dc->op2], 4);
c1 = tcg_constant_tl(dc->op1);
c2 = tcg_constant_tl(dc->op2);
cris_cc_mask(dc, 0);
- gen_helper_movl_sreg_reg(cpu_env, c2, c1);
+ gen_helper_movl_sreg_reg(tcg_env, c2, c1);
return 2;
}
static int dec_move_sr(CPUCRISState *env, DisasContext *dc)
c1 = tcg_constant_tl(dc->op1);
c2 = tcg_constant_tl(dc->op2);
cris_cc_mask(dc, 0);
- gen_helper_movl_reg_sreg(cpu_env, c1, c2);
+ gen_helper_movl_reg_sreg(tcg_env, c1, c2);
return 2;
}
cris_cc_mask(dc, 0);
if (dc->op2 == 15) {
- tcg_gen_st_i32(tcg_constant_i32(1), cpu_env,
+ tcg_gen_st_i32(tcg_constant_i32(1), tcg_env,
-offsetof(CRISCPU, env) + offsetof(CPUState, halted));
tcg_gen_movi_tl(env_pc, dc->pc + 2);
t_gen_raise_exception(EXCP_HLT);
/* rfe. */
LOG_DIS("rfe\n");
cris_evaluate_flags(dc);
- gen_helper_rfe(cpu_env);
+ gen_helper_rfe(tcg_env);
dc->base.is_jmp = DISAS_UPDATE;
dc->cpustate_changed = true;
break;
/* rfn. */
LOG_DIS("rfn\n");
cris_evaluate_flags(dc);
- gen_helper_rfn(cpu_env);
+ gen_helper_rfn(tcg_env);
dc->base.is_jmp = DISAS_UPDATE;
dc->cpustate_changed = true;
break;
{
int i;
- cc_x = tcg_global_mem_new(cpu_env,
+ cc_x = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, cc_x), "cc_x");
- cc_src = tcg_global_mem_new(cpu_env,
+ cc_src = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, cc_src), "cc_src");
- cc_dest = tcg_global_mem_new(cpu_env,
+ cc_dest = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, cc_dest),
"cc_dest");
- cc_result = tcg_global_mem_new(cpu_env,
+ cc_result = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, cc_result),
"cc_result");
- cc_op = tcg_global_mem_new(cpu_env,
+ cc_op = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, cc_op), "cc_op");
- cc_size = tcg_global_mem_new(cpu_env,
+ cc_size = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, cc_size),
"cc_size");
- cc_mask = tcg_global_mem_new(cpu_env,
+ cc_mask = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, cc_mask),
"cc_mask");
- env_pc = tcg_global_mem_new(cpu_env,
+ env_pc = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, pc),
"pc");
- env_btarget = tcg_global_mem_new(cpu_env,
+ env_btarget = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, btarget),
"btarget");
- env_btaken = tcg_global_mem_new(cpu_env,
+ env_btaken = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, btaken),
"btaken");
for (i = 0; i < 16; i++) {
- cpu_R[i] = tcg_global_mem_new(cpu_env,
+ cpu_R[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, regs[i]),
regnames_v32[i]);
}
for (i = 0; i < 16; i++) {
- cpu_PR[i] = tcg_global_mem_new(cpu_env,
+ cpu_PR[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, pregs[i]),
pregnames_v32[i]);
}
} else {
/* BTST */
cris_update_cc_op(dc, CC_OP_FLAGS, 4);
- gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->dst],
+ gen_helper_btst(cpu_PR[PR_CCS], tcg_env, cpu_R[dc->dst],
c, cpu_PR[PR_CCS]);
}
break;
LOG_DIS("btst $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
cris_cc_mask(dc, CC_MASK_NZVC);
cris_update_cc_op(dc, CC_OP_FLAGS, 4);
- gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->dst],
+ gen_helper_btst(cpu_PR[PR_CCS], tcg_env, cpu_R[dc->dst],
cpu_R[dc->src], cpu_PR[PR_CCS]);
break;
case CRISV10_REG_DSTEP:
{
int i;
- cc_x = tcg_global_mem_new(cpu_env,
+ cc_x = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, cc_x), "cc_x");
- cc_src = tcg_global_mem_new(cpu_env,
+ cc_src = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, cc_src), "cc_src");
- cc_dest = tcg_global_mem_new(cpu_env,
+ cc_dest = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, cc_dest),
"cc_dest");
- cc_result = tcg_global_mem_new(cpu_env,
+ cc_result = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, cc_result),
"cc_result");
- cc_op = tcg_global_mem_new(cpu_env,
+ cc_op = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, cc_op), "cc_op");
- cc_size = tcg_global_mem_new(cpu_env,
+ cc_size = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, cc_size),
"cc_size");
- cc_mask = tcg_global_mem_new(cpu_env,
+ cc_mask = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, cc_mask),
"cc_mask");
- env_pc = tcg_global_mem_new(cpu_env,
+ env_pc = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, pc),
"pc");
- env_btarget = tcg_global_mem_new(cpu_env,
+ env_btarget = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, btarget),
"btarget");
- env_btaken = tcg_global_mem_new(cpu_env,
+ env_btaken = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, btaken),
"btaken");
for (i = 0; i < 16; i++) {
- cpu_R[i] = tcg_global_mem_new(cpu_env,
+ cpu_R[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, regs[i]),
regnames_v10[i]);
}
for (i = 0; i < 16; i++) {
- cpu_PR[i] = tcg_global_mem_new(cpu_env,
+ cpu_PR[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUCRISState, pregs[i]),
pregnames_v10[i]);
}
const int RdN = insn->regno[0];
TCGv RsV = hex_gpr[insn->regno[1]];
TCGv RtV = hex_gpr[insn->regno[2]];
- gen_helper_A2_add(RdV, cpu_env, RsV, RtV);
+ gen_helper_A2_add(RdV, tcg_env, RsV, RtV);
gen_log_reg_write(ctx, RdN, RdV);
}
const intptr_t VdV_off =
ctx_future_vreg_off(ctx, VdN, 1, true);
TCGv_ptr VdV = tcg_temp_new_ptr();
- tcg_gen_addi_ptr(VdV, cpu_env, VdV_off);
+ tcg_gen_addi_ptr(VdV, tcg_env, VdV_off);
const int VuN = insn->regno[1];
const intptr_t VuV_off =
vreg_src_off(ctx, VuN);
const intptr_t VvV_off =
vreg_src_off(ctx, VvN);
TCGv_ptr VvV = tcg_temp_new_ptr();
- tcg_gen_addi_ptr(VuV, cpu_env, VuV_off);
- tcg_gen_addi_ptr(VvV, cpu_env, VvV_off);
- gen_helper_V6_vaddw(cpu_env, VdV, VuV, VvV);
+ tcg_gen_addi_ptr(VuV, tcg_env, VuV_off);
+ tcg_gen_addi_ptr(VvV, tcg_env, VvV_off);
+ gen_helper_V6_vaddw(tcg_env, VdV, VuV, VvV);
}
Notice that we also generate a variable named <operand>_off for each operand of
*/
#define fGEN_TCG_A5_ACS(SHORTCODE) \
do { \
- gen_helper_vacsh_pred(PeV, cpu_env, RxxV, RssV, RttV); \
- gen_helper_vacsh_val(RxxV, cpu_env, RxxV, RssV, RttV, \
+ gen_helper_vacsh_pred(PeV, tcg_env, RxxV, RssV, RttV); \
+ gen_helper_vacsh_val(RxxV, tcg_env, RxxV, RssV, RttV, \
tcg_constant_tl(ctx->need_commit)); \
} while (0)
#define fGEN_TCG_F2_sfrecipa(SHORTCODE) \
do { \
TCGv_i64 tmp = tcg_temp_new_i64(); \
- gen_helper_sfrecipa(tmp, cpu_env, RsV, RtV); \
+ gen_helper_sfrecipa(tmp, tcg_env, RsV, RtV); \
tcg_gen_extrh_i64_i32(RdV, tmp); \
tcg_gen_extrl_i64_i32(PeV, tmp); \
} while (0)
#define fGEN_TCG_F2_sfinvsqrta(SHORTCODE) \
do { \
TCGv_i64 tmp = tcg_temp_new_i64(); \
- gen_helper_sfinvsqrta(tmp, cpu_env, RsV); \
+ gen_helper_sfinvsqrta(tmp, tcg_env, RsV); \
tcg_gen_extrh_i64_i32(RdV, tmp); \
tcg_gen_extrl_i64_i32(PeV, tmp); \
} while (0)
/* Floating point */
#define fGEN_TCG_F2_conv_sf2df(SHORTCODE) \
- gen_helper_conv_sf2df(RddV, cpu_env, RsV)
+ gen_helper_conv_sf2df(RddV, tcg_env, RsV)
#define fGEN_TCG_F2_conv_df2sf(SHORTCODE) \
- gen_helper_conv_df2sf(RdV, cpu_env, RssV)
+ gen_helper_conv_df2sf(RdV, tcg_env, RssV)
#define fGEN_TCG_F2_conv_uw2sf(SHORTCODE) \
- gen_helper_conv_uw2sf(RdV, cpu_env, RsV)
+ gen_helper_conv_uw2sf(RdV, tcg_env, RsV)
#define fGEN_TCG_F2_conv_uw2df(SHORTCODE) \
- gen_helper_conv_uw2df(RddV, cpu_env, RsV)
+ gen_helper_conv_uw2df(RddV, tcg_env, RsV)
#define fGEN_TCG_F2_conv_w2sf(SHORTCODE) \
- gen_helper_conv_w2sf(RdV, cpu_env, RsV)
+ gen_helper_conv_w2sf(RdV, tcg_env, RsV)
#define fGEN_TCG_F2_conv_w2df(SHORTCODE) \
- gen_helper_conv_w2df(RddV, cpu_env, RsV)
+ gen_helper_conv_w2df(RddV, tcg_env, RsV)
#define fGEN_TCG_F2_conv_ud2sf(SHORTCODE) \
- gen_helper_conv_ud2sf(RdV, cpu_env, RssV)
+ gen_helper_conv_ud2sf(RdV, tcg_env, RssV)
#define fGEN_TCG_F2_conv_ud2df(SHORTCODE) \
- gen_helper_conv_ud2df(RddV, cpu_env, RssV)
+ gen_helper_conv_ud2df(RddV, tcg_env, RssV)
#define fGEN_TCG_F2_conv_d2sf(SHORTCODE) \
- gen_helper_conv_d2sf(RdV, cpu_env, RssV)
+ gen_helper_conv_d2sf(RdV, tcg_env, RssV)
#define fGEN_TCG_F2_conv_d2df(SHORTCODE) \
- gen_helper_conv_d2df(RddV, cpu_env, RssV)
+ gen_helper_conv_d2df(RddV, tcg_env, RssV)
#define fGEN_TCG_F2_conv_sf2uw(SHORTCODE) \
- gen_helper_conv_sf2uw(RdV, cpu_env, RsV)
+ gen_helper_conv_sf2uw(RdV, tcg_env, RsV)
#define fGEN_TCG_F2_conv_sf2w(SHORTCODE) \
- gen_helper_conv_sf2w(RdV, cpu_env, RsV)
+ gen_helper_conv_sf2w(RdV, tcg_env, RsV)
#define fGEN_TCG_F2_conv_sf2ud(SHORTCODE) \
- gen_helper_conv_sf2ud(RddV, cpu_env, RsV)
+ gen_helper_conv_sf2ud(RddV, tcg_env, RsV)
#define fGEN_TCG_F2_conv_sf2d(SHORTCODE) \
- gen_helper_conv_sf2d(RddV, cpu_env, RsV)
+ gen_helper_conv_sf2d(RddV, tcg_env, RsV)
#define fGEN_TCG_F2_conv_df2uw(SHORTCODE) \
- gen_helper_conv_df2uw(RdV, cpu_env, RssV)
+ gen_helper_conv_df2uw(RdV, tcg_env, RssV)
#define fGEN_TCG_F2_conv_df2w(SHORTCODE) \
- gen_helper_conv_df2w(RdV, cpu_env, RssV)
+ gen_helper_conv_df2w(RdV, tcg_env, RssV)
#define fGEN_TCG_F2_conv_df2ud(SHORTCODE) \
- gen_helper_conv_df2ud(RddV, cpu_env, RssV)
+ gen_helper_conv_df2ud(RddV, tcg_env, RssV)
#define fGEN_TCG_F2_conv_df2d(SHORTCODE) \
- gen_helper_conv_df2d(RddV, cpu_env, RssV)
+ gen_helper_conv_df2d(RddV, tcg_env, RssV)
#define fGEN_TCG_F2_conv_sf2uw_chop(SHORTCODE) \
- gen_helper_conv_sf2uw_chop(RdV, cpu_env, RsV)
+ gen_helper_conv_sf2uw_chop(RdV, tcg_env, RsV)
#define fGEN_TCG_F2_conv_sf2w_chop(SHORTCODE) \
- gen_helper_conv_sf2w_chop(RdV, cpu_env, RsV)
+ gen_helper_conv_sf2w_chop(RdV, tcg_env, RsV)
#define fGEN_TCG_F2_conv_sf2ud_chop(SHORTCODE) \
- gen_helper_conv_sf2ud_chop(RddV, cpu_env, RsV)
+ gen_helper_conv_sf2ud_chop(RddV, tcg_env, RsV)
#define fGEN_TCG_F2_conv_sf2d_chop(SHORTCODE) \
- gen_helper_conv_sf2d_chop(RddV, cpu_env, RsV)
+ gen_helper_conv_sf2d_chop(RddV, tcg_env, RsV)
#define fGEN_TCG_F2_conv_df2uw_chop(SHORTCODE) \
- gen_helper_conv_df2uw_chop(RdV, cpu_env, RssV)
+ gen_helper_conv_df2uw_chop(RdV, tcg_env, RssV)
#define fGEN_TCG_F2_conv_df2w_chop(SHORTCODE) \
- gen_helper_conv_df2w_chop(RdV, cpu_env, RssV)
+ gen_helper_conv_df2w_chop(RdV, tcg_env, RssV)
#define fGEN_TCG_F2_conv_df2ud_chop(SHORTCODE) \
- gen_helper_conv_df2ud_chop(RddV, cpu_env, RssV)
+ gen_helper_conv_df2ud_chop(RddV, tcg_env, RssV)
#define fGEN_TCG_F2_conv_df2d_chop(SHORTCODE) \
- gen_helper_conv_df2d_chop(RddV, cpu_env, RssV)
+ gen_helper_conv_df2d_chop(RddV, tcg_env, RssV)
#define fGEN_TCG_F2_sfadd(SHORTCODE) \
- gen_helper_sfadd(RdV, cpu_env, RsV, RtV)
+ gen_helper_sfadd(RdV, tcg_env, RsV, RtV)
#define fGEN_TCG_F2_sfsub(SHORTCODE) \
- gen_helper_sfsub(RdV, cpu_env, RsV, RtV)
+ gen_helper_sfsub(RdV, tcg_env, RsV, RtV)
#define fGEN_TCG_F2_sfcmpeq(SHORTCODE) \
- gen_helper_sfcmpeq(PdV, cpu_env, RsV, RtV)
+ gen_helper_sfcmpeq(PdV, tcg_env, RsV, RtV)
#define fGEN_TCG_F2_sfcmpgt(SHORTCODE) \
- gen_helper_sfcmpgt(PdV, cpu_env, RsV, RtV)
+ gen_helper_sfcmpgt(PdV, tcg_env, RsV, RtV)
#define fGEN_TCG_F2_sfcmpge(SHORTCODE) \
- gen_helper_sfcmpge(PdV, cpu_env, RsV, RtV)
+ gen_helper_sfcmpge(PdV, tcg_env, RsV, RtV)
#define fGEN_TCG_F2_sfcmpuo(SHORTCODE) \
- gen_helper_sfcmpuo(PdV, cpu_env, RsV, RtV)
+ gen_helper_sfcmpuo(PdV, tcg_env, RsV, RtV)
#define fGEN_TCG_F2_sfmax(SHORTCODE) \
- gen_helper_sfmax(RdV, cpu_env, RsV, RtV)
+ gen_helper_sfmax(RdV, tcg_env, RsV, RtV)
#define fGEN_TCG_F2_sfmin(SHORTCODE) \
- gen_helper_sfmin(RdV, cpu_env, RsV, RtV)
+ gen_helper_sfmin(RdV, tcg_env, RsV, RtV)
#define fGEN_TCG_F2_sfclass(SHORTCODE) \
do { \
TCGv imm = tcg_constant_tl(uiV); \
- gen_helper_sfclass(PdV, cpu_env, RsV, imm); \
+ gen_helper_sfclass(PdV, tcg_env, RsV, imm); \
} while (0)
#define fGEN_TCG_F2_sffixupn(SHORTCODE) \
- gen_helper_sffixupn(RdV, cpu_env, RsV, RtV)
+ gen_helper_sffixupn(RdV, tcg_env, RsV, RtV)
#define fGEN_TCG_F2_sffixupd(SHORTCODE) \
- gen_helper_sffixupd(RdV, cpu_env, RsV, RtV)
+ gen_helper_sffixupd(RdV, tcg_env, RsV, RtV)
#define fGEN_TCG_F2_sffixupr(SHORTCODE) \
- gen_helper_sffixupr(RdV, cpu_env, RsV)
+ gen_helper_sffixupr(RdV, tcg_env, RsV)
#define fGEN_TCG_F2_dfadd(SHORTCODE) \
- gen_helper_dfadd(RddV, cpu_env, RssV, RttV)
+ gen_helper_dfadd(RddV, tcg_env, RssV, RttV)
#define fGEN_TCG_F2_dfsub(SHORTCODE) \
- gen_helper_dfsub(RddV, cpu_env, RssV, RttV)
+ gen_helper_dfsub(RddV, tcg_env, RssV, RttV)
#define fGEN_TCG_F2_dfmax(SHORTCODE) \
- gen_helper_dfmax(RddV, cpu_env, RssV, RttV)
+ gen_helper_dfmax(RddV, tcg_env, RssV, RttV)
#define fGEN_TCG_F2_dfmin(SHORTCODE) \
- gen_helper_dfmin(RddV, cpu_env, RssV, RttV)
+ gen_helper_dfmin(RddV, tcg_env, RssV, RttV)
#define fGEN_TCG_F2_dfcmpeq(SHORTCODE) \
- gen_helper_dfcmpeq(PdV, cpu_env, RssV, RttV)
+ gen_helper_dfcmpeq(PdV, tcg_env, RssV, RttV)
#define fGEN_TCG_F2_dfcmpgt(SHORTCODE) \
- gen_helper_dfcmpgt(PdV, cpu_env, RssV, RttV)
+ gen_helper_dfcmpgt(PdV, tcg_env, RssV, RttV)
#define fGEN_TCG_F2_dfcmpge(SHORTCODE) \
- gen_helper_dfcmpge(PdV, cpu_env, RssV, RttV)
+ gen_helper_dfcmpge(PdV, tcg_env, RssV, RttV)
#define fGEN_TCG_F2_dfcmpuo(SHORTCODE) \
- gen_helper_dfcmpuo(PdV, cpu_env, RssV, RttV)
+ gen_helper_dfcmpuo(PdV, tcg_env, RssV, RttV)
#define fGEN_TCG_F2_dfclass(SHORTCODE) \
do { \
TCGv imm = tcg_constant_tl(uiV); \
- gen_helper_dfclass(PdV, cpu_env, RssV, imm); \
+ gen_helper_dfclass(PdV, tcg_env, RssV, imm); \
} while (0)
#define fGEN_TCG_F2_sfmpy(SHORTCODE) \
- gen_helper_sfmpy(RdV, cpu_env, RsV, RtV)
+ gen_helper_sfmpy(RdV, tcg_env, RsV, RtV)
#define fGEN_TCG_F2_sffma(SHORTCODE) \
- gen_helper_sffma(RxV, cpu_env, RxV, RsV, RtV)
+ gen_helper_sffma(RxV, tcg_env, RxV, RsV, RtV)
#define fGEN_TCG_F2_sffma_sc(SHORTCODE) \
- gen_helper_sffma_sc(RxV, cpu_env, RxV, RsV, RtV, PuV)
+ gen_helper_sffma_sc(RxV, tcg_env, RxV, RsV, RtV, PuV)
#define fGEN_TCG_F2_sffms(SHORTCODE) \
- gen_helper_sffms(RxV, cpu_env, RxV, RsV, RtV)
+ gen_helper_sffms(RxV, tcg_env, RxV, RsV, RtV)
#define fGEN_TCG_F2_sffma_lib(SHORTCODE) \
- gen_helper_sffma_lib(RxV, cpu_env, RxV, RsV, RtV)
+ gen_helper_sffma_lib(RxV, tcg_env, RxV, RsV, RtV)
#define fGEN_TCG_F2_sffms_lib(SHORTCODE) \
- gen_helper_sffms_lib(RxV, cpu_env, RxV, RsV, RtV)
+ gen_helper_sffms_lib(RxV, tcg_env, RxV, RsV, RtV)
#define fGEN_TCG_F2_dfmpyfix(SHORTCODE) \
- gen_helper_dfmpyfix(RddV, cpu_env, RssV, RttV)
+ gen_helper_dfmpyfix(RddV, tcg_env, RssV, RttV)
#define fGEN_TCG_F2_dfmpyhh(SHORTCODE) \
- gen_helper_dfmpyhh(RxxV, cpu_env, RxxV, RssV, RttV)
+ gen_helper_dfmpyhh(RxxV, tcg_env, RxxV, RssV, RttV)
/* Nothing to do for these in qemu, need to suppress compiler warnings */
#define fGEN_TCG_Y4_l2fetch(SHORTCODE) \
uiV = uiV; \
tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->pkt->pc); \
TCGv excp = tcg_constant_tl(HEX_EXCP_TRAP0); \
- gen_helper_raise_exception(cpu_env, excp); \
+ gen_helper_raise_exception(tcg_env, excp); \
} while (0)
#endif
if not hex_common.skip_qemu_helper(tag):
f.write(f" TCGv_ptr {regtype}{regid}V = " "tcg_temp_new_ptr();\n")
f.write(
- f" tcg_gen_addi_ptr({regtype}{regid}V, cpu_env, "
+ f" tcg_gen_addi_ptr({regtype}{regid}V, tcg_env, "
f"{regtype}{regid}V_off);\n"
)
elif regid in {"uu", "vv", "xx"}:
if not hex_common.skip_qemu_helper(tag):
f.write(f" TCGv_ptr {regtype}{regid}V = " "tcg_temp_new_ptr();\n")
f.write(
- f" tcg_gen_addi_ptr({regtype}{regid}V, cpu_env, "
+ f" tcg_gen_addi_ptr({regtype}{regid}V, tcg_env, "
f"{regtype}{regid}V_off);\n"
)
elif regid in {"s", "u", "v", "w"}:
if not hex_common.skip_qemu_helper(tag):
f.write(f" TCGv_ptr {regtype}{regid}V = " "tcg_temp_new_ptr();\n")
f.write(
- f" tcg_gen_addi_ptr({regtype}{regid}V, cpu_env, "
+ f" tcg_gen_addi_ptr({regtype}{regid}V, tcg_env, "
f"{regtype}{regid}V_off);\n"
)
else:
if not hex_common.skip_qemu_helper(tag):
f.write(f" TCGv_ptr {regtype}{regid}V = " "tcg_temp_new_ptr();\n")
f.write(
- f" tcg_gen_addi_ptr({regtype}{regid}V, cpu_env, "
+ f" tcg_gen_addi_ptr({regtype}{regid}V, tcg_env, "
f"{regtype}{regid}V_off);\n"
)
elif regid in {"s", "t", "u", "v"}:
elif regid in {"s", "u", "v", "w"}:
if not hex_common.skip_qemu_helper(tag):
f.write(
- f" tcg_gen_addi_ptr({regtype}{regid}V, cpu_env, "
+ f" tcg_gen_addi_ptr({regtype}{regid}V, tcg_env, "
f"{regtype}{regid}V_off);\n"
)
elif regid in {"x", "y"}:
if regid in {"s", "t", "u", "v"}:
if not hex_common.skip_qemu_helper(tag):
f.write(
- f" tcg_gen_addi_ptr({regtype}{regid}V, cpu_env, "
+ f" tcg_gen_addi_ptr({regtype}{regid}V, tcg_env, "
f"{regtype}{regid}V_off);\n"
)
elif regid in {"x"}:
## if hex_common.skip_qemu_helper(tag) is True
## <GEN> is fGEN_TCG_A2_add({ RdV=RsV+RtV;});
## if hex_common.skip_qemu_helper(tag) is False
-## <GEN> is gen_helper_A2_add(RdV, cpu_env, RsV, RtV);
+## <GEN> is gen_helper_A2_add(RdV, tcg_env, RsV, RtV);
##
def gen_tcg_func(f, tag, regs, imms):
f.write(f"static void generate_{tag}(DisasContext *ctx)\n")
i += 1
if i > 0:
f.write(", ")
- f.write("cpu_env")
+ f.write("tcg_env")
i = 1
## For conditional instructions, we pass in the destination register
if "A_CONDEXEC" in hex_common.attribdict[tag]:
#define fGEN_TCG_V6_vhist(SHORTCODE) \
if (!ctx->pre_commit) { \
assert_vhist_tmp(ctx); \
- gen_helper_vhist(cpu_env); \
+ gen_helper_vhist(tcg_env); \
}
#define fGEN_TCG_V6_vhistq(SHORTCODE) \
do { \
sizeof(MMVector), sizeof(MMVector)); \
} else { \
assert_vhist_tmp(ctx); \
- gen_helper_vhistq(cpu_env); \
+ gen_helper_vhistq(tcg_env); \
} \
} while (0)
#define fGEN_TCG_V6_vwhist256(SHORTCODE) \
if (!ctx->pre_commit) { \
assert_vhist_tmp(ctx); \
- gen_helper_vwhist256(cpu_env); \
+ gen_helper_vwhist256(tcg_env); \
}
#define fGEN_TCG_V6_vwhist256q(SHORTCODE) \
do { \
sizeof(MMVector), sizeof(MMVector)); \
} else { \
assert_vhist_tmp(ctx); \
- gen_helper_vwhist256q(cpu_env); \
+ gen_helper_vwhist256q(tcg_env); \
} \
} while (0)
#define fGEN_TCG_V6_vwhist256_sat(SHORTCODE) \
if (!ctx->pre_commit) { \
assert_vhist_tmp(ctx); \
- gen_helper_vwhist256_sat(cpu_env); \
+ gen_helper_vwhist256_sat(tcg_env); \
}
#define fGEN_TCG_V6_vwhist256q_sat(SHORTCODE) \
do { \
sizeof(MMVector), sizeof(MMVector)); \
} else { \
assert_vhist_tmp(ctx); \
- gen_helper_vwhist256q_sat(cpu_env); \
+ gen_helper_vwhist256q_sat(tcg_env); \
} \
} while (0)
#define fGEN_TCG_V6_vwhist128(SHORTCODE) \
if (!ctx->pre_commit) { \
assert_vhist_tmp(ctx); \
- gen_helper_vwhist128(cpu_env); \
+ gen_helper_vwhist128(tcg_env); \
}
#define fGEN_TCG_V6_vwhist128q(SHORTCODE) \
do { \
sizeof(MMVector), sizeof(MMVector)); \
} else { \
assert_vhist_tmp(ctx); \
- gen_helper_vwhist128q(cpu_env); \
+ gen_helper_vwhist128q(tcg_env); \
} \
} while (0)
#define fGEN_TCG_V6_vwhist128m(SHORTCODE) \
if (!ctx->pre_commit) { \
TCGv tcgv_uiV = tcg_constant_tl(uiV); \
assert_vhist_tmp(ctx); \
- gen_helper_vwhist128m(cpu_env, tcgv_uiV); \
+ gen_helper_vwhist128m(tcg_env, tcgv_uiV); \
}
#define fGEN_TCG_V6_vwhist128qm(SHORTCODE) \
do { \
} else { \
TCGv tcgv_uiV = tcg_constant_tl(uiV); \
assert_vhist_tmp(ctx); \
- gen_helper_vwhist128qm(cpu_env, tcgv_uiV); \
+ gen_helper_vwhist128qm(tcg_env, tcgv_uiV); \
} \
} while (0)
tcg_gen_mov_tl(hex_store_val32[slot], src);
}
-void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot)
+void gen_store1(TCGv_env tcg_env, TCGv vaddr, TCGv src, uint32_t slot)
{
gen_store32(vaddr, src, 1, slot);
}
-void gen_store1i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot)
+void gen_store1i(TCGv_env tcg_env, TCGv vaddr, int32_t src, uint32_t slot)
{
TCGv tmp = tcg_constant_tl(src);
- gen_store1(cpu_env, vaddr, tmp, slot);
+ gen_store1(tcg_env, vaddr, tmp, slot);
}
-void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot)
+void gen_store2(TCGv_env tcg_env, TCGv vaddr, TCGv src, uint32_t slot)
{
gen_store32(vaddr, src, 2, slot);
}
-void gen_store2i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot)
+void gen_store2i(TCGv_env tcg_env, TCGv vaddr, int32_t src, uint32_t slot)
{
TCGv tmp = tcg_constant_tl(src);
- gen_store2(cpu_env, vaddr, tmp, slot);
+ gen_store2(tcg_env, vaddr, tmp, slot);
}
-void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot)
+void gen_store4(TCGv_env tcg_env, TCGv vaddr, TCGv src, uint32_t slot)
{
gen_store32(vaddr, src, 4, slot);
}
-void gen_store4i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot)
+void gen_store4i(TCGv_env tcg_env, TCGv vaddr, int32_t src, uint32_t slot)
{
TCGv tmp = tcg_constant_tl(src);
- gen_store4(cpu_env, vaddr, tmp, slot);
+ gen_store4(tcg_env, vaddr, tmp, slot);
}
-void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src, uint32_t slot)
+void gen_store8(TCGv_env tcg_env, TCGv vaddr, TCGv_i64 src, uint32_t slot)
{
tcg_gen_mov_tl(hex_store_addr[slot], vaddr);
tcg_gen_movi_tl(hex_store_width[slot], 8);
tcg_gen_mov_i64(hex_store_val64[slot], src);
}
-void gen_store8i(TCGv_env cpu_env, TCGv vaddr, int64_t src, uint32_t slot)
+void gen_store8i(TCGv_env tcg_env, TCGv vaddr, int64_t src, uint32_t slot)
{
TCGv_i64 tmp = tcg_constant_i64(src);
- gen_store8(cpu_env, vaddr, tmp, slot);
+ gen_store8(tcg_env, vaddr, tmp, slot);
}
TCGv gen_8bitsof(TCGv result, TCGv value)
TCGv_i64 frame;
tcg_gen_addi_tl(r30, r29, -8);
frame = gen_frame_scramble();
- gen_store8(cpu_env, r30, frame, ctx->insn->slot);
+ gen_store8(tcg_env, r30, frame, ctx->insn->slot);
gen_log_reg_write(ctx, HEX_REG_FP, r30);
gen_framecheck(r30, framesize);
tcg_gen_subi_tl(r29, r30, framesize);
for (int i = 0; i < sizeof(MMVector) / 8; i++) {
tcg_gen_qemu_ld_i64(tmp, src, ctx->mem_idx, MO_TEUQ);
tcg_gen_addi_tl(src, src, 8);
- tcg_gen_st_i64(tmp, cpu_env, dstoff + i * 8);
+ tcg_gen_st_i64(tmp, tcg_env, dstoff + i * 8);
}
}
if (is_gather_store_insn(ctx)) {
TCGv sl = tcg_constant_tl(slot);
- gen_helper_gather_store(cpu_env, EA, sl);
+ gen_helper_gather_store(tcg_env, EA, sl);
return;
}
TCGv_i64 ones = tcg_constant_i64(~0);
for (int i = 0; i < sizeof(MMVector) / 8; i++) {
- tcg_gen_ld_i64(tmp, cpu_env, srcoff + i * 8);
+ tcg_gen_ld_i64(tmp, tcg_env, srcoff + i * 8);
tcg_gen_movi_i64(mask, 0);
for (int j = 0; j < 8; j += size) {
tcg_gen_deposit_i64(mask, mask, bits, j, size);
}
- tcg_gen_st8_i64(mask, cpu_env, dstoff + i);
+ tcg_gen_st8_i64(mask, tcg_env, dstoff + i);
}
}
{
TCGv size = tcg_constant_tl(s);
TCGv mem_idx = tcg_constant_tl(mi);
- gen_helper_probe_noshuf_load(cpu_env, va, size, mem_idx);
+ gen_helper_probe_noshuf_load(tcg_env, va, size, mem_idx);
}
/*
/* Lookup the effective address EA */
find_variable(c, locp, ea, ea);
src_m = rvalue_materialize(c, locp, &src_m);
- OUT(c, locp, "gen_store", &mem_width, "(cpu_env, ", ea, ", ", &src_m);
+ OUT(c, locp, "gen_store", &mem_width, "(tcg_env, ", ea, ", ", &src_m);
OUT(c, locp, ", insn->slot);\n");
}
__builtin_choose_expr(TYPE_TCGV(X), \
gen_store1, (void)0))
#define MEM_STORE1(VA, DATA, SLOT) \
- MEM_STORE1_FUNC(DATA)(cpu_env, VA, DATA, SLOT)
+ MEM_STORE1_FUNC(DATA)(tcg_env, VA, DATA, SLOT)
#define MEM_STORE2_FUNC(X) \
__builtin_choose_expr(TYPE_INT(X), \
__builtin_choose_expr(TYPE_TCGV(X), \
gen_store2, (void)0))
#define MEM_STORE2(VA, DATA, SLOT) \
- MEM_STORE2_FUNC(DATA)(cpu_env, VA, DATA, SLOT)
+ MEM_STORE2_FUNC(DATA)(tcg_env, VA, DATA, SLOT)
#define MEM_STORE4_FUNC(X) \
__builtin_choose_expr(TYPE_INT(X), \
__builtin_choose_expr(TYPE_TCGV(X), \
gen_store4, (void)0))
#define MEM_STORE4(VA, DATA, SLOT) \
- MEM_STORE4_FUNC(DATA)(cpu_env, VA, DATA, SLOT)
+ MEM_STORE4_FUNC(DATA)(tcg_env, VA, DATA, SLOT)
#define MEM_STORE8_FUNC(X) \
__builtin_choose_expr(TYPE_INT(X), \
__builtin_choose_expr(TYPE_TCGV_I64(X), \
gen_store8, (void)0))
#define MEM_STORE8(VA, DATA, SLOT) \
- MEM_STORE8_FUNC(DATA)(cpu_env, VA, DATA, SLOT)
+ MEM_STORE8_FUNC(DATA)(tcg_env, VA, DATA, SLOT)
#else
#define MEM_LOAD1s(VA) ((int8_t)mem_load1(env, pkt_has_store_s1, slot, VA))
#define MEM_LOAD1u(VA) ((uint8_t)mem_load1(env, pkt_has_store_s1, slot, VA))
static void gen_exception_raw(int excp)
{
- gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
+ gen_helper_raise_exception(tcg_env, tcg_constant_i32(excp));
}
static void gen_exec_counters(DisasContext *ctx)
if (HEX_DEBUG) {
/* Handy place to set a breakpoint before the packet executes */
- gen_helper_debug_start_packet(cpu_env);
+ gen_helper_debug_start_packet(tcg_env);
}
/* Initialize the runtime state for packet semantics */
if (HEX_DEBUG) {
TCGv slot = tcg_constant_tl(slot_num);
TCGv check = tcg_constant_tl(ctx->store_width[slot_num]);
- gen_helper_debug_check_store_width(cpu_env, slot, check);
+ gen_helper_debug_check_store_width(tcg_env, slot, check);
}
}
* avoid branching based on the width at runtime.
*/
TCGv slot = tcg_constant_tl(slot_num);
- gen_helper_commit_store(cpu_env, slot);
+ gen_helper_commit_store(tcg_env, slot);
}
}
}
}
if (pkt_has_hvx_store(ctx->pkt)) {
- gen_helper_commit_hvx_stores(cpu_env);
+ gen_helper_commit_hvx_stores(tcg_env);
}
}
} else if (has_hvx_store) {
if (!has_store_s0 && !has_store_s1) {
TCGv mem_idx = tcg_constant_tl(ctx->mem_idx);
- gen_helper_probe_hvx_stores(cpu_env, mem_idx);
+ gen_helper_probe_hvx_stores(tcg_env, mem_idx);
} else {
int mask = 0;
}
mask = FIELD_DP32(mask, PROBE_PKT_SCALAR_HVX_STORES, MMU_IDX,
ctx->mem_idx);
- gen_helper_probe_pkt_scalar_hvx_stores(cpu_env,
+ gen_helper_probe_pkt_scalar_hvx_stores(tcg_env,
tcg_constant_tl(mask));
}
} else if (has_store_s0 && has_store_s1) {
FIELD_DP32(args, PROBE_PKT_SCALAR_STORE_S0, IS_PREDICATED, 1);
}
TCGv args_tcgv = tcg_constant_tl(args);
- gen_helper_probe_pkt_scalar_store_s0(cpu_env, args_tcgv);
+ gen_helper_probe_pkt_scalar_store_s0(tcg_env, args_tcgv);
}
process_store_log(ctx);
tcg_constant_tl(pkt->pkt_has_store_s1 && !pkt->pkt_has_dczeroa);
/* Handy place to set a breakpoint at the end of execution */
- gen_helper_debug_commit_end(cpu_env, tcg_constant_tl(ctx->pkt->pc),
+ gen_helper_debug_commit_end(tcg_env, tcg_constant_tl(ctx->pkt->pc),
ctx->pred_written, has_st0, has_st1);
}
opcode_init();
for (i = 0; i < TOTAL_PER_THREAD_REGS; i++) {
- hex_gpr[i] = tcg_global_mem_new(cpu_env,
+ hex_gpr[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUHexagonState, gpr[i]),
hexagon_regnames[i]);
if (HEX_DEBUG) {
snprintf(reg_written_names[i], NAME_LEN, "reg_written_%s",
hexagon_regnames[i]);
- hex_reg_written[i] = tcg_global_mem_new(cpu_env,
+ hex_reg_written[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUHexagonState, reg_written[i]),
reg_written_names[i]);
}
}
- hex_new_value_usr = tcg_global_mem_new(cpu_env,
+ hex_new_value_usr = tcg_global_mem_new(tcg_env,
offsetof(CPUHexagonState, new_value_usr), "new_value_usr");
for (i = 0; i < NUM_PREGS; i++) {
- hex_pred[i] = tcg_global_mem_new(cpu_env,
+ hex_pred[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUHexagonState, pred[i]),
hexagon_prednames[i]);
}
- hex_slot_cancelled = tcg_global_mem_new(cpu_env,
+ hex_slot_cancelled = tcg_global_mem_new(tcg_env,
offsetof(CPUHexagonState, slot_cancelled), "slot_cancelled");
- hex_llsc_addr = tcg_global_mem_new(cpu_env,
+ hex_llsc_addr = tcg_global_mem_new(tcg_env,
offsetof(CPUHexagonState, llsc_addr), "llsc_addr");
- hex_llsc_val = tcg_global_mem_new(cpu_env,
+ hex_llsc_val = tcg_global_mem_new(tcg_env,
offsetof(CPUHexagonState, llsc_val), "llsc_val");
- hex_llsc_val_i64 = tcg_global_mem_new_i64(cpu_env,
+ hex_llsc_val_i64 = tcg_global_mem_new_i64(tcg_env,
offsetof(CPUHexagonState, llsc_val_i64), "llsc_val_i64");
for (i = 0; i < STORES_MAX; i++) {
snprintf(store_addr_names[i], NAME_LEN, "store_addr_%d", i);
- hex_store_addr[i] = tcg_global_mem_new(cpu_env,
+ hex_store_addr[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUHexagonState, mem_log_stores[i].va),
store_addr_names[i]);
snprintf(store_width_names[i], NAME_LEN, "store_width_%d", i);
- hex_store_width[i] = tcg_global_mem_new(cpu_env,
+ hex_store_width[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUHexagonState, mem_log_stores[i].width),
store_width_names[i]);
snprintf(store_val32_names[i], NAME_LEN, "store_val32_%d", i);
- hex_store_val32[i] = tcg_global_mem_new(cpu_env,
+ hex_store_val32[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUHexagonState, mem_log_stores[i].data32),
store_val32_names[i]);
snprintf(store_val64_names[i], NAME_LEN, "store_val64_%d", i);
- hex_store_val64[i] = tcg_global_mem_new_i64(cpu_env,
+ hex_store_val64[i] = tcg_global_mem_new_i64(tcg_env,
offsetof(CPUHexagonState, mem_log_stores[i].data64),
store_val64_names[i]);
}
for (int i = 0; i < VSTORES_MAX; i++) {
snprintf(vstore_addr_names[i], NAME_LEN, "vstore_addr_%d", i);
- hex_vstore_addr[i] = tcg_global_mem_new(cpu_env,
+ hex_vstore_addr[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUHexagonState, vstore[i].va),
vstore_addr_names[i]);
snprintf(vstore_size_names[i], NAME_LEN, "vstore_size_%d", i);
- hex_vstore_size[i] = tcg_global_mem_new(cpu_env,
+ hex_vstore_size[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUHexagonState, vstore[i].size),
vstore_size_names[i]);
snprintf(vstore_pending_names[i], NAME_LEN, "vstore_pending_%d", i);
- hex_vstore_pending[i] = tcg_global_mem_new(cpu_env,
+ hex_vstore_pending[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUHexagonState, vstore_pending[i]),
vstore_pending_names[i]);
}
cpu_gr[0] = NULL;
for (i = 1; i < 32; i++) {
- cpu_gr[i] = tcg_global_mem_new(cpu_env,
+ cpu_gr[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUHPPAState, gr[i]),
gr_names[i]);
}
for (i = 0; i < 4; i++) {
- cpu_sr[i] = tcg_global_mem_new_i64(cpu_env,
+ cpu_sr[i] = tcg_global_mem_new_i64(tcg_env,
offsetof(CPUHPPAState, sr[i]),
sr_names[i]);
}
- cpu_srH = tcg_global_mem_new_i64(cpu_env,
+ cpu_srH = tcg_global_mem_new_i64(tcg_env,
offsetof(CPUHPPAState, sr[4]),
sr_names[4]);
for (i = 0; i < ARRAY_SIZE(vars); ++i) {
const GlobalVar *v = &vars[i];
- *v->var = tcg_global_mem_new(cpu_env, v->ofs, v->name);
+ *v->var = tcg_global_mem_new(tcg_env, v->ofs, v->name);
}
- cpu_iasq_f = tcg_global_mem_new_i64(cpu_env,
+ cpu_iasq_f = tcg_global_mem_new_i64(tcg_env,
offsetof(CPUHPPAState, iasq_f),
"iasq_f");
- cpu_iasq_b = tcg_global_mem_new_i64(cpu_env,
+ cpu_iasq_b = tcg_global_mem_new_i64(tcg_env,
offsetof(CPUHPPAState, iasq_b),
"iasq_b");
}
static TCGv_i32 load_frw_i32(unsigned rt)
{
TCGv_i32 ret = tcg_temp_new_i32();
- tcg_gen_ld_i32(ret, cpu_env,
+ tcg_gen_ld_i32(ret, tcg_env,
offsetof(CPUHPPAState, fr[rt & 31])
+ (rt & 32 ? LO_OFS : HI_OFS));
return ret;
if (rt == 0) {
tcg_gen_movi_i64(ret, 0);
} else {
- tcg_gen_ld32u_i64(ret, cpu_env,
+ tcg_gen_ld32u_i64(ret, tcg_env,
offsetof(CPUHPPAState, fr[rt & 31])
+ (rt & 32 ? LO_OFS : HI_OFS));
}
static void save_frw_i32(unsigned rt, TCGv_i32 val)
{
- tcg_gen_st_i32(val, cpu_env,
+ tcg_gen_st_i32(val, tcg_env,
offsetof(CPUHPPAState, fr[rt & 31])
+ (rt & 32 ? LO_OFS : HI_OFS));
}
static TCGv_i64 load_frd(unsigned rt)
{
TCGv_i64 ret = tcg_temp_new_i64();
- tcg_gen_ld_i64(ret, cpu_env, offsetof(CPUHPPAState, fr[rt]));
+ tcg_gen_ld_i64(ret, tcg_env, offsetof(CPUHPPAState, fr[rt]));
return ret;
}
static void save_frd(unsigned rt, TCGv_i64 val)
{
- tcg_gen_st_i64(val, cpu_env, offsetof(CPUHPPAState, fr[rt]));
+ tcg_gen_st_i64(val, tcg_env, offsetof(CPUHPPAState, fr[rt]));
}
static void load_spr(DisasContext *ctx, TCGv_i64 dest, unsigned reg)
} else if (ctx->tb_flags & TB_FLAG_SR_SAME) {
tcg_gen_mov_i64(dest, cpu_srH);
} else {
- tcg_gen_ld_i64(dest, cpu_env, offsetof(CPUHPPAState, sr[reg]));
+ tcg_gen_ld_i64(dest, tcg_env, offsetof(CPUHPPAState, sr[reg]));
}
#endif
}
static void gen_excp_1(int exception)
{
- gen_helper_excp(cpu_env, tcg_constant_i32(exception));
+ gen_helper_excp(tcg_env, tcg_constant_i32(exception));
}
static void gen_excp(DisasContext *ctx, int exception)
{
nullify_over(ctx);
tcg_gen_st_reg(tcg_constant_reg(ctx->insn),
- cpu_env, offsetof(CPUHPPAState, cr[CR_IIR]));
+ tcg_env, offsetof(CPUHPPAState, cr[CR_IIR]));
gen_excp(ctx, exc);
return nullify_end(ctx);
}
sv = do_add_sv(ctx, dest, in1, in2);
if (is_tsv) {
/* ??? Need to include overflow from shift. */
- gen_helper_tsv(cpu_env, sv);
+ gen_helper_tsv(tcg_env, sv);
}
}
if (is_tc) {
tmp = tcg_temp_new();
tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1);
- gen_helper_tcond(cpu_env, tmp);
+ gen_helper_tcond(tcg_env, tmp);
}
/* Write back the result. */
if (is_tsv || cond_need_sv(c)) {
sv = do_sub_sv(ctx, dest, in1, in2);
if (is_tsv) {
- gen_helper_tsv(cpu_env, sv);
+ gen_helper_tsv(tcg_env, sv);
}
}
if (is_tc) {
tmp = tcg_temp_new();
tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1);
- gen_helper_tcond(cpu_env, tmp);
+ gen_helper_tcond(tcg_env, tmp);
}
/* Write back the result. */
if (is_tc) {
TCGv_reg tmp = tcg_temp_new();
tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1);
- gen_helper_tcond(cpu_env, tmp);
+ gen_helper_tcond(tcg_env, tmp);
}
save_gpr(ctx, rt, dest);
tcg_gen_andi_reg(tmp, tmp, 030);
tcg_gen_trunc_reg_ptr(ptr, tmp);
- tcg_gen_add_ptr(ptr, ptr, cpu_env);
+ tcg_gen_add_ptr(ptr, ptr, tcg_env);
tcg_gen_ld_i64(spc, ptr, offsetof(CPUHPPAState, sr[4]));
return spc;
save_frw_i32(rt, tmp);
if (rt == 0) {
- gen_helper_loaded_fr0(cpu_env);
+ gen_helper_loaded_fr0(tcg_env);
}
return nullify_end(ctx);
save_frd(rt, tmp);
if (rt == 0) {
- gen_helper_loaded_fr0(cpu_env);
+ gen_helper_loaded_fr0(tcg_env);
}
return nullify_end(ctx);
nullify_over(ctx);
tmp = load_frw0_i32(ra);
- func(tmp, cpu_env, tmp);
+ func(tmp, tcg_env, tmp);
save_frw_i32(rt, tmp);
return nullify_end(ctx);
src = load_frd(ra);
dst = tcg_temp_new_i32();
- func(dst, cpu_env, src);
+ func(dst, tcg_env, src);
save_frw_i32(rt, dst);
return nullify_end(ctx);
nullify_over(ctx);
tmp = load_frd0(ra);
- func(tmp, cpu_env, tmp);
+ func(tmp, tcg_env, tmp);
save_frd(rt, tmp);
return nullify_end(ctx);
src = load_frw0_i32(ra);
dst = tcg_temp_new_i64();
- func(dst, cpu_env, src);
+ func(dst, tcg_env, src);
save_frd(rt, dst);
return nullify_end(ctx);
a = load_frw0_i32(ra);
b = load_frw0_i32(rb);
- func(a, cpu_env, a, b);
+ func(a, tcg_env, a, b);
save_frw_i32(rt, a);
return nullify_end(ctx);
a = load_frd0(ra);
b = load_frd0(rb);
- func(a, cpu_env, a, b);
+ func(a, tcg_env, a, b);
save_frd(rt, a);
return nullify_end(ctx);
break;
case 0xe0: /* SET_THREAD_POINTER */
- tcg_gen_st_reg(cpu_gr[26], cpu_env, offsetof(CPUHPPAState, cr[27]));
+ tcg_gen_st_reg(cpu_gr[26], tcg_env, offsetof(CPUHPPAState, cr[27]));
tcg_gen_ori_reg(cpu_iaoq_f, cpu_gr[31], 3);
tcg_gen_addi_reg(cpu_iaoq_b, cpu_iaoq_f, 4);
ctx->base.is_jmp = DISAS_IAQ_N_UPDATED;
}
tmp = get_temp(ctx);
- tcg_gen_ld_reg(tmp, cpu_env, offsetof(CPUHPPAState, cr[ctl]));
+ tcg_gen_ld_reg(tmp, tcg_env, offsetof(CPUHPPAState, cr[ctl]));
save_gpr(ctx, rt, tmp);
done:
tcg_gen_shli_i64(t64, t64, 32);
if (rs >= 4) {
- tcg_gen_st_i64(t64, cpu_env, offsetof(CPUHPPAState, sr[rs]));
+ tcg_gen_st_i64(t64, tcg_env, offsetof(CPUHPPAState, sr[rs]));
ctx->tb_flags &= ~TB_FLAG_SR_SAME;
} else {
tcg_gen_mov_i64(cpu_sr[rs], t64);
switch (ctl) {
case CR_IT:
- gen_helper_write_interval_timer(cpu_env, reg);
+ gen_helper_write_interval_timer(tcg_env, reg);
break;
case CR_EIRR:
- gen_helper_write_eirr(cpu_env, reg);
+ gen_helper_write_eirr(tcg_env, reg);
break;
case CR_EIEM:
- gen_helper_write_eiem(cpu_env, reg);
+ gen_helper_write_eiem(tcg_env, reg);
ctx->base.is_jmp = DISAS_IAQ_N_STALE_EXIT;
break;
/* FIXME: Respect PSW_Q bit */
/* The write advances the queue and stores to the back element. */
tmp = get_temp(ctx);
- tcg_gen_ld_reg(tmp, cpu_env,
+ tcg_gen_ld_reg(tmp, tcg_env,
offsetof(CPUHPPAState, cr_back[ctl - CR_IIASQ]));
- tcg_gen_st_reg(tmp, cpu_env, offsetof(CPUHPPAState, cr[ctl]));
- tcg_gen_st_reg(reg, cpu_env,
+ tcg_gen_st_reg(tmp, tcg_env, offsetof(CPUHPPAState, cr[ctl]));
+ tcg_gen_st_reg(reg, tcg_env,
offsetof(CPUHPPAState, cr_back[ctl - CR_IIASQ]));
break;
case CR_PID2:
case CR_PID3:
case CR_PID4:
- tcg_gen_st_reg(reg, cpu_env, offsetof(CPUHPPAState, cr[ctl]));
+ tcg_gen_st_reg(reg, tcg_env, offsetof(CPUHPPAState, cr[ctl]));
#ifndef CONFIG_USER_ONLY
- gen_helper_change_prot_id(cpu_env);
+ gen_helper_change_prot_id(tcg_env);
#endif
break;
default:
- tcg_gen_st_reg(reg, cpu_env, offsetof(CPUHPPAState, cr[ctl]));
+ tcg_gen_st_reg(reg, tcg_env, offsetof(CPUHPPAState, cr[ctl]));
break;
}
return nullify_end(ctx);
nullify_over(ctx);
tmp = get_temp(ctx);
- tcg_gen_ld_reg(tmp, cpu_env, offsetof(CPUHPPAState, psw));
+ tcg_gen_ld_reg(tmp, tcg_env, offsetof(CPUHPPAState, psw));
tcg_gen_andi_reg(tmp, tmp, ~a->i);
- gen_helper_swap_system_mask(tmp, cpu_env, tmp);
+ gen_helper_swap_system_mask(tmp, tcg_env, tmp);
save_gpr(ctx, a->t, tmp);
/* Exit the TB to recognize new interrupts, e.g. PSW_M. */
nullify_over(ctx);
tmp = get_temp(ctx);
- tcg_gen_ld_reg(tmp, cpu_env, offsetof(CPUHPPAState, psw));
+ tcg_gen_ld_reg(tmp, tcg_env, offsetof(CPUHPPAState, psw));
tcg_gen_ori_reg(tmp, tmp, a->i);
- gen_helper_swap_system_mask(tmp, cpu_env, tmp);
+ gen_helper_swap_system_mask(tmp, tcg_env, tmp);
save_gpr(ctx, a->t, tmp);
/* Exit the TB to recognize new interrupts, e.g. PSW_I. */
reg = load_gpr(ctx, a->r);
tmp = get_temp(ctx);
- gen_helper_swap_system_mask(tmp, cpu_env, reg);
+ gen_helper_swap_system_mask(tmp, tcg_env, reg);
/* Exit the TB to recognize new interrupts. */
ctx->base.is_jmp = DISAS_IAQ_N_STALE_EXIT;
nullify_over(ctx);
if (rfi_r) {
- gen_helper_rfi_r(cpu_env);
+ gen_helper_rfi_r(tcg_env);
} else {
- gen_helper_rfi(cpu_env);
+ gen_helper_rfi(tcg_env);
}
/* Exit the TB to recognize new interrupts. */
tcg_gen_exit_tb(NULL, 0);
CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
#ifndef CONFIG_USER_ONLY
nullify_over(ctx);
- gen_helper_halt(cpu_env);
+ gen_helper_halt(tcg_env);
ctx->base.is_jmp = DISAS_NORETURN;
return nullify_end(ctx);
#endif
CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
#ifndef CONFIG_USER_ONLY
nullify_over(ctx);
- gen_helper_reset(cpu_env);
+ gen_helper_reset(tcg_env);
ctx->base.is_jmp = DISAS_NORETURN;
return nullify_end(ctx);
#endif
CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
#ifndef CONFIG_USER_ONLY
nullify_over(ctx);
- gen_helper_getshadowregs(cpu_env);
+ gen_helper_getshadowregs(tcg_env);
return nullify_end(ctx);
#endif
}
}
want = tcg_constant_i32(a->write ? PAGE_WRITE : PAGE_READ);
- gen_helper_probe(dest, cpu_env, addr, level, want);
+ gen_helper_probe(dest, tcg_env, addr, level, want);
save_gpr(ctx, a->t, dest);
return nullify_end(ctx);
form_gva(ctx, &addr, &ofs, a->b, 0, 0, 0, a->sp, 0, false);
reg = load_gpr(ctx, a->r);
if (a->addr) {
- gen_helper_itlba(cpu_env, addr, reg);
+ gen_helper_itlba(tcg_env, addr, reg);
} else {
- gen_helper_itlbp(cpu_env, addr, reg);
+ gen_helper_itlbp(tcg_env, addr, reg);
}
/* Exit TB for TLB change if mmu is enabled. */
save_gpr(ctx, a->b, ofs);
}
if (a->local) {
- gen_helper_ptlbe(cpu_env);
+ gen_helper_ptlbe(tcg_env);
} else {
- gen_helper_ptlb(cpu_env, addr);
+ gen_helper_ptlb(tcg_env, addr);
}
/* Exit TB for TLB change if mmu is enabled. */
stl = tcg_temp_new_tl();
addr = tcg_temp_new_tl();
- tcg_gen_ld32u_i64(stl, cpu_env,
+ tcg_gen_ld32u_i64(stl, tcg_env,
a->data ? offsetof(CPUHPPAState, cr[CR_ISR])
: offsetof(CPUHPPAState, cr[CR_IIASQ]));
- tcg_gen_ld32u_i64(atl, cpu_env,
+ tcg_gen_ld32u_i64(atl, tcg_env,
a->data ? offsetof(CPUHPPAState, cr[CR_IOR])
: offsetof(CPUHPPAState, cr[CR_IIAOQ]));
tcg_gen_shli_i64(stl, stl, 32);
reg = load_gpr(ctx, a->r);
if (a->addr) {
- gen_helper_itlba(cpu_env, addr, reg);
+ gen_helper_itlba(tcg_env, addr, reg);
} else {
- gen_helper_itlbp(cpu_env, addr, reg);
+ gen_helper_itlbp(tcg_env, addr, reg);
}
/* Exit TB for TLB change if mmu is enabled. */
form_gva(ctx, &vaddr, &ofs, a->b, a->x, 0, 0, a->sp, a->m, false);
paddr = tcg_temp_new();
- gen_helper_lpa(paddr, cpu_env, vaddr);
+ gen_helper_lpa(paddr, tcg_env, vaddr);
/* Note that physical address result overrides base modification. */
if (a->m) {
nullify_set(ctx, 0);
/* Tell the qemu main loop to halt until this cpu has work. */
- tcg_gen_st_i32(tcg_constant_i32(1), cpu_env,
+ tcg_gen_st_i32(tcg_constant_i32(1), tcg_env,
offsetof(CPUState, halted) - offsetof(HPPACPU, env));
gen_excp_1(EXCP_HALTED);
ctx->base.is_jmp = DISAS_NORETURN;
val = load_gpr(ctx, a->r);
if (a->a) {
if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
- gen_helper_stby_e_parallel(cpu_env, addr, val);
+ gen_helper_stby_e_parallel(tcg_env, addr, val);
} else {
- gen_helper_stby_e(cpu_env, addr, val);
+ gen_helper_stby_e(tcg_env, addr, val);
}
} else {
if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
- gen_helper_stby_b_parallel(cpu_env, addr, val);
+ gen_helper_stby_b_parallel(tcg_env, addr, val);
} else {
- gen_helper_stby_b(cpu_env, addr, val);
+ gen_helper_stby_b(tcg_env, addr, val);
}
}
if (a->m) {
ty = tcg_constant_i32(a->y);
tc = tcg_constant_i32(a->c);
- gen_helper_fcmp_s(cpu_env, ta, tb, ty, tc);
+ gen_helper_fcmp_s(tcg_env, ta, tb, ty, tc);
return nullify_end(ctx);
}
ty = tcg_constant_i32(a->y);
tc = tcg_constant_i32(a->c);
- gen_helper_fcmp_d(cpu_env, ta, tb, ty, tc);
+ gen_helper_fcmp_d(tcg_env, ta, tb, ty, tc);
return nullify_end(ctx);
}
nullify_over(ctx);
t = get_temp(ctx);
- tcg_gen_ld32u_reg(t, cpu_env, offsetof(CPUHPPAState, fr0_shadow));
+ tcg_gen_ld32u_reg(t, tcg_env, offsetof(CPUHPPAState, fr0_shadow));
if (a->y == 1) {
int mask;
z = load_frw0_i32(a->ra3);
if (a->neg) {
- gen_helper_fmpynfadd_s(x, cpu_env, x, y, z);
+ gen_helper_fmpynfadd_s(x, tcg_env, x, y, z);
} else {
- gen_helper_fmpyfadd_s(x, cpu_env, x, y, z);
+ gen_helper_fmpyfadd_s(x, tcg_env, x, y, z);
}
save_frw_i32(a->t, x);
z = load_frd0(a->ra3);
if (a->neg) {
- gen_helper_fmpynfadd_d(x, cpu_env, x, y, z);
+ gen_helper_fmpynfadd_d(x, tcg_env, x, y, z);
} else {
- gen_helper_fmpyfadd_d(x, cpu_env, x, y, z);
+ gen_helper_fmpyfadd_d(x, tcg_env, x, y, z);
}
save_frd(a->t, x);
static bool trans_diag(DisasContext *ctx, arg_diag *a)
{
- nullify_over(ctx);
CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
#ifndef CONFIG_USER_ONLY
if (a->i == 0x100) {
/* emulate PDC BTLB, called by SeaBIOS-hppa */
- gen_helper_diag_btlb(cpu_env);
- } else
-#endif
- {
- qemu_log_mask(LOG_UNIMP, "DIAG opcode 0x%04x ignored\n", a->i);
+ nullify_over(ctx);
+ gen_helper_diag_btlb(tcg_env);
+ return nullify_end(ctx);
}
- return nullify_end(ctx);
+#endif
+ qemu_log_mask(LOG_UNIMP, "DIAG opcode 0x%04x ignored\n", a->i);
+ return true;
}
static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
}
if (decode.e.special == X86_SPECIAL_MMX &&
!(s->prefix & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))) {
- gen_helper_enter_mmx(cpu_env);
+ gen_helper_enter_mmx(tcg_env);
}
if (decode.op[0].has_ea || decode.op[1].has_ea || decode.op[2].has_ea) {
switch(ot) {
case MO_8:
gen_op_ld_v(s, MO_8, temp, s->A0);
- tcg_gen_st8_tl(temp, cpu_env, dest_ofs);
+ tcg_gen_st8_tl(temp, tcg_env, dest_ofs);
break;
case MO_16:
gen_op_ld_v(s, MO_16, temp, s->A0);
- tcg_gen_st16_tl(temp, cpu_env, dest_ofs);
+ tcg_gen_st16_tl(temp, tcg_env, dest_ofs);
break;
case MO_32:
gen_op_ld_v(s, MO_32, temp, s->A0);
- tcg_gen_st32_tl(temp, cpu_env, dest_ofs);
+ tcg_gen_st32_tl(temp, tcg_env, dest_ofs);
break;
case MO_64:
gen_ldq_env_A0(s, dest_ofs);
case X86_OP_SKIP:
return;
case X86_OP_SEG:
- tcg_gen_ld32u_tl(v, cpu_env,
+ tcg_gen_ld32u_tl(v, tcg_env,
offsetof(CPUX86State,segs[op->n].selector));
break;
case X86_OP_CR:
- tcg_gen_ld_tl(v, cpu_env, offsetof(CPUX86State, cr[op->n]));
+ tcg_gen_ld_tl(v, tcg_env, offsetof(CPUX86State, cr[op->n]));
break;
case X86_OP_DR:
- tcg_gen_ld_tl(v, cpu_env, offsetof(CPUX86State, dr[op->n]));
+ tcg_gen_ld_tl(v, tcg_env, offsetof(CPUX86State, dr[op->n]));
break;
case X86_OP_INT:
if (op->has_ea) {
op->v_ptr = tcg_temp_new_ptr();
/* The temporary points to the MMXReg or ZMMReg. */
- tcg_gen_addi_ptr(op->v_ptr, cpu_env, vector_reg_offset(op));
+ tcg_gen_addi_ptr(op->v_ptr, tcg_env, vector_reg_offset(op));
return op->v_ptr;
}
return;
}
- gen_helper_enter_mmx(cpu_env);
+ gen_helper_enter_mmx(tcg_env);
if (fn == FN_3DNOW_MOVE) {
- tcg_gen_ld_i64(s->tmp1_i64, cpu_env, decode->op[1].offset);
- tcg_gen_st_i64(s->tmp1_i64, cpu_env, decode->op[0].offset);
+ tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[1].offset);
+ tcg_gen_st_i64(s->tmp1_i64, tcg_env, decode->op[0].offset);
} else {
- fn(cpu_env, OP_PTR0, OP_PTR1);
+ fn(tcg_env, OP_PTR0, OP_PTR1);
}
}
gen_illegal_opcode(s);
return;
}
- fn(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2);
+ fn(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2);
} else {
SSEFunc_0_epp ps, pd, fn;
ps = s->vex_l ? ps_ymm : ps_xmm;
gen_illegal_opcode(s);
return;
}
- fn(cpu_env, OP_PTR0, OP_PTR2);
+ fn(tcg_env, OP_PTR0, OP_PTR2);
}
}
#define UNARY_FP_SSE(uname, lname) \
fn = s->prefix & PREFIX_DATA ? pd : ps;
}
if (fn) {
- fn(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2);
+ fn(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2);
} else {
gen_illegal_opcode(s);
}
SSEFunc_0_eppppii ymm = s->vex_w ? gen_helper_fma4pd_ymm : gen_helper_fma4ps_ymm; \
SSEFunc_0_eppppii fn = s->vex_l ? ymm : xmm; \
\
- fn(cpu_env, OP_PTR0, ptr0, ptr1, ptr2, \
+ fn(tcg_env, OP_PTR0, ptr0, ptr1, ptr2, \
tcg_constant_i32(even), \
tcg_constant_i32((even) ^ (odd))); \
}
{ \
SSEFunc_0_eppppi fn = s->vex_w ? gen_helper_fma4sd : gen_helper_fma4ss; \
\
- fn(cpu_env, OP_PTR0, ptr0, ptr1, ptr2, \
+ fn(tcg_env, OP_PTR0, ptr0, ptr1, ptr2, \
tcg_constant_i32(flags)); \
} \
if (!ss) {
goto illegal_op;
}
- ss(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2);
+ ss(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2);
} else {
SSEFunc_0_epp fn = s->vex_l ? ps_ymm : ps_xmm;
if (!fn) {
goto illegal_op;
}
- fn(cpu_env, OP_PTR0, OP_PTR2);
+ fn(tcg_env, OP_PTR0, OP_PTR2);
}
return;
ps = s->vex_l ? ps_ymm : ps_xmm;
pd = s->vex_l ? pd_ymm : pd_xmm;
fn = s->prefix & PREFIX_DATA ? pd : ps;
- fn(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2);
+ fn(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2);
}
#define HORIZONTAL_FP_SSE(uname, lname) \
static void gen_##uname(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) \
TCGv_ptr ptr3 = tcg_temp_new_ptr();
/* The format of the fourth input is Lx */
- tcg_gen_addi_ptr(ptr3, cpu_env, ZMM_OFFSET(op3));
- fn(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2, ptr3);
+ tcg_gen_addi_ptr(ptr3, tcg_env, ZMM_OFFSET(op3));
+ fn(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2, ptr3);
}
#define TERNARY_SSE(uname, uvname, lname) \
static void gen_##uvname(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) \
{
TCGv_i32 imm = tcg_constant8u_i32(decode->immediate);
if (!s->vex_l) {
- xmm(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2, imm);
+ xmm(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2, imm);
} else {
- ymm(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2, imm);
+ ymm(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2, imm);
}
}
return;
}
if (!(s->prefix & PREFIX_DATA)) {
- mmx(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2);
+ mmx(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2);
} else if (!s->vex_l) {
- xmm(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2);
+ xmm(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2);
} else {
- ymm(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2);
+ ymm(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2);
}
}
static void gen_##uname(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) \
{ \
if (!s->vex_l) { \
- gen_helper_##lname##_xmm(cpu_env, OP_PTR1, OP_PTR2); \
+ gen_helper_##lname##_xmm(tcg_env, OP_PTR1, OP_PTR2); \
} else { \
- gen_helper_##lname##_ymm(cpu_env, OP_PTR1, OP_PTR2); \
+ gen_helper_##lname##_ymm(tcg_env, OP_PTR1, OP_PTR2); \
} \
set_cc_op(s, CC_OP_EFLAGS); \
}
SSEFunc_0_epp xmm, SSEFunc_0_epp ymm)
{
if (!s->vex_l) {
- xmm(cpu_env, OP_PTR0, OP_PTR2);
+ xmm(tcg_env, OP_PTR0, OP_PTR2);
} else {
- ymm(cpu_env, OP_PTR0, OP_PTR2);
+ ymm(tcg_env, OP_PTR0, OP_PTR2);
}
}
{
TCGv_i32 imm = tcg_constant8u_i32(decode->immediate);
if (!s->vex_l) {
- xmm(cpu_env, OP_PTR0, OP_PTR1, imm);
+ xmm(tcg_env, OP_PTR0, OP_PTR1, imm);
} else {
- ymm(cpu_env, OP_PTR0, OP_PTR1, imm);
+ ymm(tcg_env, OP_PTR0, OP_PTR1, imm);
}
}
SSEFunc_0_eppp d = s->vex_l ? d_ymm : d_xmm;
SSEFunc_0_eppp q = s->vex_l ? q_ymm : q_xmm;
SSEFunc_0_eppp fn = s->vex_w ? q : d;
- fn(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2);
+ fn(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2);
}
/* VEX.W affects whether to operate on 32- or 64-bit elements. */
TCGv_ptr index = tcg_temp_new_ptr();
/* Pass third input as (index, base, scale) */
- tcg_gen_addi_ptr(index, cpu_env, ZMM_OFFSET(decode->mem.index));
- fn(cpu_env, OP_PTR0, OP_PTR1, index, s->A0, scale);
+ tcg_gen_addi_ptr(index, tcg_env, ZMM_OFFSET(decode->mem.index));
+ fn(tcg_env, OP_PTR0, OP_PTR1, index, s->A0, scale);
/*
* There are two output operands, so zero OP1's high 128 bits
static void gen_CVTPI2Px(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
- gen_helper_enter_mmx(cpu_env);
+ gen_helper_enter_mmx(tcg_env);
if (s->prefix & PREFIX_DATA) {
- gen_helper_cvtpi2pd(cpu_env, OP_PTR0, OP_PTR2);
+ gen_helper_cvtpi2pd(tcg_env, OP_PTR0, OP_PTR2);
} else {
- gen_helper_cvtpi2ps(cpu_env, OP_PTR0, OP_PTR2);
+ gen_helper_cvtpi2ps(tcg_env, OP_PTR0, OP_PTR2);
}
}
static void gen_CVTPx2PI(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
- gen_helper_enter_mmx(cpu_env);
+ gen_helper_enter_mmx(tcg_env);
if (s->prefix & PREFIX_DATA) {
- gen_helper_cvtpd2pi(cpu_env, OP_PTR0, OP_PTR2);
+ gen_helper_cvtpd2pi(tcg_env, OP_PTR0, OP_PTR2);
} else {
- gen_helper_cvtps2pi(cpu_env, OP_PTR0, OP_PTR2);
+ gen_helper_cvtps2pi(tcg_env, OP_PTR0, OP_PTR2);
}
}
static void gen_CVTTPx2PI(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
- gen_helper_enter_mmx(cpu_env);
+ gen_helper_enter_mmx(tcg_env);
if (s->prefix & PREFIX_DATA) {
- gen_helper_cvttpd2pi(cpu_env, OP_PTR0, OP_PTR2);
+ gen_helper_cvttpd2pi(tcg_env, OP_PTR0, OP_PTR2);
} else {
- gen_helper_cvttps2pi(cpu_env, OP_PTR0, OP_PTR2);
+ gen_helper_cvttps2pi(tcg_env, OP_PTR0, OP_PTR2);
}
}
static void gen_EMMS(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
- gen_helper_emms(cpu_env);
+ gen_helper_emms(tcg_env);
}
static void gen_EXTRQ_i(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
TCGv_i32 length = tcg_constant_i32(decode->immediate & 63);
TCGv_i32 index = tcg_constant_i32((decode->immediate >> 8) & 63);
- gen_helper_extrq_i(cpu_env, OP_PTR0, index, length);
+ gen_helper_extrq_i(tcg_env, OP_PTR0, index, length);
}
static void gen_EXTRQ_r(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
- gen_helper_extrq_r(cpu_env, OP_PTR0, OP_PTR2);
+ gen_helper_extrq_r(tcg_env, OP_PTR0, OP_PTR2);
}
static void gen_INSERTQ_i(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
TCGv_i32 length = tcg_constant_i32(decode->immediate & 63);
TCGv_i32 index = tcg_constant_i32((decode->immediate >> 8) & 63);
- gen_helper_insertq_i(cpu_env, OP_PTR0, OP_PTR1, index, length);
+ gen_helper_insertq_i(tcg_env, OP_PTR0, OP_PTR1, index, length);
}
static void gen_INSERTQ_r(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
- gen_helper_insertq_r(cpu_env, OP_PTR0, OP_PTR2);
+ gen_helper_insertq_r(tcg_env, OP_PTR0, OP_PTR2);
}
static void gen_LDMXCSR(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
return;
}
tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T1);
- gen_helper_ldmxcsr(cpu_env, s->tmp2_i32);
+ gen_helper_ldmxcsr(tcg_env, s->tmp2_i32);
}
static void gen_MASKMOV(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
gen_add_A0_ds_seg(s);
if (s->prefix & PREFIX_DATA) {
- gen_helper_maskmov_xmm(cpu_env, OP_PTR1, OP_PTR2, s->A0);
+ gen_helper_maskmov_xmm(tcg_env, OP_PTR1, OP_PTR2, s->A0);
} else {
- gen_helper_maskmov_mmx(cpu_env, OP_PTR1, OP_PTR2, s->A0);
+ gen_helper_maskmov_mmx(tcg_env, OP_PTR1, OP_PTR2, s->A0);
}
}
switch (ot) {
case MO_32:
#ifdef TARGET_X86_64
- tcg_gen_ld32u_tl(s->T0, cpu_env, decode->op[2].offset);
+ tcg_gen_ld32u_tl(s->T0, tcg_env, decode->op[2].offset);
break;
case MO_64:
#endif
- tcg_gen_ld_tl(s->T0, cpu_env, decode->op[2].offset);
+ tcg_gen_ld_tl(s->T0, tcg_env, decode->op[2].offset);
break;
default:
abort();
switch (ot) {
case MO_32:
#ifdef TARGET_X86_64
- tcg_gen_st32_tl(s->T1, cpu_env, lo_ofs);
+ tcg_gen_st32_tl(s->T1, tcg_env, lo_ofs);
break;
case MO_64:
#endif
- tcg_gen_st_tl(s->T1, cpu_env, lo_ofs);
+ tcg_gen_st_tl(s->T1, tcg_env, lo_ofs);
break;
default:
g_assert_not_reached();
ps = s->vex_l ? gen_helper_movmskps_ymm : gen_helper_movmskps_xmm;
pd = s->vex_l ? gen_helper_movmskpd_ymm : gen_helper_movmskpd_xmm;
fn = s->prefix & PREFIX_DATA ? pd : ps;
- fn(s->tmp2_i32, cpu_env, OP_PTR2);
+ fn(s->tmp2_i32, tcg_env, OP_PTR2);
tcg_gen_extu_i32_tl(s->T0, s->tmp2_i32);
}
int vec_len = vector_len(s, decode);
int lo_ofs = vector_elem_offset(&decode->op[0], MO_64, 0);
- tcg_gen_ld_i64(s->tmp1_i64, cpu_env, decode->op[2].offset);
+ tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[2].offset);
if (decode->op[0].has_ea) {
tcg_gen_qemu_st_i64(s->tmp1_i64, s->A0, s->mem_index, MO_LEUQ);
} else {
* it disqualifies using oprsz < maxsz to emulate VEX128.
*/
tcg_gen_gvec_dup_imm(MO_64, decode->op[0].offset, vec_len, vec_len, 0);
- tcg_gen_st_i64(s->tmp1_i64, cpu_env, lo_ofs);
+ tcg_gen_st_i64(s->tmp1_i64, tcg_env, lo_ofs);
}
}
static void gen_MOVq_dq(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
- gen_helper_enter_mmx(cpu_env);
+ gen_helper_enter_mmx(tcg_env);
/* Otherwise the same as any other movq. */
return gen_MOVQ(s, env, decode);
}
{
TCGv_i32 imm = tcg_constant8u_i32(decode->immediate);
if (!(s->prefix & PREFIX_DATA)) {
- gen_helper_palignr_mmx(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2, imm);
+ gen_helper_palignr_mmx(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2, imm);
} else if (!s->vex_l) {
- gen_helper_palignr_xmm(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2, imm);
+ gen_helper_palignr_xmm(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2, imm);
} else {
- gen_helper_palignr_ymm(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2, imm);
+ gen_helper_palignr_ymm(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2, imm);
}
}
static void gen_PCMPESTRI(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
TCGv_i32 imm = tcg_constant8u_i32(decode->immediate);
- gen_helper_pcmpestri_xmm(cpu_env, OP_PTR1, OP_PTR2, imm);
+ gen_helper_pcmpestri_xmm(tcg_env, OP_PTR1, OP_PTR2, imm);
set_cc_op(s, CC_OP_EFLAGS);
}
static void gen_PCMPESTRM(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
TCGv_i32 imm = tcg_constant8u_i32(decode->immediate);
- gen_helper_pcmpestrm_xmm(cpu_env, OP_PTR1, OP_PTR2, imm);
+ gen_helper_pcmpestrm_xmm(tcg_env, OP_PTR1, OP_PTR2, imm);
set_cc_op(s, CC_OP_EFLAGS);
if ((s->prefix & PREFIX_VEX) && !s->vex_l) {
tcg_gen_gvec_dup_imm(MO_64, offsetof(CPUX86State, xmm_regs[0].ZMM_X(1)),
static void gen_PCMPISTRI(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
TCGv_i32 imm = tcg_constant8u_i32(decode->immediate);
- gen_helper_pcmpistri_xmm(cpu_env, OP_PTR1, OP_PTR2, imm);
+ gen_helper_pcmpistri_xmm(tcg_env, OP_PTR1, OP_PTR2, imm);
set_cc_op(s, CC_OP_EFLAGS);
}
static void gen_PCMPISTRM(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
TCGv_i32 imm = tcg_constant8u_i32(decode->immediate);
- gen_helper_pcmpistrm_xmm(cpu_env, OP_PTR1, OP_PTR2, imm);
+ gen_helper_pcmpistrm_xmm(tcg_env, OP_PTR1, OP_PTR2, imm);
set_cc_op(s, CC_OP_EFLAGS);
if ((s->prefix & PREFIX_VEX) && !s->vex_l) {
tcg_gen_gvec_dup_imm(MO_64, offsetof(CPUX86State, xmm_regs[0].ZMM_X(1)),
switch (ot) {
case MO_8:
- tcg_gen_ld8u_tl(s->T0, cpu_env, vector_elem_offset(&decode->op[1], ot, val));
+ tcg_gen_ld8u_tl(s->T0, tcg_env, vector_elem_offset(&decode->op[1], ot, val));
break;
case MO_16:
- tcg_gen_ld16u_tl(s->T0, cpu_env, vector_elem_offset(&decode->op[1], ot, val));
+ tcg_gen_ld16u_tl(s->T0, tcg_env, vector_elem_offset(&decode->op[1], ot, val));
break;
case MO_32:
#ifdef TARGET_X86_64
- tcg_gen_ld32u_tl(s->T0, cpu_env, vector_elem_offset(&decode->op[1], ot, val));
+ tcg_gen_ld32u_tl(s->T0, tcg_env, vector_elem_offset(&decode->op[1], ot, val));
break;
case MO_64:
#endif
- tcg_gen_ld_tl(s->T0, cpu_env, vector_elem_offset(&decode->op[1], ot, val));
+ tcg_gen_ld_tl(s->T0, tcg_env, vector_elem_offset(&decode->op[1], ot, val));
break;
default:
abort();
switch (ot) {
case MO_8:
- tcg_gen_st8_tl(s->T1, cpu_env, vector_elem_offset(&decode->op[0], ot, val));
+ tcg_gen_st8_tl(s->T1, tcg_env, vector_elem_offset(&decode->op[0], ot, val));
break;
case MO_16:
- tcg_gen_st16_tl(s->T1, cpu_env, vector_elem_offset(&decode->op[0], ot, val));
+ tcg_gen_st16_tl(s->T1, tcg_env, vector_elem_offset(&decode->op[0], ot, val));
break;
case MO_32:
#ifdef TARGET_X86_64
- tcg_gen_st32_tl(s->T1, cpu_env, vector_elem_offset(&decode->op[0], ot, val));
+ tcg_gen_st32_tl(s->T1, tcg_env, vector_elem_offset(&decode->op[0], ot, val));
break;
case MO_64:
#endif
- tcg_gen_st_tl(s->T1, cpu_env, vector_elem_offset(&decode->op[0], ot, val));
+ tcg_gen_st_tl(s->T1, tcg_env, vector_elem_offset(&decode->op[0], ot, val));
break;
default:
abort();
tcg_gen_gvec_2(offsetof(CPUX86State, xmm_t0) + xmm_offset(ot), decode->op[2].offset,
vec_len, vec_len, &g);
- tcg_gen_ld8u_tl(s->T0, cpu_env, offsetof(CPUX86State, xmm_t0.ZMM_B(vec_len - 1)));
+ tcg_gen_ld8u_tl(s->T0, tcg_env, offsetof(CPUX86State, xmm_t0.ZMM_B(vec_len - 1)));
while (vec_len > 8) {
vec_len -= 8;
if (TCG_TARGET_HAS_extract2_tl) {
* loading the whole word, the shift left is avoided.
*/
#ifdef TARGET_X86_64
- tcg_gen_ld_tl(t, cpu_env, offsetof(CPUX86State, xmm_t0.ZMM_Q((vec_len - 1) / 8)));
+ tcg_gen_ld_tl(t, tcg_env, offsetof(CPUX86State, xmm_t0.ZMM_Q((vec_len - 1) / 8)));
#else
- tcg_gen_ld_tl(t, cpu_env, offsetof(CPUX86State, xmm_t0.ZMM_L((vec_len - 1) / 4)));
+ tcg_gen_ld_tl(t, tcg_env, offsetof(CPUX86State, xmm_t0.ZMM_L((vec_len - 1) / 4)));
#endif
tcg_gen_extract2_tl(s->T0, t, s->T0, TARGET_LONG_BITS - 8);
* those bits are known to be zero after ld8u, this becomes a shift+or
* if deposit is not available.
*/
- tcg_gen_ld8u_tl(t, cpu_env, offsetof(CPUX86State, xmm_t0.ZMM_B(vec_len - 1)));
+ tcg_gen_ld8u_tl(t, tcg_env, offsetof(CPUX86State, xmm_t0.ZMM_B(vec_len - 1)));
tcg_gen_deposit_tl(s->T0, t, s->T0, 8, TARGET_LONG_BITS - 8);
}
}
tcg_gen_gvec_dup_imm(MO_64, offsetof(CPUX86State, xmm_t0) + xmm_offset(ot),
vec_len, vec_len, 0);
- tcg_gen_addi_ptr(ptr, cpu_env, offsetof(CPUX86State, xmm_t0));
- tcg_gen_st_i32(imm_v, cpu_env, offsetof(CPUX86State, xmm_t0.ZMM_L(0)));
+ tcg_gen_addi_ptr(ptr, tcg_env, offsetof(CPUX86State, xmm_t0));
+ tcg_gen_st_i32(imm_v, tcg_env, offsetof(CPUX86State, xmm_t0.ZMM_L(0)));
return ptr;
}
TCGv_ptr imm_vec = make_imm8u_xmm_vec(decode->immediate, vec_len);
if (s->vex_l) {
- gen_helper_psrldq_ymm(cpu_env, OP_PTR0, OP_PTR1, imm_vec);
+ gen_helper_psrldq_ymm(tcg_env, OP_PTR0, OP_PTR1, imm_vec);
} else {
- gen_helper_psrldq_xmm(cpu_env, OP_PTR0, OP_PTR1, imm_vec);
+ gen_helper_psrldq_xmm(tcg_env, OP_PTR0, OP_PTR1, imm_vec);
}
}
TCGv_ptr imm_vec = make_imm8u_xmm_vec(decode->immediate, vec_len);
if (s->vex_l) {
- gen_helper_pslldq_ymm(cpu_env, OP_PTR0, OP_PTR1, imm_vec);
+ gen_helper_pslldq_ymm(tcg_env, OP_PTR0, OP_PTR1, imm_vec);
} else {
- gen_helper_pslldq_xmm(cpu_env, OP_PTR0, OP_PTR1, imm_vec);
+ gen_helper_pslldq_xmm(tcg_env, OP_PTR0, OP_PTR1, imm_vec);
}
}
{
TCGv_i32 imm = tcg_constant8u_i32(decode->immediate);
assert(!s->vex_l);
- gen_helper_aeskeygenassist_xmm(cpu_env, OP_PTR0, OP_PTR1, imm);
+ gen_helper_aeskeygenassist_xmm(tcg_env, OP_PTR0, OP_PTR1, imm);
}
static void gen_STMXCSR(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
gen_illegal_opcode(s);
return;
}
- gen_helper_update_mxcsr(cpu_env);
- tcg_gen_ld32u_tl(s->T0, cpu_env, offsetof(CPUX86State, mxcsr));
+ gen_helper_update_mxcsr(tcg_env);
+ tcg_gen_ld32u_tl(s->T0, tcg_env, offsetof(CPUX86State, mxcsr));
}
static void gen_VAESIMC(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
assert(!s->vex_l);
- gen_helper_aesimc_xmm(cpu_env, OP_PTR0, OP_PTR2);
+ gen_helper_aesimc_xmm(tcg_env, OP_PTR0, OP_PTR2);
}
/*
s->prefix & PREFIX_REPNZ ? 3 /* sd */ :
!!(s->prefix & PREFIX_DATA) /* pd */ + (s->vex_l << 2);
- gen_helper_cmp_funcs[index][b](cpu_env, OP_PTR0, OP_PTR1, OP_PTR2);
+ gen_helper_cmp_funcs[index][b](tcg_env, OP_PTR0, OP_PTR1, OP_PTR2);
}
static void gen_VCOMI(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
SSEFunc_0_epp fn;
fn = s->prefix & PREFIX_DATA ? gen_helper_comisd : gen_helper_comiss;
- fn(cpu_env, OP_PTR1, OP_PTR2);
+ fn(tcg_env, OP_PTR1, OP_PTR2);
set_cc_op(s, CC_OP_EFLAGS);
}
static void gen_VCVTPD2PS(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
if (s->vex_l) {
- gen_helper_cvtpd2ps_ymm(cpu_env, OP_PTR0, OP_PTR2);
+ gen_helper_cvtpd2ps_ymm(tcg_env, OP_PTR0, OP_PTR2);
} else {
- gen_helper_cvtpd2ps_xmm(cpu_env, OP_PTR0, OP_PTR2);
+ gen_helper_cvtpd2ps_xmm(tcg_env, OP_PTR0, OP_PTR2);
}
}
static void gen_VCVTPS2PD(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
if (s->vex_l) {
- gen_helper_cvtps2pd_ymm(cpu_env, OP_PTR0, OP_PTR2);
+ gen_helper_cvtps2pd_ymm(tcg_env, OP_PTR0, OP_PTR2);
} else {
- gen_helper_cvtps2pd_xmm(cpu_env, OP_PTR0, OP_PTR2);
+ gen_helper_cvtps2pd_xmm(tcg_env, OP_PTR0, OP_PTR2);
}
}
static void gen_VCVTSD2SS(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
- gen_helper_cvtsd2ss(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2);
+ gen_helper_cvtsd2ss(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2);
}
static void gen_VCVTSS2SD(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
- gen_helper_cvtss2sd(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2);
+ gen_helper_cvtss2sd(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2);
}
static void gen_VCVTSI2Sx(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
MemOp ot = decode->op[2].ot;
if (ot == MO_64) {
if (s->prefix & PREFIX_REPNZ) {
- gen_helper_cvtsq2sd(cpu_env, OP_PTR0, s->T1);
+ gen_helper_cvtsq2sd(tcg_env, OP_PTR0, s->T1);
} else {
- gen_helper_cvtsq2ss(cpu_env, OP_PTR0, s->T1);
+ gen_helper_cvtsq2ss(tcg_env, OP_PTR0, s->T1);
}
return;
}
#endif
if (s->prefix & PREFIX_REPNZ) {
- gen_helper_cvtsi2sd(cpu_env, OP_PTR0, in);
+ gen_helper_cvtsi2sd(tcg_env, OP_PTR0, in);
} else {
- gen_helper_cvtsi2ss(cpu_env, OP_PTR0, in);
+ gen_helper_cvtsi2ss(tcg_env, OP_PTR0, in);
}
}
MemOp ot = decode->op[0].ot;
if (ot == MO_64) {
if (s->prefix & PREFIX_REPNZ) {
- sd2sq(s->T0, cpu_env, OP_PTR2);
+ sd2sq(s->T0, tcg_env, OP_PTR2);
} else {
- ss2sq(s->T0, cpu_env, OP_PTR2);
+ ss2sq(s->T0, tcg_env, OP_PTR2);
}
return;
}
out = s->T0;
#endif
if (s->prefix & PREFIX_REPNZ) {
- sd2si(out, cpu_env, OP_PTR2);
+ sd2si(out, tcg_env, OP_PTR2);
} else {
- ss2si(out, cpu_env, OP_PTR2);
+ ss2si(out, tcg_env, OP_PTR2);
}
#ifdef TARGET_X86_64
tcg_gen_extu_i32_tl(s->T0, out);
}
if (new_mask != (val & 15)) {
- tcg_gen_st_i32(s->tmp2_i32, cpu_env,
+ tcg_gen_st_i32(s->tmp2_i32, tcg_env,
vector_elem_offset(&decode->op[0], MO_32, dest_word));
}
int i;
for (i = 0; i < 4; i++) {
if ((val >> i) & 1) {
- tcg_gen_st_i32(zero, cpu_env,
+ tcg_gen_st_i32(zero, tcg_env,
vector_elem_offset(&decode->op[0], MO_32, i));
}
}
static void gen_VINSERTPS_r(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
int val = decode->immediate;
- tcg_gen_ld_i32(s->tmp2_i32, cpu_env,
+ tcg_gen_ld_i32(s->tmp2_i32, tcg_env,
vector_elem_offset(&decode->op[2], MO_32, (val >> 6) & 3));
gen_vinsertps(s, env, decode);
}
SSEFunc_0_eppt xmm, SSEFunc_0_eppt ymm)
{
if (!s->vex_l) {
- xmm(cpu_env, OP_PTR2, OP_PTR1, s->A0);
+ xmm(tcg_env, OP_PTR2, OP_PTR1, s->A0);
} else {
- ymm(cpu_env, OP_PTR2, OP_PTR1, s->A0);
+ ymm(tcg_env, OP_PTR2, OP_PTR1, s->A0);
}
}
{
gen_ldq_env_A0(s, decode->op[0].offset + offsetof(XMMReg, XMM_Q(1)));
if (decode->op[0].offset != decode->op[1].offset) {
- tcg_gen_ld_i64(s->tmp1_i64, cpu_env, decode->op[1].offset + offsetof(XMMReg, XMM_Q(0)));
- tcg_gen_st_i64(s->tmp1_i64, cpu_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(0)));
+ tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[1].offset + offsetof(XMMReg, XMM_Q(0)));
+ tcg_gen_st_i64(s->tmp1_i64, tcg_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(0)));
}
}
static void gen_VMOVHPx(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
if (decode->op[0].offset != decode->op[2].offset) {
- tcg_gen_ld_i64(s->tmp1_i64, cpu_env, decode->op[2].offset + offsetof(XMMReg, XMM_Q(1)));
- tcg_gen_st_i64(s->tmp1_i64, cpu_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(1)));
+ tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[2].offset + offsetof(XMMReg, XMM_Q(1)));
+ tcg_gen_st_i64(s->tmp1_i64, tcg_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(1)));
}
if (decode->op[0].offset != decode->op[1].offset) {
- tcg_gen_ld_i64(s->tmp1_i64, cpu_env, decode->op[1].offset + offsetof(XMMReg, XMM_Q(0)));
- tcg_gen_st_i64(s->tmp1_i64, cpu_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(0)));
+ tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[1].offset + offsetof(XMMReg, XMM_Q(0)));
+ tcg_gen_st_i64(s->tmp1_i64, tcg_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(0)));
}
}
static void gen_VMOVHLPS(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
- tcg_gen_ld_i64(s->tmp1_i64, cpu_env, decode->op[2].offset + offsetof(XMMReg, XMM_Q(1)));
- tcg_gen_st_i64(s->tmp1_i64, cpu_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(0)));
+ tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[2].offset + offsetof(XMMReg, XMM_Q(1)));
+ tcg_gen_st_i64(s->tmp1_i64, tcg_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(0)));
if (decode->op[0].offset != decode->op[1].offset) {
- tcg_gen_ld_i64(s->tmp1_i64, cpu_env, decode->op[1].offset + offsetof(XMMReg, XMM_Q(1)));
- tcg_gen_st_i64(s->tmp1_i64, cpu_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(1)));
+ tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[1].offset + offsetof(XMMReg, XMM_Q(1)));
+ tcg_gen_st_i64(s->tmp1_i64, tcg_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(1)));
}
}
static void gen_VMOVLHPS(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
- tcg_gen_ld_i64(s->tmp1_i64, cpu_env, decode->op[2].offset);
- tcg_gen_st_i64(s->tmp1_i64, cpu_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(1)));
+ tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[2].offset);
+ tcg_gen_st_i64(s->tmp1_i64, tcg_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(1)));
if (decode->op[0].offset != decode->op[1].offset) {
- tcg_gen_ld_i64(s->tmp1_i64, cpu_env, decode->op[1].offset + offsetof(XMMReg, XMM_Q(0)));
- tcg_gen_st_i64(s->tmp1_i64, cpu_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(0)));
+ tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[1].offset + offsetof(XMMReg, XMM_Q(0)));
+ tcg_gen_st_i64(s->tmp1_i64, tcg_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(0)));
}
}
{
int vec_len = vector_len(s, decode);
- tcg_gen_ld_i64(s->tmp1_i64, cpu_env, decode->op[2].offset + offsetof(XMMReg, XMM_Q(0)));
+ tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[2].offset + offsetof(XMMReg, XMM_Q(0)));
tcg_gen_gvec_mov(MO_64, decode->op[0].offset, decode->op[1].offset, vec_len, vec_len);
- tcg_gen_st_i64(s->tmp1_i64, cpu_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(0)));
+ tcg_gen_st_i64(s->tmp1_i64, tcg_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(0)));
}
static void gen_VMOVLPx_ld(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
static void gen_VPHMINPOSUW(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
assert(!s->vex_l);
- gen_helper_phminposuw_xmm(cpu_env, OP_PTR0, OP_PTR2);
+ gen_helper_phminposuw_xmm(tcg_env, OP_PTR0, OP_PTR2);
}
static void gen_VROUNDSD(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
TCGv_i32 imm = tcg_constant8u_i32(decode->immediate);
assert(!s->vex_l);
- gen_helper_roundsd_xmm(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2, imm);
+ gen_helper_roundsd_xmm(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2, imm);
}
static void gen_VROUNDSS(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
TCGv_i32 imm = tcg_constant8u_i32(decode->immediate);
assert(!s->vex_l);
- gen_helper_roundss_xmm(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2, imm);
+ gen_helper_roundss_xmm(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2, imm);
}
static void gen_VSHUF(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
SSEFunc_0_epp fn;
fn = s->prefix & PREFIX_DATA ? gen_helper_ucomisd : gen_helper_ucomiss;
- fn(cpu_env, OP_PTR1, OP_PTR2);
+ fn(tcg_env, OP_PTR1, OP_PTR2);
set_cc_op(s, CC_OP_EFLAGS);
}
{
TCGv_ptr ptr = tcg_temp_new_ptr();
- tcg_gen_addi_ptr(ptr, cpu_env, offsetof(CPUX86State, xmm_regs));
+ tcg_gen_addi_ptr(ptr, tcg_env, offsetof(CPUX86State, xmm_regs));
gen_helper_memset(ptr, ptr, tcg_constant_i32(0),
tcg_constant_ptr(CPU_NB_REGS * sizeof(ZMMReg)));
}
static inline void gen_op_movl_T0_Dshift(DisasContext *s, MemOp ot)
{
- tcg_gen_ld32s_tl(s->T0, cpu_env, offsetof(CPUX86State, df));
+ tcg_gen_ld32s_tl(s->T0, tcg_env, offsetof(CPUX86State, df));
tcg_gen_shli_tl(s->T0, s->T0, ot);
};
{
switch (ot) {
case MO_8:
- gen_helper_inb(v, cpu_env, n);
+ gen_helper_inb(v, tcg_env, n);
break;
case MO_16:
- gen_helper_inw(v, cpu_env, n);
+ gen_helper_inw(v, tcg_env, n);
break;
case MO_32:
- gen_helper_inl(v, cpu_env, n);
+ gen_helper_inl(v, tcg_env, n);
break;
default:
g_assert_not_reached();
{
switch (ot) {
case MO_8:
- gen_helper_outb(cpu_env, v, n);
+ gen_helper_outb(tcg_env, v, n);
break;
case MO_16:
- gen_helper_outw(cpu_env, v, n);
+ gen_helper_outw(tcg_env, v, n);
break;
case MO_32:
- gen_helper_outl(cpu_env, v, n);
+ gen_helper_outl(tcg_env, v, n);
break;
default:
g_assert_not_reached();
return false;
#else
if (PE(s) && (CPL(s) > IOPL(s) || VM86(s))) {
- gen_helper_check_io(cpu_env, port, tcg_constant_i32(1 << ot));
+ gen_helper_check_io(tcg_env, port, tcg_constant_i32(1 << ot));
}
if (GUEST(s)) {
gen_update_cc_op(s);
svm_flags |= SVM_IOIO_REP_MASK;
}
svm_flags |= 1 << (SVM_IOIO_SIZE_SHIFT + ot);
- gen_helper_svm_check_io(cpu_env, port,
+ gen_helper_svm_check_io(tcg_env, port,
tcg_constant_i32(svm_flags),
cur_insn_len_i32(s));
}
#else
TCGv_i32 t_size = tcg_constant_i32(1 << ot);
TCGv t_next = eip_next_tl(s);
- gen_helper_bpt_io(cpu_env, t_port, t_size, t_next);
+ gen_helper_bpt_io(tcg_env, t_port, t_size, t_next);
#endif /* CONFIG_USER_ONLY */
}
}
{
switch (op) {
case 0:
- gen_helper_fadd_ST0_FT0(cpu_env);
+ gen_helper_fadd_ST0_FT0(tcg_env);
break;
case 1:
- gen_helper_fmul_ST0_FT0(cpu_env);
+ gen_helper_fmul_ST0_FT0(tcg_env);
break;
case 2:
- gen_helper_fcom_ST0_FT0(cpu_env);
+ gen_helper_fcom_ST0_FT0(tcg_env);
break;
case 3:
- gen_helper_fcom_ST0_FT0(cpu_env);
+ gen_helper_fcom_ST0_FT0(tcg_env);
break;
case 4:
- gen_helper_fsub_ST0_FT0(cpu_env);
+ gen_helper_fsub_ST0_FT0(tcg_env);
break;
case 5:
- gen_helper_fsubr_ST0_FT0(cpu_env);
+ gen_helper_fsubr_ST0_FT0(tcg_env);
break;
case 6:
- gen_helper_fdiv_ST0_FT0(cpu_env);
+ gen_helper_fdiv_ST0_FT0(tcg_env);
break;
case 7:
- gen_helper_fdivr_ST0_FT0(cpu_env);
+ gen_helper_fdivr_ST0_FT0(tcg_env);
break;
}
}
TCGv_i32 tmp = tcg_constant_i32(opreg);
switch (op) {
case 0:
- gen_helper_fadd_STN_ST0(cpu_env, tmp);
+ gen_helper_fadd_STN_ST0(tcg_env, tmp);
break;
case 1:
- gen_helper_fmul_STN_ST0(cpu_env, tmp);
+ gen_helper_fmul_STN_ST0(tcg_env, tmp);
break;
case 4:
- gen_helper_fsubr_STN_ST0(cpu_env, tmp);
+ gen_helper_fsubr_STN_ST0(tcg_env, tmp);
break;
case 5:
- gen_helper_fsub_STN_ST0(cpu_env, tmp);
+ gen_helper_fsub_STN_ST0(tcg_env, tmp);
break;
case 6:
- gen_helper_fdivr_STN_ST0(cpu_env, tmp);
+ gen_helper_fdivr_STN_ST0(tcg_env, tmp);
break;
case 7:
- gen_helper_fdiv_STN_ST0(cpu_env, tmp);
+ gen_helper_fdiv_STN_ST0(tcg_env, tmp);
break;
}
}
{
gen_update_cc_op(s);
gen_update_eip_cur(s);
- gen_helper_raise_exception(cpu_env, tcg_constant_i32(trapno));
+ gen_helper_raise_exception(tcg_env, tcg_constant_i32(trapno));
s->base.is_jmp = DISAS_NORETURN;
}
if (is_right) {
switch (ot) {
case MO_8:
- gen_helper_rcrb(s->T0, cpu_env, s->T0, s->T1);
+ gen_helper_rcrb(s->T0, tcg_env, s->T0, s->T1);
break;
case MO_16:
- gen_helper_rcrw(s->T0, cpu_env, s->T0, s->T1);
+ gen_helper_rcrw(s->T0, tcg_env, s->T0, s->T1);
break;
case MO_32:
- gen_helper_rcrl(s->T0, cpu_env, s->T0, s->T1);
+ gen_helper_rcrl(s->T0, tcg_env, s->T0, s->T1);
break;
#ifdef TARGET_X86_64
case MO_64:
- gen_helper_rcrq(s->T0, cpu_env, s->T0, s->T1);
+ gen_helper_rcrq(s->T0, tcg_env, s->T0, s->T1);
break;
#endif
default:
} else {
switch (ot) {
case MO_8:
- gen_helper_rclb(s->T0, cpu_env, s->T0, s->T1);
+ gen_helper_rclb(s->T0, tcg_env, s->T0, s->T1);
break;
case MO_16:
- gen_helper_rclw(s->T0, cpu_env, s->T0, s->T1);
+ gen_helper_rclw(s->T0, tcg_env, s->T0, s->T1);
break;
case MO_32:
- gen_helper_rcll(s->T0, cpu_env, s->T0, s->T1);
+ gen_helper_rcll(s->T0, tcg_env, s->T0, s->T1);
break;
#ifdef TARGET_X86_64
case MO_64:
- gen_helper_rclq(s->T0, cpu_env, s->T0, s->T1);
+ gen_helper_rclq(s->T0, tcg_env, s->T0, s->T1);
break;
#endif
default:
}
tcg_gen_setcond_i64(cond, s->tmp1_i64, s->tmp1_i64, bndv);
tcg_gen_extrl_i64_i32(s->tmp2_i32, s->tmp1_i64);
- gen_helper_bndck(cpu_env, s->tmp2_i32);
+ gen_helper_bndck(tcg_env, s->tmp2_i32);
}
/* used for LEA and MOV AX, mem */
static inline void gen_op_movl_T0_seg(DisasContext *s, X86Seg seg_reg)
{
- tcg_gen_ld32u_tl(s->T0, cpu_env,
+ tcg_gen_ld32u_tl(s->T0, tcg_env,
offsetof(CPUX86State,segs[seg_reg].selector));
}
static inline void gen_op_movl_seg_T0_vm(DisasContext *s, X86Seg seg_reg)
{
tcg_gen_ext16u_tl(s->T0, s->T0);
- tcg_gen_st32_tl(s->T0, cpu_env,
+ tcg_gen_st32_tl(s->T0, tcg_env,
offsetof(CPUX86State,segs[seg_reg].selector));
tcg_gen_shli_tl(cpu_seg_base[seg_reg], s->T0, 4);
}
{
if (PE(s) && !VM86(s)) {
tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);
- gen_helper_load_seg(cpu_env, tcg_constant_i32(seg_reg), s->tmp2_i32);
+ gen_helper_load_seg(tcg_env, tcg_constant_i32(seg_reg), s->tmp2_i32);
/* abort translation because the addseg value may change or
because ss32 may change. For R_SS, translation must always
stop as a special handling must be done to disable hardware
if (likely(!GUEST(s))) {
return;
}
- gen_helper_svm_check_intercept(cpu_env, tcg_constant_i32(type));
+ gen_helper_svm_check_intercept(tcg_env, tcg_constant_i32(type));
}
static inline void gen_stack_update(DisasContext *s, int addend)
{
gen_update_cc_op(s);
gen_update_eip_cur(s);
- gen_helper_raise_interrupt(cpu_env, tcg_constant_i32(intno),
+ gen_helper_raise_interrupt(tcg_env, tcg_constant_i32(intno),
cur_insn_len_i32(s));
s->base.is_jmp = DISAS_NORETURN;
}
{
if ((s->flags & mask) == 0) {
TCGv_i32 t = tcg_temp_new_i32();
- tcg_gen_ld_i32(t, cpu_env, offsetof(CPUX86State, hflags));
+ tcg_gen_ld_i32(t, tcg_env, offsetof(CPUX86State, hflags));
tcg_gen_ori_i32(t, t, mask);
- tcg_gen_st_i32(t, cpu_env, offsetof(CPUX86State, hflags));
+ tcg_gen_st_i32(t, tcg_env, offsetof(CPUX86State, hflags));
s->flags |= mask;
}
}
{
if (s->flags & mask) {
TCGv_i32 t = tcg_temp_new_i32();
- tcg_gen_ld_i32(t, cpu_env, offsetof(CPUX86State, hflags));
+ tcg_gen_ld_i32(t, tcg_env, offsetof(CPUX86State, hflags));
tcg_gen_andi_i32(t, t, ~mask);
- tcg_gen_st_i32(t, cpu_env, offsetof(CPUX86State, hflags));
+ tcg_gen_st_i32(t, tcg_env, offsetof(CPUX86State, hflags));
s->flags &= ~mask;
}
}
{
TCGv t = tcg_temp_new();
- tcg_gen_ld_tl(t, cpu_env, offsetof(CPUX86State, eflags));
+ tcg_gen_ld_tl(t, tcg_env, offsetof(CPUX86State, eflags));
tcg_gen_ori_tl(t, t, mask);
- tcg_gen_st_tl(t, cpu_env, offsetof(CPUX86State, eflags));
+ tcg_gen_st_tl(t, tcg_env, offsetof(CPUX86State, eflags));
}
static void gen_reset_eflags(DisasContext *s, target_ulong mask)
{
TCGv t = tcg_temp_new();
- tcg_gen_ld_tl(t, cpu_env, offsetof(CPUX86State, eflags));
+ tcg_gen_ld_tl(t, tcg_env, offsetof(CPUX86State, eflags));
tcg_gen_andi_tl(t, t, ~mask);
- tcg_gen_st_tl(t, cpu_env, offsetof(CPUX86State, eflags));
+ tcg_gen_st_tl(t, tcg_env, offsetof(CPUX86State, eflags));
}
/* Clear BND registers during legacy branches. */
if ((s->prefix & PREFIX_REPNZ) == 0
&& (s->flags & HF_MPX_EN_MASK) != 0
&& (s->flags & HF_MPX_IU_MASK) != 0) {
- gen_helper_bnd_jmp(cpu_env);
+ gen_helper_bnd_jmp(tcg_env);
}
}
gen_reset_eflags(s, RF_MASK);
}
if (recheck_tf) {
- gen_helper_rechecking_single_step(cpu_env);
+ gen_helper_rechecking_single_step(tcg_env);
tcg_gen_exit_tb(NULL, 0);
} else if (s->flags & HF_TF_MASK) {
- gen_helper_single_step(cpu_env);
+ gen_helper_single_step(tcg_env);
} else if (jr) {
tcg_gen_lookup_and_goto_ptr();
} else {
static inline void gen_ldq_env_A0(DisasContext *s, int offset)
{
tcg_gen_qemu_ld_i64(s->tmp1_i64, s->A0, s->mem_index, MO_LEUQ);
- tcg_gen_st_i64(s->tmp1_i64, cpu_env, offset);
+ tcg_gen_st_i64(s->tmp1_i64, tcg_env, offset);
}
static inline void gen_stq_env_A0(DisasContext *s, int offset)
{
- tcg_gen_ld_i64(s->tmp1_i64, cpu_env, offset);
+ tcg_gen_ld_i64(s->tmp1_i64, tcg_env, offset);
tcg_gen_qemu_st_i64(s->tmp1_i64, s->A0, s->mem_index, MO_LEUQ);
}
int mem_index = s->mem_index;
tcg_gen_qemu_ld_i64(s->tmp1_i64, s->A0, mem_index,
MO_LEUQ | (align ? MO_ALIGN_16 : 0));
- tcg_gen_st_i64(s->tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
+ tcg_gen_st_i64(s->tmp1_i64, tcg_env, offset + offsetof(XMMReg, XMM_Q(0)));
tcg_gen_addi_tl(s->tmp0, s->A0, 8);
tcg_gen_qemu_ld_i64(s->tmp1_i64, s->tmp0, mem_index, MO_LEUQ);
- tcg_gen_st_i64(s->tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
+ tcg_gen_st_i64(s->tmp1_i64, tcg_env, offset + offsetof(XMMReg, XMM_Q(1)));
}
static inline void gen_sto_env_A0(DisasContext *s, int offset, bool align)
{
int mem_index = s->mem_index;
- tcg_gen_ld_i64(s->tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
+ tcg_gen_ld_i64(s->tmp1_i64, tcg_env, offset + offsetof(XMMReg, XMM_Q(0)));
tcg_gen_qemu_st_i64(s->tmp1_i64, s->A0, mem_index,
MO_LEUQ | (align ? MO_ALIGN_16 : 0));
tcg_gen_addi_tl(s->tmp0, s->A0, 8);
- tcg_gen_ld_i64(s->tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
+ tcg_gen_ld_i64(s->tmp1_i64, tcg_env, offset + offsetof(XMMReg, XMM_Q(1)));
tcg_gen_qemu_st_i64(s->tmp1_i64, s->tmp0, mem_index, MO_LEUQ);
}
int mem_index = s->mem_index;
tcg_gen_qemu_ld_i64(s->tmp1_i64, s->A0, mem_index,
MO_LEUQ | (align ? MO_ALIGN_32 : 0));
- tcg_gen_st_i64(s->tmp1_i64, cpu_env, offset + offsetof(YMMReg, YMM_Q(0)));
+ tcg_gen_st_i64(s->tmp1_i64, tcg_env, offset + offsetof(YMMReg, YMM_Q(0)));
tcg_gen_addi_tl(s->tmp0, s->A0, 8);
tcg_gen_qemu_ld_i64(s->tmp1_i64, s->tmp0, mem_index, MO_LEUQ);
- tcg_gen_st_i64(s->tmp1_i64, cpu_env, offset + offsetof(YMMReg, YMM_Q(1)));
+ tcg_gen_st_i64(s->tmp1_i64, tcg_env, offset + offsetof(YMMReg, YMM_Q(1)));
tcg_gen_addi_tl(s->tmp0, s->A0, 16);
tcg_gen_qemu_ld_i64(s->tmp1_i64, s->tmp0, mem_index, MO_LEUQ);
- tcg_gen_st_i64(s->tmp1_i64, cpu_env, offset + offsetof(YMMReg, YMM_Q(2)));
+ tcg_gen_st_i64(s->tmp1_i64, tcg_env, offset + offsetof(YMMReg, YMM_Q(2)));
tcg_gen_addi_tl(s->tmp0, s->A0, 24);
tcg_gen_qemu_ld_i64(s->tmp1_i64, s->tmp0, mem_index, MO_LEUQ);
- tcg_gen_st_i64(s->tmp1_i64, cpu_env, offset + offsetof(YMMReg, YMM_Q(3)));
+ tcg_gen_st_i64(s->tmp1_i64, tcg_env, offset + offsetof(YMMReg, YMM_Q(3)));
}
static void gen_sty_env_A0(DisasContext *s, int offset, bool align)
{
int mem_index = s->mem_index;
- tcg_gen_ld_i64(s->tmp1_i64, cpu_env, offset + offsetof(YMMReg, YMM_Q(0)));
+ tcg_gen_ld_i64(s->tmp1_i64, tcg_env, offset + offsetof(YMMReg, YMM_Q(0)));
tcg_gen_qemu_st_i64(s->tmp1_i64, s->A0, mem_index,
MO_LEUQ | (align ? MO_ALIGN_32 : 0));
tcg_gen_addi_tl(s->tmp0, s->A0, 8);
- tcg_gen_ld_i64(s->tmp1_i64, cpu_env, offset + offsetof(YMMReg, YMM_Q(1)));
+ tcg_gen_ld_i64(s->tmp1_i64, tcg_env, offset + offsetof(YMMReg, YMM_Q(1)));
tcg_gen_qemu_st_i64(s->tmp1_i64, s->tmp0, mem_index, MO_LEUQ);
tcg_gen_addi_tl(s->tmp0, s->A0, 16);
- tcg_gen_ld_i64(s->tmp1_i64, cpu_env, offset + offsetof(YMMReg, YMM_Q(2)));
+ tcg_gen_ld_i64(s->tmp1_i64, tcg_env, offset + offsetof(YMMReg, YMM_Q(2)));
tcg_gen_qemu_st_i64(s->tmp1_i64, s->tmp0, mem_index, MO_LEUQ);
tcg_gen_addi_tl(s->tmp0, s->A0, 24);
- tcg_gen_ld_i64(s->tmp1_i64, cpu_env, offset + offsetof(YMMReg, YMM_Q(3)));
+ tcg_gen_ld_i64(s->tmp1_i64, tcg_env, offset + offsetof(YMMReg, YMM_Q(3)));
tcg_gen_qemu_st_i64(s->tmp1_i64, s->tmp0, mem_index, MO_LEUQ);
}
case 6: /* div */
switch(ot) {
case MO_8:
- gen_helper_divb_AL(cpu_env, s->T0);
+ gen_helper_divb_AL(tcg_env, s->T0);
break;
case MO_16:
- gen_helper_divw_AX(cpu_env, s->T0);
+ gen_helper_divw_AX(tcg_env, s->T0);
break;
default:
case MO_32:
- gen_helper_divl_EAX(cpu_env, s->T0);
+ gen_helper_divl_EAX(tcg_env, s->T0);
break;
#ifdef TARGET_X86_64
case MO_64:
- gen_helper_divq_EAX(cpu_env, s->T0);
+ gen_helper_divq_EAX(tcg_env, s->T0);
break;
#endif
}
case 7: /* idiv */
switch(ot) {
case MO_8:
- gen_helper_idivb_AL(cpu_env, s->T0);
+ gen_helper_idivb_AL(tcg_env, s->T0);
break;
case MO_16:
- gen_helper_idivw_AX(cpu_env, s->T0);
+ gen_helper_idivw_AX(tcg_env, s->T0);
break;
default:
case MO_32:
- gen_helper_idivl_EAX(cpu_env, s->T0);
+ gen_helper_idivl_EAX(tcg_env, s->T0);
break;
#ifdef TARGET_X86_64
case MO_64:
- gen_helper_idivq_EAX(cpu_env, s->T0);
+ gen_helper_idivq_EAX(tcg_env, s->T0);
break;
#endif
}
do_lcall:
if (PE(s) && !VM86(s)) {
tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);
- gen_helper_lcall_protected(cpu_env, s->tmp2_i32, s->T1,
+ gen_helper_lcall_protected(tcg_env, s->tmp2_i32, s->T1,
tcg_constant_i32(dflag - 1),
eip_next_tl(s));
} else {
tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);
tcg_gen_trunc_tl_i32(s->tmp3_i32, s->T1);
- gen_helper_lcall_real(cpu_env, s->tmp2_i32, s->tmp3_i32,
+ gen_helper_lcall_real(tcg_env, s->tmp2_i32, s->tmp3_i32,
tcg_constant_i32(dflag - 1),
eip_next_i32(s));
}
do_ljmp:
if (PE(s) && !VM86(s)) {
tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);
- gen_helper_ljmp_protected(cpu_env, s->tmp2_i32, s->T1,
+ gen_helper_ljmp_protected(tcg_env, s->tmp2_i32, s->T1,
eip_next_tl(s));
} else {
gen_op_movl_seg_T0_vm(s, R_CS);
if (!(s->cpuid_ext_features & CPUID_7_0_ECX_RDPID)) {
goto illegal_op;
}
- gen_helper_rdpid(s->T0, cpu_env);
+ gen_helper_rdpid(s->T0, tcg_env);
rm = (modrm & 7) | REX_B(s);
gen_op_mov_reg_v(s, dflag, rm, s->T0);
break;
}
do_rdrand:
translator_io_start(&s->base);
- gen_helper_rdrand(s->T0, cpu_env);
+ gen_helper_rdrand(s->T0, tcg_env);
rm = (modrm & 7) | REX_B(s);
gen_op_mov_reg_v(s, dflag, rm, s->T0);
set_cc_op(s, CC_OP_EFLAGS);
case 0:
tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0,
s->mem_index, MO_LEUL);
- gen_helper_flds_FT0(cpu_env, s->tmp2_i32);
+ gen_helper_flds_FT0(tcg_env, s->tmp2_i32);
break;
case 1:
tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0,
s->mem_index, MO_LEUL);
- gen_helper_fildl_FT0(cpu_env, s->tmp2_i32);
+ gen_helper_fildl_FT0(tcg_env, s->tmp2_i32);
break;
case 2:
tcg_gen_qemu_ld_i64(s->tmp1_i64, s->A0,
s->mem_index, MO_LEUQ);
- gen_helper_fldl_FT0(cpu_env, s->tmp1_i64);
+ gen_helper_fldl_FT0(tcg_env, s->tmp1_i64);
break;
case 3:
default:
tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0,
s->mem_index, MO_LESW);
- gen_helper_fildl_FT0(cpu_env, s->tmp2_i32);
+ gen_helper_fildl_FT0(tcg_env, s->tmp2_i32);
break;
}
gen_helper_fp_arith_ST0_FT0(op1);
if (op1 == 3) {
/* fcomp needs pop */
- gen_helper_fpop(cpu_env);
+ gen_helper_fpop(tcg_env);
}
}
break;
case 0:
tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0,
s->mem_index, MO_LEUL);
- gen_helper_flds_ST0(cpu_env, s->tmp2_i32);
+ gen_helper_flds_ST0(tcg_env, s->tmp2_i32);
break;
case 1:
tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0,
s->mem_index, MO_LEUL);
- gen_helper_fildl_ST0(cpu_env, s->tmp2_i32);
+ gen_helper_fildl_ST0(tcg_env, s->tmp2_i32);
break;
case 2:
tcg_gen_qemu_ld_i64(s->tmp1_i64, s->A0,
s->mem_index, MO_LEUQ);
- gen_helper_fldl_ST0(cpu_env, s->tmp1_i64);
+ gen_helper_fldl_ST0(tcg_env, s->tmp1_i64);
break;
case 3:
default:
tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0,
s->mem_index, MO_LESW);
- gen_helper_fildl_ST0(cpu_env, s->tmp2_i32);
+ gen_helper_fildl_ST0(tcg_env, s->tmp2_i32);
break;
}
break;
/* XXX: the corresponding CPUID bit must be tested ! */
switch (op >> 4) {
case 1:
- gen_helper_fisttl_ST0(s->tmp2_i32, cpu_env);
+ gen_helper_fisttl_ST0(s->tmp2_i32, tcg_env);
tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0,
s->mem_index, MO_LEUL);
break;
case 2:
- gen_helper_fisttll_ST0(s->tmp1_i64, cpu_env);
+ gen_helper_fisttll_ST0(s->tmp1_i64, tcg_env);
tcg_gen_qemu_st_i64(s->tmp1_i64, s->A0,
s->mem_index, MO_LEUQ);
break;
case 3:
default:
- gen_helper_fistt_ST0(s->tmp2_i32, cpu_env);
+ gen_helper_fistt_ST0(s->tmp2_i32, tcg_env);
tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0,
s->mem_index, MO_LEUW);
break;
}
- gen_helper_fpop(cpu_env);
+ gen_helper_fpop(tcg_env);
break;
default:
switch (op >> 4) {
case 0:
- gen_helper_fsts_ST0(s->tmp2_i32, cpu_env);
+ gen_helper_fsts_ST0(s->tmp2_i32, tcg_env);
tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0,
s->mem_index, MO_LEUL);
break;
case 1:
- gen_helper_fistl_ST0(s->tmp2_i32, cpu_env);
+ gen_helper_fistl_ST0(s->tmp2_i32, tcg_env);
tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0,
s->mem_index, MO_LEUL);
break;
case 2:
- gen_helper_fstl_ST0(s->tmp1_i64, cpu_env);
+ gen_helper_fstl_ST0(s->tmp1_i64, tcg_env);
tcg_gen_qemu_st_i64(s->tmp1_i64, s->A0,
s->mem_index, MO_LEUQ);
break;
case 3:
default:
- gen_helper_fist_ST0(s->tmp2_i32, cpu_env);
+ gen_helper_fist_ST0(s->tmp2_i32, tcg_env);
tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0,
s->mem_index, MO_LEUW);
break;
}
if ((op & 7) == 3) {
- gen_helper_fpop(cpu_env);
+ gen_helper_fpop(tcg_env);
}
break;
}
break;
case 0x0c: /* fldenv mem */
- gen_helper_fldenv(cpu_env, s->A0,
+ gen_helper_fldenv(tcg_env, s->A0,
tcg_constant_i32(dflag - 1));
update_fip = update_fdp = false;
break;
case 0x0d: /* fldcw mem */
tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0,
s->mem_index, MO_LEUW);
- gen_helper_fldcw(cpu_env, s->tmp2_i32);
+ gen_helper_fldcw(tcg_env, s->tmp2_i32);
update_fip = update_fdp = false;
break;
case 0x0e: /* fnstenv mem */
- gen_helper_fstenv(cpu_env, s->A0,
+ gen_helper_fstenv(tcg_env, s->A0,
tcg_constant_i32(dflag - 1));
update_fip = update_fdp = false;
break;
case 0x0f: /* fnstcw mem */
- gen_helper_fnstcw(s->tmp2_i32, cpu_env);
+ gen_helper_fnstcw(s->tmp2_i32, tcg_env);
tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0,
s->mem_index, MO_LEUW);
update_fip = update_fdp = false;
break;
case 0x1d: /* fldt mem */
- gen_helper_fldt_ST0(cpu_env, s->A0);
+ gen_helper_fldt_ST0(tcg_env, s->A0);
break;
case 0x1f: /* fstpt mem */
- gen_helper_fstt_ST0(cpu_env, s->A0);
- gen_helper_fpop(cpu_env);
+ gen_helper_fstt_ST0(tcg_env, s->A0);
+ gen_helper_fpop(tcg_env);
break;
case 0x2c: /* frstor mem */
- gen_helper_frstor(cpu_env, s->A0,
+ gen_helper_frstor(tcg_env, s->A0,
tcg_constant_i32(dflag - 1));
update_fip = update_fdp = false;
break;
case 0x2e: /* fnsave mem */
- gen_helper_fsave(cpu_env, s->A0,
+ gen_helper_fsave(tcg_env, s->A0,
tcg_constant_i32(dflag - 1));
update_fip = update_fdp = false;
break;
case 0x2f: /* fnstsw mem */
- gen_helper_fnstsw(s->tmp2_i32, cpu_env);
+ gen_helper_fnstsw(s->tmp2_i32, tcg_env);
tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0,
s->mem_index, MO_LEUW);
update_fip = update_fdp = false;
break;
case 0x3c: /* fbld */
- gen_helper_fbld_ST0(cpu_env, s->A0);
+ gen_helper_fbld_ST0(tcg_env, s->A0);
break;
case 0x3e: /* fbstp */
- gen_helper_fbst_ST0(cpu_env, s->A0);
- gen_helper_fpop(cpu_env);
+ gen_helper_fbst_ST0(tcg_env, s->A0);
+ gen_helper_fpop(tcg_env);
break;
case 0x3d: /* fildll */
tcg_gen_qemu_ld_i64(s->tmp1_i64, s->A0,
s->mem_index, MO_LEUQ);
- gen_helper_fildll_ST0(cpu_env, s->tmp1_i64);
+ gen_helper_fildll_ST0(tcg_env, s->tmp1_i64);
break;
case 0x3f: /* fistpll */
- gen_helper_fistll_ST0(s->tmp1_i64, cpu_env);
+ gen_helper_fistll_ST0(s->tmp1_i64, tcg_env);
tcg_gen_qemu_st_i64(s->tmp1_i64, s->A0,
s->mem_index, MO_LEUQ);
- gen_helper_fpop(cpu_env);
+ gen_helper_fpop(tcg_env);
break;
default:
goto unknown_op;
if (update_fdp) {
int last_seg = s->override >= 0 ? s->override : a.def_seg;
- tcg_gen_ld_i32(s->tmp2_i32, cpu_env,
+ tcg_gen_ld_i32(s->tmp2_i32, tcg_env,
offsetof(CPUX86State,
segs[last_seg].selector));
- tcg_gen_st16_i32(s->tmp2_i32, cpu_env,
+ tcg_gen_st16_i32(s->tmp2_i32, tcg_env,
offsetof(CPUX86State, fpds));
- tcg_gen_st_tl(last_addr, cpu_env,
+ tcg_gen_st_tl(last_addr, tcg_env,
offsetof(CPUX86State, fpdp));
}
} else {
switch (op) {
case 0x08: /* fld sti */
- gen_helper_fpush(cpu_env);
- gen_helper_fmov_ST0_STN(cpu_env,
+ gen_helper_fpush(tcg_env);
+ gen_helper_fmov_ST0_STN(tcg_env,
tcg_constant_i32((opreg + 1) & 7));
break;
case 0x09: /* fxchg sti */
case 0x29: /* fxchg4 sti, undocumented op */
case 0x39: /* fxchg7 sti, undocumented op */
- gen_helper_fxchg_ST0_STN(cpu_env, tcg_constant_i32(opreg));
+ gen_helper_fxchg_ST0_STN(tcg_env, tcg_constant_i32(opreg));
break;
case 0x0a: /* grp d9/2 */
switch (rm) {
* needs to be treated as I/O because of ferr_irq
*/
translator_io_start(&s->base);
- gen_helper_fwait(cpu_env);
+ gen_helper_fwait(tcg_env);
update_fip = false;
break;
default:
case 0x0c: /* grp d9/4 */
switch (rm) {
case 0: /* fchs */
- gen_helper_fchs_ST0(cpu_env);
+ gen_helper_fchs_ST0(tcg_env);
break;
case 1: /* fabs */
- gen_helper_fabs_ST0(cpu_env);
+ gen_helper_fabs_ST0(tcg_env);
break;
case 4: /* ftst */
- gen_helper_fldz_FT0(cpu_env);
- gen_helper_fcom_ST0_FT0(cpu_env);
+ gen_helper_fldz_FT0(tcg_env);
+ gen_helper_fcom_ST0_FT0(tcg_env);
break;
case 5: /* fxam */
- gen_helper_fxam_ST0(cpu_env);
+ gen_helper_fxam_ST0(tcg_env);
break;
default:
goto unknown_op;
{
switch (rm) {
case 0:
- gen_helper_fpush(cpu_env);
- gen_helper_fld1_ST0(cpu_env);
+ gen_helper_fpush(tcg_env);
+ gen_helper_fld1_ST0(tcg_env);
break;
case 1:
- gen_helper_fpush(cpu_env);
- gen_helper_fldl2t_ST0(cpu_env);
+ gen_helper_fpush(tcg_env);
+ gen_helper_fldl2t_ST0(tcg_env);
break;
case 2:
- gen_helper_fpush(cpu_env);
- gen_helper_fldl2e_ST0(cpu_env);
+ gen_helper_fpush(tcg_env);
+ gen_helper_fldl2e_ST0(tcg_env);
break;
case 3:
- gen_helper_fpush(cpu_env);
- gen_helper_fldpi_ST0(cpu_env);
+ gen_helper_fpush(tcg_env);
+ gen_helper_fldpi_ST0(tcg_env);
break;
case 4:
- gen_helper_fpush(cpu_env);
- gen_helper_fldlg2_ST0(cpu_env);
+ gen_helper_fpush(tcg_env);
+ gen_helper_fldlg2_ST0(tcg_env);
break;
case 5:
- gen_helper_fpush(cpu_env);
- gen_helper_fldln2_ST0(cpu_env);
+ gen_helper_fpush(tcg_env);
+ gen_helper_fldln2_ST0(tcg_env);
break;
case 6:
- gen_helper_fpush(cpu_env);
- gen_helper_fldz_ST0(cpu_env);
+ gen_helper_fpush(tcg_env);
+ gen_helper_fldz_ST0(tcg_env);
break;
default:
goto unknown_op;
case 0x0e: /* grp d9/6 */
switch (rm) {
case 0: /* f2xm1 */
- gen_helper_f2xm1(cpu_env);
+ gen_helper_f2xm1(tcg_env);
break;
case 1: /* fyl2x */
- gen_helper_fyl2x(cpu_env);
+ gen_helper_fyl2x(tcg_env);
break;
case 2: /* fptan */
- gen_helper_fptan(cpu_env);
+ gen_helper_fptan(tcg_env);
break;
case 3: /* fpatan */
- gen_helper_fpatan(cpu_env);
+ gen_helper_fpatan(tcg_env);
break;
case 4: /* fxtract */
- gen_helper_fxtract(cpu_env);
+ gen_helper_fxtract(tcg_env);
break;
case 5: /* fprem1 */
- gen_helper_fprem1(cpu_env);
+ gen_helper_fprem1(tcg_env);
break;
case 6: /* fdecstp */
- gen_helper_fdecstp(cpu_env);
+ gen_helper_fdecstp(tcg_env);
break;
default:
case 7: /* fincstp */
- gen_helper_fincstp(cpu_env);
+ gen_helper_fincstp(tcg_env);
break;
}
break;
case 0x0f: /* grp d9/7 */
switch (rm) {
case 0: /* fprem */
- gen_helper_fprem(cpu_env);
+ gen_helper_fprem(tcg_env);
break;
case 1: /* fyl2xp1 */
- gen_helper_fyl2xp1(cpu_env);
+ gen_helper_fyl2xp1(tcg_env);
break;
case 2: /* fsqrt */
- gen_helper_fsqrt(cpu_env);
+ gen_helper_fsqrt(tcg_env);
break;
case 3: /* fsincos */
- gen_helper_fsincos(cpu_env);
+ gen_helper_fsincos(tcg_env);
break;
case 5: /* fscale */
- gen_helper_fscale(cpu_env);
+ gen_helper_fscale(tcg_env);
break;
case 4: /* frndint */
- gen_helper_frndint(cpu_env);
+ gen_helper_frndint(tcg_env);
break;
case 6: /* fsin */
- gen_helper_fsin(cpu_env);
+ gen_helper_fsin(tcg_env);
break;
default:
case 7: /* fcos */
- gen_helper_fcos(cpu_env);
+ gen_helper_fcos(tcg_env);
break;
}
break;
if (op >= 0x20) {
gen_helper_fp_arith_STN_ST0(op1, opreg);
if (op >= 0x30) {
- gen_helper_fpop(cpu_env);
+ gen_helper_fpop(tcg_env);
}
} else {
- gen_helper_fmov_FT0_STN(cpu_env,
+ gen_helper_fmov_FT0_STN(tcg_env,
tcg_constant_i32(opreg));
gen_helper_fp_arith_ST0_FT0(op1);
}
break;
case 0x02: /* fcom */
case 0x22: /* fcom2, undocumented op */
- gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(opreg));
- gen_helper_fcom_ST0_FT0(cpu_env);
+ gen_helper_fmov_FT0_STN(tcg_env, tcg_constant_i32(opreg));
+ gen_helper_fcom_ST0_FT0(tcg_env);
break;
case 0x03: /* fcomp */
case 0x23: /* fcomp3, undocumented op */
case 0x32: /* fcomp5, undocumented op */
- gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(opreg));
- gen_helper_fcom_ST0_FT0(cpu_env);
- gen_helper_fpop(cpu_env);
+ gen_helper_fmov_FT0_STN(tcg_env, tcg_constant_i32(opreg));
+ gen_helper_fcom_ST0_FT0(tcg_env);
+ gen_helper_fpop(tcg_env);
break;
case 0x15: /* da/5 */
switch (rm) {
case 1: /* fucompp */
- gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(1));
- gen_helper_fucom_ST0_FT0(cpu_env);
- gen_helper_fpop(cpu_env);
- gen_helper_fpop(cpu_env);
+ gen_helper_fmov_FT0_STN(tcg_env, tcg_constant_i32(1));
+ gen_helper_fucom_ST0_FT0(tcg_env);
+ gen_helper_fpop(tcg_env);
+ gen_helper_fpop(tcg_env);
break;
default:
goto unknown_op;
case 1: /* fdisi (287 only, just do nop here) */
break;
case 2: /* fclex */
- gen_helper_fclex(cpu_env);
+ gen_helper_fclex(tcg_env);
update_fip = false;
break;
case 3: /* fninit */
- gen_helper_fninit(cpu_env);
+ gen_helper_fninit(tcg_env);
update_fip = false;
break;
case 4: /* fsetpm (287 only, just do nop here) */
goto illegal_op;
}
gen_update_cc_op(s);
- gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(opreg));
- gen_helper_fucomi_ST0_FT0(cpu_env);
+ gen_helper_fmov_FT0_STN(tcg_env, tcg_constant_i32(opreg));
+ gen_helper_fucomi_ST0_FT0(tcg_env);
set_cc_op(s, CC_OP_EFLAGS);
break;
case 0x1e: /* fcomi */
goto illegal_op;
}
gen_update_cc_op(s);
- gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(opreg));
- gen_helper_fcomi_ST0_FT0(cpu_env);
+ gen_helper_fmov_FT0_STN(tcg_env, tcg_constant_i32(opreg));
+ gen_helper_fcomi_ST0_FT0(tcg_env);
set_cc_op(s, CC_OP_EFLAGS);
break;
case 0x28: /* ffree sti */
- gen_helper_ffree_STN(cpu_env, tcg_constant_i32(opreg));
+ gen_helper_ffree_STN(tcg_env, tcg_constant_i32(opreg));
break;
case 0x2a: /* fst sti */
- gen_helper_fmov_STN_ST0(cpu_env, tcg_constant_i32(opreg));
+ gen_helper_fmov_STN_ST0(tcg_env, tcg_constant_i32(opreg));
break;
case 0x2b: /* fstp sti */
case 0x0b: /* fstp1 sti, undocumented op */
case 0x3a: /* fstp8 sti, undocumented op */
case 0x3b: /* fstp9 sti, undocumented op */
- gen_helper_fmov_STN_ST0(cpu_env, tcg_constant_i32(opreg));
- gen_helper_fpop(cpu_env);
+ gen_helper_fmov_STN_ST0(tcg_env, tcg_constant_i32(opreg));
+ gen_helper_fpop(tcg_env);
break;
case 0x2c: /* fucom st(i) */
- gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(opreg));
- gen_helper_fucom_ST0_FT0(cpu_env);
+ gen_helper_fmov_FT0_STN(tcg_env, tcg_constant_i32(opreg));
+ gen_helper_fucom_ST0_FT0(tcg_env);
break;
case 0x2d: /* fucomp st(i) */
- gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(opreg));
- gen_helper_fucom_ST0_FT0(cpu_env);
- gen_helper_fpop(cpu_env);
+ gen_helper_fmov_FT0_STN(tcg_env, tcg_constant_i32(opreg));
+ gen_helper_fucom_ST0_FT0(tcg_env);
+ gen_helper_fpop(tcg_env);
break;
case 0x33: /* de/3 */
switch (rm) {
case 1: /* fcompp */
- gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(1));
- gen_helper_fcom_ST0_FT0(cpu_env);
- gen_helper_fpop(cpu_env);
- gen_helper_fpop(cpu_env);
+ gen_helper_fmov_FT0_STN(tcg_env, tcg_constant_i32(1));
+ gen_helper_fcom_ST0_FT0(tcg_env);
+ gen_helper_fpop(tcg_env);
+ gen_helper_fpop(tcg_env);
break;
default:
goto unknown_op;
}
break;
case 0x38: /* ffreep sti, undocumented op */
- gen_helper_ffree_STN(cpu_env, tcg_constant_i32(opreg));
- gen_helper_fpop(cpu_env);
+ gen_helper_ffree_STN(tcg_env, tcg_constant_i32(opreg));
+ gen_helper_fpop(tcg_env);
break;
case 0x3c: /* df/4 */
switch (rm) {
case 0:
- gen_helper_fnstsw(s->tmp2_i32, cpu_env);
+ gen_helper_fnstsw(s->tmp2_i32, tcg_env);
tcg_gen_extu_i32_tl(s->T0, s->tmp2_i32);
gen_op_mov_reg_v(s, MO_16, R_EAX, s->T0);
break;
goto illegal_op;
}
gen_update_cc_op(s);
- gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(opreg));
- gen_helper_fucomi_ST0_FT0(cpu_env);
- gen_helper_fpop(cpu_env);
+ gen_helper_fmov_FT0_STN(tcg_env, tcg_constant_i32(opreg));
+ gen_helper_fucomi_ST0_FT0(tcg_env);
+ gen_helper_fpop(tcg_env);
set_cc_op(s, CC_OP_EFLAGS);
break;
case 0x3e: /* fcomip */
goto illegal_op;
}
gen_update_cc_op(s);
- gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(opreg));
- gen_helper_fcomi_ST0_FT0(cpu_env);
- gen_helper_fpop(cpu_env);
+ gen_helper_fmov_FT0_STN(tcg_env, tcg_constant_i32(opreg));
+ gen_helper_fcomi_ST0_FT0(tcg_env);
+ gen_helper_fpop(tcg_env);
set_cc_op(s, CC_OP_EFLAGS);
break;
case 0x10 ... 0x13: /* fcmovxx */
op1 = fcmov_cc[op & 3] | (((op >> 3) & 1) ^ 1);
l1 = gen_new_label();
gen_jcc1_noeob(s, op1, l1);
- gen_helper_fmov_ST0_STN(cpu_env,
+ gen_helper_fmov_ST0_STN(tcg_env,
tcg_constant_i32(opreg));
gen_set_label(l1);
}
}
if (update_fip) {
- tcg_gen_ld_i32(s->tmp2_i32, cpu_env,
+ tcg_gen_ld_i32(s->tmp2_i32, tcg_env,
offsetof(CPUX86State, segs[R_CS].selector));
- tcg_gen_st16_i32(s->tmp2_i32, cpu_env,
+ tcg_gen_st16_i32(s->tmp2_i32, tcg_env,
offsetof(CPUX86State, fpcs));
tcg_gen_st_tl(eip_cur_tl(s),
- cpu_env, offsetof(CPUX86State, fpip));
+ tcg_env, offsetof(CPUX86State, fpip));
}
}
break;
if (PE(s) && !VM86(s)) {
gen_update_cc_op(s);
gen_update_eip_cur(s);
- gen_helper_lret_protected(cpu_env, tcg_constant_i32(dflag - 1),
+ gen_helper_lret_protected(tcg_env, tcg_constant_i32(dflag - 1),
tcg_constant_i32(val));
} else {
gen_stack_A0(s);
if (!check_vm86_iopl(s)) {
break;
}
- gen_helper_iret_real(cpu_env, tcg_constant_i32(dflag - 1));
+ gen_helper_iret_real(tcg_env, tcg_constant_i32(dflag - 1));
} else {
- gen_helper_iret_protected(cpu_env, tcg_constant_i32(dflag - 1),
+ gen_helper_iret_protected(tcg_env, tcg_constant_i32(dflag - 1),
eip_next_i32(s));
}
set_cc_op(s, CC_OP_EFLAGS);
gen_svm_check_intercept(s, SVM_EXIT_PUSHF);
if (check_vm86_iopl(s)) {
gen_update_cc_op(s);
- gen_helper_read_eflags(s->T0, cpu_env);
+ gen_helper_read_eflags(s->T0, tcg_env);
gen_push_v(s, s->T0);
}
break;
}
ot = gen_pop_T0(s);
- gen_helper_write_eflags(cpu_env, s->T0, tcg_constant_i32(mask));
+ gen_helper_write_eflags(tcg_env, s->T0, tcg_constant_i32(mask));
gen_pop_update(s, ot);
set_cc_op(s, CC_OP_EFLAGS);
/* abort translation because TF/AC flag may change */
break;
case 0xfc: /* cld */
tcg_gen_movi_i32(s->tmp2_i32, 1);
- tcg_gen_st_i32(s->tmp2_i32, cpu_env, offsetof(CPUX86State, df));
+ tcg_gen_st_i32(s->tmp2_i32, tcg_env, offsetof(CPUX86State, df));
break;
case 0xfd: /* std */
tcg_gen_movi_i32(s->tmp2_i32, -1);
- tcg_gen_st_i32(s->tmp2_i32, cpu_env, offsetof(CPUX86State, df));
+ tcg_gen_st_i32(s->tmp2_i32, tcg_env, offsetof(CPUX86State, df));
break;
/************************/
if (CODE64(s))
goto illegal_op;
gen_update_cc_op(s);
- gen_helper_daa(cpu_env);
+ gen_helper_daa(tcg_env);
set_cc_op(s, CC_OP_EFLAGS);
break;
case 0x2f: /* das */
if (CODE64(s))
goto illegal_op;
gen_update_cc_op(s);
- gen_helper_das(cpu_env);
+ gen_helper_das(tcg_env);
set_cc_op(s, CC_OP_EFLAGS);
break;
case 0x37: /* aaa */
if (CODE64(s))
goto illegal_op;
gen_update_cc_op(s);
- gen_helper_aaa(cpu_env);
+ gen_helper_aaa(tcg_env);
set_cc_op(s, CC_OP_EFLAGS);
break;
case 0x3f: /* aas */
if (CODE64(s))
goto illegal_op;
gen_update_cc_op(s);
- gen_helper_aas(cpu_env);
+ gen_helper_aas(tcg_env);
set_cc_op(s, CC_OP_EFLAGS);
break;
case 0xd4: /* aam */
if (val == 0) {
gen_exception(s, EXCP00_DIVZ);
} else {
- gen_helper_aam(cpu_env, tcg_constant_i32(val));
+ gen_helper_aam(tcg_env, tcg_constant_i32(val));
set_cc_op(s, CC_OP_LOGICB);
}
break;
if (CODE64(s))
goto illegal_op;
val = x86_ldub_code(env, s);
- gen_helper_aad(cpu_env, tcg_constant_i32(val));
+ gen_helper_aad(tcg_env, tcg_constant_i32(val));
set_cc_op(s, CC_OP_LOGICB);
break;
/************************/
if (prefixes & PREFIX_REPZ) {
gen_update_cc_op(s);
gen_update_eip_cur(s);
- gen_helper_pause(cpu_env, cur_insn_len_i32(s));
+ gen_helper_pause(tcg_env, cur_insn_len_i32(s));
s->base.is_jmp = DISAS_NORETURN;
}
break;
} else {
/* needs to be treated as I/O because of ferr_irq */
translator_io_start(&s->base);
- gen_helper_fwait(cpu_env);
+ gen_helper_fwait(tcg_env);
}
break;
case 0xcc: /* int3 */
goto illegal_op;
gen_update_cc_op(s);
gen_update_eip_cur(s);
- gen_helper_into(cpu_env, cur_insn_len_i32(s));
+ gen_helper_into(tcg_env, cur_insn_len_i32(s));
break;
#ifdef WANT_ICEBP
case 0xf1: /* icebp (undocumented, exits to external debugger) */
gen_lea_modrm(env, s, modrm);
tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);
if (ot == MO_16) {
- gen_helper_boundw(cpu_env, s->A0, s->tmp2_i32);
+ gen_helper_boundw(tcg_env, s->A0, s->tmp2_i32);
} else {
- gen_helper_boundl(cpu_env, s->A0, s->tmp2_i32);
+ gen_helper_boundl(tcg_env, s->A0, s->tmp2_i32);
}
break;
case 0x1c8 ... 0x1cf: /* bswap reg */
gen_update_cc_op(s);
gen_update_eip_cur(s);
if (b & 2) {
- gen_helper_rdmsr(cpu_env);
+ gen_helper_rdmsr(tcg_env);
} else {
- gen_helper_wrmsr(cpu_env);
+ gen_helper_wrmsr(tcg_env);
s->base.is_jmp = DISAS_EOB_NEXT;
}
}
gen_update_cc_op(s);
gen_update_eip_cur(s);
translator_io_start(&s->base);
- gen_helper_rdtsc(cpu_env);
+ gen_helper_rdtsc(tcg_env);
break;
case 0x133: /* rdpmc */
gen_update_cc_op(s);
gen_update_eip_cur(s);
- gen_helper_rdpmc(cpu_env);
+ gen_helper_rdpmc(tcg_env);
s->base.is_jmp = DISAS_NORETURN;
break;
case 0x134: /* sysenter */
if (!PE(s)) {
gen_exception_gpf(s);
} else {
- gen_helper_sysenter(cpu_env);
+ gen_helper_sysenter(tcg_env);
s->base.is_jmp = DISAS_EOB_ONLY;
}
break;
if (!PE(s) || CPL(s) != 0) {
gen_exception_gpf(s);
} else {
- gen_helper_sysexit(cpu_env, tcg_constant_i32(dflag - 1));
+ gen_helper_sysexit(tcg_env, tcg_constant_i32(dflag - 1));
s->base.is_jmp = DISAS_EOB_ONLY;
}
break;
}
gen_update_cc_op(s);
gen_update_eip_cur(s);
- gen_helper_syscall(cpu_env, cur_insn_len_i32(s));
+ gen_helper_syscall(tcg_env, cur_insn_len_i32(s));
/* TF handling for the syscall insn is different. The TF bit is checked
after the syscall insn completes. This allows #DB to not be
generated after one has entered CPL0 if TF is set in FMASK. */
if (!PE(s) || CPL(s) != 0) {
gen_exception_gpf(s);
} else {
- gen_helper_sysret(cpu_env, tcg_constant_i32(dflag - 1));
+ gen_helper_sysret(tcg_env, tcg_constant_i32(dflag - 1));
/* condition codes are modified only in long mode */
if (LMA(s)) {
set_cc_op(s, CC_OP_EFLAGS);
case 0x1a2: /* cpuid */
gen_update_cc_op(s);
gen_update_eip_cur(s);
- gen_helper_cpuid(cpu_env);
+ gen_helper_cpuid(tcg_env);
break;
case 0xf4: /* hlt */
if (check_cpl0(s)) {
gen_update_cc_op(s);
gen_update_eip_cur(s);
- gen_helper_hlt(cpu_env, cur_insn_len_i32(s));
+ gen_helper_hlt(tcg_env, cur_insn_len_i32(s));
s->base.is_jmp = DISAS_NORETURN;
}
break;
break;
}
gen_svm_check_intercept(s, SVM_EXIT_LDTR_READ);
- tcg_gen_ld32u_tl(s->T0, cpu_env,
+ tcg_gen_ld32u_tl(s->T0, tcg_env,
offsetof(CPUX86State, ldt.selector));
ot = mod == 3 ? dflag : MO_16;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
gen_svm_check_intercept(s, SVM_EXIT_LDTR_WRITE);
gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);
tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);
- gen_helper_lldt(cpu_env, s->tmp2_i32);
+ gen_helper_lldt(tcg_env, s->tmp2_i32);
}
break;
case 1: /* str */
break;
}
gen_svm_check_intercept(s, SVM_EXIT_TR_READ);
- tcg_gen_ld32u_tl(s->T0, cpu_env,
+ tcg_gen_ld32u_tl(s->T0, tcg_env,
offsetof(CPUX86State, tr.selector));
ot = mod == 3 ? dflag : MO_16;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
gen_svm_check_intercept(s, SVM_EXIT_TR_WRITE);
gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);
tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);
- gen_helper_ltr(cpu_env, s->tmp2_i32);
+ gen_helper_ltr(tcg_env, s->tmp2_i32);
}
break;
case 4: /* verr */
gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);
gen_update_cc_op(s);
if (op == 4) {
- gen_helper_verr(cpu_env, s->T0);
+ gen_helper_verr(tcg_env, s->T0);
} else {
- gen_helper_verw(cpu_env, s->T0);
+ gen_helper_verw(tcg_env, s->T0);
}
set_cc_op(s, CC_OP_EFLAGS);
break;
gen_svm_check_intercept(s, SVM_EXIT_GDTR_READ);
gen_lea_modrm(env, s, modrm);
tcg_gen_ld32u_tl(s->T0,
- cpu_env, offsetof(CPUX86State, gdt.limit));
+ tcg_env, offsetof(CPUX86State, gdt.limit));
gen_op_st_v(s, MO_16, s->T0, s->A0);
gen_add_A0_im(s, 2);
- tcg_gen_ld_tl(s->T0, cpu_env, offsetof(CPUX86State, gdt.base));
+ tcg_gen_ld_tl(s->T0, tcg_env, offsetof(CPUX86State, gdt.base));
if (dflag == MO_16) {
tcg_gen_andi_tl(s->T0, s->T0, 0xffffff);
}
tcg_gen_mov_tl(s->A0, cpu_regs[R_EAX]);
gen_extu(s->aflag, s->A0);
gen_add_A0_ds_seg(s);
- gen_helper_monitor(cpu_env, s->A0);
+ gen_helper_monitor(tcg_env, s->A0);
break;
case 0xc9: /* mwait */
}
gen_update_cc_op(s);
gen_update_eip_cur(s);
- gen_helper_mwait(cpu_env, cur_insn_len_i32(s));
+ gen_helper_mwait(tcg_env, cur_insn_len_i32(s));
s->base.is_jmp = DISAS_NORETURN;
break;
}
gen_svm_check_intercept(s, SVM_EXIT_IDTR_READ);
gen_lea_modrm(env, s, modrm);
- tcg_gen_ld32u_tl(s->T0, cpu_env, offsetof(CPUX86State, idt.limit));
+ tcg_gen_ld32u_tl(s->T0, tcg_env, offsetof(CPUX86State, idt.limit));
gen_op_st_v(s, MO_16, s->T0, s->A0);
gen_add_A0_im(s, 2);
- tcg_gen_ld_tl(s->T0, cpu_env, offsetof(CPUX86State, idt.base));
+ tcg_gen_ld_tl(s->T0, tcg_env, offsetof(CPUX86State, idt.base));
if (dflag == MO_16) {
tcg_gen_andi_tl(s->T0, s->T0, 0xffffff);
}
goto illegal_op;
}
tcg_gen_trunc_tl_i32(s->tmp2_i32, cpu_regs[R_ECX]);
- gen_helper_xgetbv(s->tmp1_i64, cpu_env, s->tmp2_i32);
+ gen_helper_xgetbv(s->tmp1_i64, tcg_env, s->tmp2_i32);
tcg_gen_extr_i64_tl(cpu_regs[R_EAX], cpu_regs[R_EDX], s->tmp1_i64);
break;
tcg_gen_concat_tl_i64(s->tmp1_i64, cpu_regs[R_EAX],
cpu_regs[R_EDX]);
tcg_gen_trunc_tl_i32(s->tmp2_i32, cpu_regs[R_ECX]);
- gen_helper_xsetbv(cpu_env, s->tmp2_i32, s->tmp1_i64);
+ gen_helper_xsetbv(tcg_env, s->tmp2_i32, s->tmp1_i64);
/* End TB because translation flags may change. */
s->base.is_jmp = DISAS_EOB_NEXT;
break;
}
gen_update_cc_op(s);
gen_update_eip_cur(s);
- gen_helper_vmrun(cpu_env, tcg_constant_i32(s->aflag - 1),
+ gen_helper_vmrun(tcg_env, tcg_constant_i32(s->aflag - 1),
cur_insn_len_i32(s));
tcg_gen_exit_tb(NULL, 0);
s->base.is_jmp = DISAS_NORETURN;
}
gen_update_cc_op(s);
gen_update_eip_cur(s);
- gen_helper_vmmcall(cpu_env);
+ gen_helper_vmmcall(tcg_env);
break;
case 0xda: /* VMLOAD */
}
gen_update_cc_op(s);
gen_update_eip_cur(s);
- gen_helper_vmload(cpu_env, tcg_constant_i32(s->aflag - 1));
+ gen_helper_vmload(tcg_env, tcg_constant_i32(s->aflag - 1));
break;
case 0xdb: /* VMSAVE */
}
gen_update_cc_op(s);
gen_update_eip_cur(s);
- gen_helper_vmsave(cpu_env, tcg_constant_i32(s->aflag - 1));
+ gen_helper_vmsave(tcg_env, tcg_constant_i32(s->aflag - 1));
break;
case 0xdc: /* STGI */
break;
}
gen_update_cc_op(s);
- gen_helper_stgi(cpu_env);
+ gen_helper_stgi(tcg_env);
s->base.is_jmp = DISAS_EOB_NEXT;
break;
}
gen_update_cc_op(s);
gen_update_eip_cur(s);
- gen_helper_clgi(cpu_env);
+ gen_helper_clgi(tcg_env);
break;
case 0xde: /* SKINIT */
} else {
tcg_gen_ext32u_tl(s->A0, cpu_regs[R_EAX]);
}
- gen_helper_flush_page(cpu_env, s->A0);
+ gen_helper_flush_page(tcg_env, s->A0);
s->base.is_jmp = DISAS_EOB_NEXT;
break;
if (dflag == MO_16) {
tcg_gen_andi_tl(s->T0, s->T0, 0xffffff);
}
- tcg_gen_st_tl(s->T0, cpu_env, offsetof(CPUX86State, gdt.base));
- tcg_gen_st32_tl(s->T1, cpu_env, offsetof(CPUX86State, gdt.limit));
+ tcg_gen_st_tl(s->T0, tcg_env, offsetof(CPUX86State, gdt.base));
+ tcg_gen_st32_tl(s->T1, tcg_env, offsetof(CPUX86State, gdt.limit));
break;
CASE_MODRM_MEM_OP(3): /* lidt */
if (dflag == MO_16) {
tcg_gen_andi_tl(s->T0, s->T0, 0xffffff);
}
- tcg_gen_st_tl(s->T0, cpu_env, offsetof(CPUX86State, idt.base));
- tcg_gen_st32_tl(s->T1, cpu_env, offsetof(CPUX86State, idt.limit));
+ tcg_gen_st_tl(s->T0, tcg_env, offsetof(CPUX86State, idt.base));
+ tcg_gen_st32_tl(s->T1, tcg_env, offsetof(CPUX86State, idt.limit));
break;
CASE_MODRM_OP(4): /* smsw */
break;
}
gen_svm_check_intercept(s, SVM_EXIT_READ_CR0);
- tcg_gen_ld_tl(s->T0, cpu_env, offsetof(CPUX86State, cr[0]));
+ tcg_gen_ld_tl(s->T0, tcg_env, offsetof(CPUX86State, cr[0]));
/*
* In 32-bit mode, the higher 16 bits of the destination
* register are undefined. In practice CR0[31:0] is stored
goto illegal_op;
}
tcg_gen_trunc_tl_i32(s->tmp2_i32, cpu_regs[R_ECX]);
- gen_helper_rdpkru(s->tmp1_i64, cpu_env, s->tmp2_i32);
+ gen_helper_rdpkru(s->tmp1_i64, tcg_env, s->tmp2_i32);
tcg_gen_extr_i64_tl(cpu_regs[R_EAX], cpu_regs[R_EDX], s->tmp1_i64);
break;
case 0xef: /* wrpkru */
tcg_gen_concat_tl_i64(s->tmp1_i64, cpu_regs[R_EAX],
cpu_regs[R_EDX]);
tcg_gen_trunc_tl_i32(s->tmp2_i32, cpu_regs[R_ECX]);
- gen_helper_wrpkru(cpu_env, s->tmp2_i32, s->tmp1_i64);
+ gen_helper_wrpkru(tcg_env, s->tmp2_i32, s->tmp1_i64);
break;
CASE_MODRM_OP(6): /* lmsw */
* Only the 4 lower bits of CR0 are modified.
* PE cannot be set to zero if already set to one.
*/
- tcg_gen_ld_tl(s->T1, cpu_env, offsetof(CPUX86State, cr[0]));
+ tcg_gen_ld_tl(s->T1, tcg_env, offsetof(CPUX86State, cr[0]));
tcg_gen_andi_tl(s->T0, s->T0, 0xf);
tcg_gen_andi_tl(s->T1, s->T1, ~0xe);
tcg_gen_or_tl(s->T0, s->T0, s->T1);
- gen_helper_write_crN(cpu_env, tcg_constant_i32(0), s->T0);
+ gen_helper_write_crN(tcg_env, tcg_constant_i32(0), s->T0);
s->base.is_jmp = DISAS_EOB_NEXT;
break;
}
gen_svm_check_intercept(s, SVM_EXIT_INVLPG);
gen_lea_modrm(env, s, modrm);
- gen_helper_flush_page(cpu_env, s->A0);
+ gen_helper_flush_page(tcg_env, s->A0);
s->base.is_jmp = DISAS_EOB_NEXT;
break;
if (CODE64(s)) {
if (check_cpl0(s)) {
tcg_gen_mov_tl(s->T0, cpu_seg_base[R_GS]);
- tcg_gen_ld_tl(cpu_seg_base[R_GS], cpu_env,
+ tcg_gen_ld_tl(cpu_seg_base[R_GS], tcg_env,
offsetof(CPUX86State, kernelgsbase));
- tcg_gen_st_tl(s->T0, cpu_env,
+ tcg_gen_st_tl(s->T0, tcg_env,
offsetof(CPUX86State, kernelgsbase));
}
break;
gen_update_cc_op(s);
gen_update_eip_cur(s);
translator_io_start(&s->base);
- gen_helper_rdtsc(cpu_env);
- gen_helper_rdpid(s->T0, cpu_env);
+ gen_helper_rdtsc(tcg_env);
+ gen_helper_rdpid(s->T0, tcg_env);
gen_op_mov_reg_v(s, dflag, R_ECX, s->T0);
break;
t0 = tcg_temp_new();
gen_update_cc_op(s);
if (b == 0x102) {
- gen_helper_lar(t0, cpu_env, s->T0);
+ gen_helper_lar(t0, tcg_env, s->T0);
} else {
- gen_helper_lsl(t0, cpu_env, s->T0);
+ gen_helper_lsl(t0, tcg_env, s->T0);
}
tcg_gen_andi_tl(s->tmp0, cpu_cc_src, CC_Z);
label1 = gen_new_label();
tcg_gen_movi_tl(s->T0, 0);
}
if (CODE64(s)) {
- gen_helper_bndldx64(cpu_bndl[reg], cpu_env, s->A0, s->T0);
- tcg_gen_ld_i64(cpu_bndu[reg], cpu_env,
+ gen_helper_bndldx64(cpu_bndl[reg], tcg_env, s->A0, s->T0);
+ tcg_gen_ld_i64(cpu_bndu[reg], tcg_env,
offsetof(CPUX86State, mmx_t0.MMX_Q(0)));
} else {
- gen_helper_bndldx32(cpu_bndu[reg], cpu_env, s->A0, s->T0);
+ gen_helper_bndldx32(cpu_bndu[reg], tcg_env, s->A0, s->T0);
tcg_gen_ext32u_i64(cpu_bndl[reg], cpu_bndu[reg]);
tcg_gen_shri_i64(cpu_bndu[reg], cpu_bndu[reg], 32);
}
tcg_gen_movi_tl(s->T0, 0);
}
if (CODE64(s)) {
- gen_helper_bndstx64(cpu_env, s->A0, s->T0,
+ gen_helper_bndstx64(tcg_env, s->A0, s->T0,
cpu_bndl[reg], cpu_bndu[reg]);
} else {
- gen_helper_bndstx32(cpu_env, s->A0, s->T0,
+ gen_helper_bndstx32(tcg_env, s->A0, s->T0,
cpu_bndl[reg], cpu_bndu[reg]);
}
}
if (b & 2) {
gen_svm_check_intercept(s, SVM_EXIT_WRITE_CR0 + reg);
gen_op_mov_v_reg(s, ot, s->T0, rm);
- gen_helper_write_crN(cpu_env, tcg_constant_i32(reg), s->T0);
+ gen_helper_write_crN(tcg_env, tcg_constant_i32(reg), s->T0);
s->base.is_jmp = DISAS_EOB_NEXT;
} else {
gen_svm_check_intercept(s, SVM_EXIT_READ_CR0 + reg);
- gen_helper_read_crN(s->T0, cpu_env, tcg_constant_i32(reg));
+ gen_helper_read_crN(s->T0, tcg_env, tcg_constant_i32(reg));
gen_op_mov_reg_v(s, ot, rm, s->T0);
}
break;
gen_svm_check_intercept(s, SVM_EXIT_WRITE_DR0 + reg);
gen_op_mov_v_reg(s, ot, s->T0, rm);
tcg_gen_movi_i32(s->tmp2_i32, reg);
- gen_helper_set_dr(cpu_env, s->tmp2_i32, s->T0);
+ gen_helper_set_dr(tcg_env, s->tmp2_i32, s->T0);
s->base.is_jmp = DISAS_EOB_NEXT;
} else {
gen_svm_check_intercept(s, SVM_EXIT_READ_DR0 + reg);
tcg_gen_movi_i32(s->tmp2_i32, reg);
- gen_helper_get_dr(s->T0, cpu_env, s->tmp2_i32);
+ gen_helper_get_dr(s->T0, tcg_env, s->tmp2_i32);
gen_op_mov_reg_v(s, ot, rm, s->T0);
}
}
case 0x106: /* clts */
if (check_cpl0(s)) {
gen_svm_check_intercept(s, SVM_EXIT_WRITE_CR0);
- gen_helper_clts(cpu_env);
+ gen_helper_clts(tcg_env);
/* abort block because static cpu state changed */
s->base.is_jmp = DISAS_EOB_NEXT;
}
break;
}
gen_lea_modrm(env, s, modrm);
- gen_helper_fxsave(cpu_env, s->A0);
+ gen_helper_fxsave(tcg_env, s->A0);
break;
CASE_MODRM_MEM_OP(1): /* fxrstor */
break;
}
gen_lea_modrm(env, s, modrm);
- gen_helper_fxrstor(cpu_env, s->A0);
+ gen_helper_fxrstor(tcg_env, s->A0);
break;
CASE_MODRM_MEM_OP(2): /* ldmxcsr */
}
gen_lea_modrm(env, s, modrm);
tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, s->mem_index, MO_LEUL);
- gen_helper_ldmxcsr(cpu_env, s->tmp2_i32);
+ gen_helper_ldmxcsr(tcg_env, s->tmp2_i32);
break;
CASE_MODRM_MEM_OP(3): /* stmxcsr */
gen_exception(s, EXCP07_PREX);
break;
}
- gen_helper_update_mxcsr(cpu_env);
+ gen_helper_update_mxcsr(tcg_env);
gen_lea_modrm(env, s, modrm);
- tcg_gen_ld32u_tl(s->T0, cpu_env, offsetof(CPUX86State, mxcsr));
+ tcg_gen_ld32u_tl(s->T0, tcg_env, offsetof(CPUX86State, mxcsr));
gen_op_st_v(s, MO_32, s->T0, s->A0);
break;
gen_lea_modrm(env, s, modrm);
tcg_gen_concat_tl_i64(s->tmp1_i64, cpu_regs[R_EAX],
cpu_regs[R_EDX]);
- gen_helper_xsave(cpu_env, s->A0, s->tmp1_i64);
+ gen_helper_xsave(tcg_env, s->A0, s->tmp1_i64);
break;
CASE_MODRM_MEM_OP(5): /* xrstor */
gen_lea_modrm(env, s, modrm);
tcg_gen_concat_tl_i64(s->tmp1_i64, cpu_regs[R_EAX],
cpu_regs[R_EDX]);
- gen_helper_xrstor(cpu_env, s->A0, s->tmp1_i64);
+ gen_helper_xrstor(tcg_env, s->A0, s->tmp1_i64);
/* XRSTOR is how MPX is enabled, which changes how
we translate. Thus we need to end the TB. */
s->base.is_jmp = DISAS_EOB_NEXT;
gen_lea_modrm(env, s, modrm);
tcg_gen_concat_tl_i64(s->tmp1_i64, cpu_regs[R_EAX],
cpu_regs[R_EDX]);
- gen_helper_xsaveopt(cpu_env, s->A0, s->tmp1_i64);
+ gen_helper_xsaveopt(tcg_env, s->A0, s->tmp1_i64);
}
break;
/* Preserve hflags bits by testing CR4 at runtime. */
tcg_gen_movi_i32(s->tmp2_i32, CR4_FSGSBASE_MASK);
- gen_helper_cr4_testbit(cpu_env, s->tmp2_i32);
+ gen_helper_cr4_testbit(tcg_env, s->tmp2_i32);
base = cpu_seg_base[modrm & 8 ? R_GS : R_FS];
treg = cpu_regs[(modrm & 7) | REX_B(s)];
#else
gen_update_cc_op(s);
gen_update_eip_next(s);
- gen_helper_rsm(cpu_env);
+ gen_helper_rsm(tcg_env);
#endif /* CONFIG_USER_ONLY */
s->base.is_jmp = DISAS_EOB_ONLY;
break;
};
int i;
- cpu_cc_op = tcg_global_mem_new_i32(cpu_env,
+ cpu_cc_op = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUX86State, cc_op), "cc_op");
- cpu_cc_dst = tcg_global_mem_new(cpu_env, offsetof(CPUX86State, cc_dst),
+ cpu_cc_dst = tcg_global_mem_new(tcg_env, offsetof(CPUX86State, cc_dst),
"cc_dst");
- cpu_cc_src = tcg_global_mem_new(cpu_env, offsetof(CPUX86State, cc_src),
+ cpu_cc_src = tcg_global_mem_new(tcg_env, offsetof(CPUX86State, cc_src),
"cc_src");
- cpu_cc_src2 = tcg_global_mem_new(cpu_env, offsetof(CPUX86State, cc_src2),
+ cpu_cc_src2 = tcg_global_mem_new(tcg_env, offsetof(CPUX86State, cc_src2),
"cc_src2");
- cpu_eip = tcg_global_mem_new(cpu_env, offsetof(CPUX86State, eip), eip_name);
+ cpu_eip = tcg_global_mem_new(tcg_env, offsetof(CPUX86State, eip), eip_name);
for (i = 0; i < CPU_NB_REGS; ++i) {
- cpu_regs[i] = tcg_global_mem_new(cpu_env,
+ cpu_regs[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUX86State, regs[i]),
reg_names[i]);
}
for (i = 0; i < 6; ++i) {
cpu_seg_base[i]
- = tcg_global_mem_new(cpu_env,
+ = tcg_global_mem_new(tcg_env,
offsetof(CPUX86State, segs[i].base),
seg_base_names[i]);
}
for (i = 0; i < 4; ++i) {
cpu_bndl[i]
- = tcg_global_mem_new_i64(cpu_env,
+ = tcg_global_mem_new_i64(tcg_env,
offsetof(CPUX86State, bnd_regs[i].lb),
bnd_regl_names[i]);
cpu_bndu[i]
- = tcg_global_mem_new_i64(cpu_env,
+ = tcg_global_mem_new_i64(tcg_env,
offsetof(CPUX86State, bnd_regs[i].ub),
bnd_regu_names[i]);
}
TCGv t0 = make_address_i(ctx, src1, a->imm);
tcg_gen_qemu_ld_i64(dest, t0, ctx->mem_idx, mop);
- tcg_gen_st_tl(t0, cpu_env, offsetof(CPULoongArchState, lladdr));
- tcg_gen_st_tl(dest, cpu_env, offsetof(CPULoongArchState, llval));
+ tcg_gen_st_tl(t0, tcg_env, offsetof(CPULoongArchState, lladdr));
+ tcg_gen_st_tl(dest, tcg_env, offsetof(CPULoongArchState, llval));
gen_set_gpr(a->rd, dest, EXT_NONE);
return true;
TCGv src1 = tcg_temp_new();
TCGv src2 = tcg_constant_tl(0);
- tcg_gen_ld8u_tl(src1, cpu_env,
+ tcg_gen_ld8u_tl(src1, tcg_env,
offsetof(CPULoongArchState, cf[a->cj]));
gen_bc(ctx, src1, src2, a->offs, cond);
return true;
return false;
}
- gen_helper_asrtle_d(cpu_env, src1, src2);
+ gen_helper_asrtle_d(tcg_env, src1, src2);
return true;
}
return false;
}
- gen_helper_asrtgt_d(cpu_env, src1, src2);
+ gen_helper_asrtgt_d(tcg_env, src1, src2);
return true;
}
TCGv dst2 = gpr_dst(ctx, a->rj, EXT_NONE);
translator_io_start(&ctx->base);
- gen_helper_rdtime_d(dst1, cpu_env);
+ gen_helper_rdtime_d(dst1, tcg_env);
if (word) {
tcg_gen_sextract_tl(dst1, dst1, high ? 32 : 0, 32);
}
- tcg_gen_ld_i64(dst2, cpu_env, offsetof(CPULoongArchState, CSR_TID));
+ tcg_gen_ld_i64(dst2, tcg_env, offsetof(CPULoongArchState, CSR_TID));
return true;
}
TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
- gen_helper_cpucfg(dest, cpu_env, src1);
+ gen_helper_cpucfg(dest, tcg_env, src1);
gen_set_gpr(a->rd, dest, EXT_NONE);
return true;
CHECK_FPE;
- func(dest, cpu_env, src1, src2);
+ func(dest, tcg_env, src1, src2);
set_fpr(a->fd, dest);
return true;
CHECK_FPE;
- func(dest, cpu_env, src);
+ func(dest, tcg_env, src);
set_fpr(a->fd, dest);
return true;
CHECK_FPE;
- func(dest, cpu_env, src1, src2, src3, tflag);
+ func(dest, tcg_env, src1, src2, src3, tflag);
set_fpr(a->fd, dest);
return true;
fn = (a->fcond & 1 ? gen_helper_fcmp_s_s : gen_helper_fcmp_c_s);
flags = get_fcmp_flags(a->fcond >> 1);
- fn(var, cpu_env, src1, src2, tcg_constant_i32(flags));
+ fn(var, tcg_env, src1, src2, tcg_constant_i32(flags));
- tcg_gen_st8_tl(var, cpu_env, offsetof(CPULoongArchState, cf[a->cd]));
+ tcg_gen_st8_tl(var, tcg_env, offsetof(CPULoongArchState, cf[a->cd]));
return true;
}
fn = (a->fcond & 1 ? gen_helper_fcmp_s_d : gen_helper_fcmp_c_d);
flags = get_fcmp_flags(a->fcond >> 1);
- fn(var, cpu_env, src1, src2, tcg_constant_i32(flags));
+ fn(var, tcg_env, src1, src2, tcg_constant_i32(flags));
- tcg_gen_st8_tl(var, cpu_env, offsetof(CPULoongArchState, cf[a->cd]));
+ tcg_gen_st8_tl(var, tcg_env, offsetof(CPULoongArchState, cf[a->cd]));
return true;
}
CHECK_FPE;
- gen_helper_asrtgt_d(cpu_env, src1, src2);
+ gen_helper_asrtgt_d(tcg_env, src1, src2);
addr = make_address_x(ctx, src1, src2);
tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop);
maybe_nanbox_load(dest, mop);
CHECK_FPE;
- gen_helper_asrtgt_d(cpu_env, src1, src2);
+ gen_helper_asrtgt_d(tcg_env, src1, src2);
addr = make_address_x(ctx, src1, src2);
tcg_gen_qemu_st_tl(src3, addr, ctx->mem_idx, mop);
CHECK_FPE;
- gen_helper_asrtle_d(cpu_env, src1, src2);
+ gen_helper_asrtle_d(tcg_env, src1, src2);
addr = make_address_x(ctx, src1, src2);
tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop);
maybe_nanbox_load(dest, mop);
CHECK_FPE;
- gen_helper_asrtle_d(cpu_env, src1, src2);
+ gen_helper_asrtle_d(tcg_env, src1, src2);
addr = make_address_x(ctx, src1, src2);
tcg_gen_qemu_st_tl(src3, addr, ctx->mem_idx, mop);
CHECK_FPE;
cond = tcg_temp_new();
- tcg_gen_ld8u_tl(cond, cpu_env, offsetof(CPULoongArchState, cf[a->ca]));
+ tcg_gen_ld8u_tl(cond, tcg_env, offsetof(CPULoongArchState, cf[a->ca]));
tcg_gen_movcond_tl(TCG_COND_EQ, dest, cond, zero, src1, src2);
set_fpr(a->fd, dest);
CHECK_FPE;
if (mask == UINT32_MAX) {
- tcg_gen_st32_i64(Rj, cpu_env, offsetof(CPULoongArchState, fcsr0));
+ tcg_gen_st32_i64(Rj, tcg_env, offsetof(CPULoongArchState, fcsr0));
} else {
TCGv_i32 fcsr0 = tcg_temp_new_i32();
TCGv_i32 temp = tcg_temp_new_i32();
- tcg_gen_ld_i32(fcsr0, cpu_env, offsetof(CPULoongArchState, fcsr0));
+ tcg_gen_ld_i32(fcsr0, tcg_env, offsetof(CPULoongArchState, fcsr0));
tcg_gen_extrl_i64_i32(temp, Rj);
tcg_gen_andi_i32(temp, temp, mask);
tcg_gen_andi_i32(fcsr0, fcsr0, ~mask);
tcg_gen_or_i32(fcsr0, fcsr0, temp);
- tcg_gen_st_i32(fcsr0, cpu_env, offsetof(CPULoongArchState, fcsr0));
+ tcg_gen_st_i32(fcsr0, tcg_env, offsetof(CPULoongArchState, fcsr0));
}
/*
* Note that FCSR3 is exactly the rounding mode field.
*/
if (mask & FCSR0_M3) {
- gen_helper_set_rounding_mode(cpu_env);
+ gen_helper_set_rounding_mode(tcg_env);
}
return true;
}
CHECK_FPE;
- tcg_gen_ld32u_i64(dest, cpu_env, offsetof(CPULoongArchState, fcsr0));
+ tcg_gen_ld32u_i64(dest, tcg_env, offsetof(CPULoongArchState, fcsr0));
tcg_gen_andi_i64(dest, dest, fcsr_mask[a->fcsrs]);
gen_set_gpr(a->rd, dest, EXT_NONE);
t0 = tcg_temp_new();
tcg_gen_andi_tl(t0, src, 0x1);
- tcg_gen_st8_tl(t0, cpu_env, offsetof(CPULoongArchState, cf[a->cd & 0x7]));
+ tcg_gen_st8_tl(t0, tcg_env, offsetof(CPULoongArchState, cf[a->cd & 0x7]));
return true;
}
CHECK_FPE;
- tcg_gen_ld8u_tl(dest, cpu_env,
+ tcg_gen_ld8u_tl(dest, tcg_env,
offsetof(CPULoongArchState, cf[a->cj & 0x7]));
set_fpr(a->fd, dest);
t0 = tcg_temp_new();
tcg_gen_andi_tl(t0, gpr_src(ctx, a->rj, EXT_NONE), 0x1);
- tcg_gen_st8_tl(t0, cpu_env, offsetof(CPULoongArchState, cf[a->cd & 0x7]));
+ tcg_gen_st8_tl(t0, tcg_env, offsetof(CPULoongArchState, cf[a->cd & 0x7]));
return true;
}
CHECK_FPE;
- tcg_gen_ld8u_tl(gpr_dst(ctx, a->rd, EXT_NONE), cpu_env,
+ tcg_gen_ld8u_tl(gpr_dst(ctx, a->rd, EXT_NONE), tcg_env,
offsetof(CPULoongArchState, cf[a->cj & 0x7]));
return true;
}
TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
- gen_helper_asrtgt_d(cpu_env, src1, src2);
+ gen_helper_asrtgt_d(tcg_env, src1, src2);
src1 = make_address_i(ctx, src1, 0);
tcg_gen_qemu_ld_tl(dest, src1, ctx->mem_idx, mop);
gen_set_gpr(a->rd, dest, EXT_NONE);
TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
- gen_helper_asrtle_d(cpu_env, src1, src2);
+ gen_helper_asrtle_d(tcg_env, src1, src2);
src1 = make_address_i(ctx, src1, 0);
tcg_gen_qemu_ld_tl(dest, src1, ctx->mem_idx, mop);
gen_set_gpr(a->rd, dest, EXT_NONE);
TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
- gen_helper_asrtgt_d(cpu_env, src1, src2);
+ gen_helper_asrtgt_d(tcg_env, src1, src2);
src1 = make_address_i(ctx, src1, 0);
tcg_gen_qemu_st_tl(data, src1, ctx->mem_idx, mop);
TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
- gen_helper_asrtle_d(cpu_env, src1, src2);
+ gen_helper_asrtle_d(tcg_env, src1, src2);
src1 = make_address_i(ctx, src1, 0);
tcg_gen_qemu_st_tl(data, src1, ctx->mem_idx, mop);
check_csr_flags(ctx, csr, false);
dest = gpr_dst(ctx, a->rd, EXT_NONE);
if (csr->readfn) {
- csr->readfn(dest, cpu_env);
+ csr->readfn(dest, tcg_env);
} else {
- tcg_gen_ld_tl(dest, cpu_env, csr->offset);
+ tcg_gen_ld_tl(dest, tcg_env, csr->offset);
}
}
gen_set_gpr(a->rd, dest, EXT_NONE);
src1 = gpr_src(ctx, a->rd, EXT_NONE);
if (csr->writefn) {
dest = gpr_dst(ctx, a->rd, EXT_NONE);
- csr->writefn(dest, cpu_env, src1);
+ csr->writefn(dest, tcg_env, src1);
} else {
dest = tcg_temp_new();
- tcg_gen_ld_tl(dest, cpu_env, csr->offset);
- tcg_gen_st_tl(src1, cpu_env, csr->offset);
+ tcg_gen_ld_tl(dest, tcg_env, csr->offset);
+ tcg_gen_st_tl(src1, tcg_env, csr->offset);
}
gen_set_gpr(a->rd, dest, EXT_NONE);
return true;
newv = tcg_temp_new();
temp = tcg_temp_new();
- tcg_gen_ld_tl(oldv, cpu_env, csr->offset);
+ tcg_gen_ld_tl(oldv, tcg_env, csr->offset);
tcg_gen_and_tl(newv, src1, mask);
tcg_gen_andc_tl(temp, oldv, mask);
tcg_gen_or_tl(newv, newv, temp);
if (csr->writefn) {
- csr->writefn(oldv, cpu_env, newv);
+ csr->writefn(oldv, tcg_env, newv);
} else {
- tcg_gen_st_tl(newv, cpu_env, csr->offset);
+ tcg_gen_st_tl(newv, tcg_env, csr->offset);
}
gen_set_gpr(a->rd, oldv, EXT_NONE);
return true;
if (check_plv(ctx)) {
return false;
}
- func(dest, cpu_env, src1);
+ func(dest, tcg_env, src1);
return true;
}
if (check_plv(ctx)) {
return false;
}
- func(cpu_env, addr, val);
+ func(tcg_env, addr, val);
return true;
}
if (check_plv(ctx)) {
return false;
}
- gen_helper_tlbsrch(cpu_env);
+ gen_helper_tlbsrch(tcg_env);
return true;
}
if (check_plv(ctx)) {
return false;
}
- gen_helper_tlbrd(cpu_env);
+ gen_helper_tlbrd(tcg_env);
return true;
}
if (check_plv(ctx)) {
return false;
}
- gen_helper_tlbwr(cpu_env);
+ gen_helper_tlbwr(tcg_env);
check_mmu_idx(ctx);
return true;
}
if (check_plv(ctx)) {
return false;
}
- gen_helper_tlbfill(cpu_env);
+ gen_helper_tlbfill(tcg_env);
check_mmu_idx(ctx);
return true;
}
if (check_plv(ctx)) {
return false;
}
- gen_helper_tlbclr(cpu_env);
+ gen_helper_tlbclr(tcg_env);
check_mmu_idx(ctx);
return true;
}
if (check_plv(ctx)) {
return false;
}
- gen_helper_tlbflush(cpu_env);
+ gen_helper_tlbflush(tcg_env);
check_mmu_idx(ctx);
return true;
}
switch (a->imm) {
case 0:
case 1:
- gen_helper_invtlb_all(cpu_env);
+ gen_helper_invtlb_all(tcg_env);
break;
case 2:
- gen_helper_invtlb_all_g(cpu_env, tcg_constant_i32(1));
+ gen_helper_invtlb_all_g(tcg_env, tcg_constant_i32(1));
break;
case 3:
- gen_helper_invtlb_all_g(cpu_env, tcg_constant_i32(0));
+ gen_helper_invtlb_all_g(tcg_env, tcg_constant_i32(0));
break;
case 4:
- gen_helper_invtlb_all_asid(cpu_env, rj);
+ gen_helper_invtlb_all_asid(tcg_env, rj);
break;
case 5:
- gen_helper_invtlb_page_asid(cpu_env, rj, rk);
+ gen_helper_invtlb_page_asid(tcg_env, rj, rk);
break;
case 6:
- gen_helper_invtlb_page_asid_or_g(cpu_env, rj, rk);
+ gen_helper_invtlb_page_asid_or_g(tcg_env, rj, rk);
break;
default:
return false;
if (check_plv(ctx)) {
return false;
}
- gen_helper_ldpte(cpu_env, src1, tcg_constant_tl(a->imm), mem_idx);
+ gen_helper_ldpte(tcg_env, src1, tcg_constant_tl(a->imm), mem_idx);
return true;
}
if (check_plv(ctx)) {
return false;
}
- gen_helper_lddir(dest, cpu_env, src, tcg_constant_tl(a->imm), mem_idx);
+ gen_helper_lddir(dest, tcg_env, src, tcg_constant_tl(a->imm), mem_idx);
return true;
}
if (check_plv(ctx)) {
return false;
}
- gen_helper_ertn(cpu_env);
+ gen_helper_ertn(tcg_env);
ctx->base.is_jmp = DISAS_EXIT;
return true;
}
}
tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next + 4);
- gen_helper_idle(cpu_env);
+ gen_helper_idle(tcg_env);
ctx->base.is_jmp = DISAS_NORETURN;
return true;
}
vec_full_offset(a->vj),
vec_full_offset(a->vk),
vec_full_offset(a->va),
- cpu_env,
+ tcg_env,
oprsz, ctx->vl / 8, 0, fn);
return true;
}
tcg_gen_gvec_3_ptr(vec_full_offset(a->vd),
vec_full_offset(a->vj),
vec_full_offset(a->vk),
- cpu_env,
+ tcg_env,
oprsz, ctx->vl / 8, 0, fn);
return true;
}
tcg_gen_gvec_2_ptr(vec_full_offset(a->vd),
vec_full_offset(a->vj),
- cpu_env,
+ tcg_env,
oprsz, ctx->vl / 8, 0, fn);
return true;
}
TCGv_i32 cd = tcg_constant_i32(a->cd);
TCGv_i32 oprsz = tcg_constant_i32(sz);
- func(cpu_env, oprsz, cd, vj);
+ func(tcg_env, oprsz, cd, vj);
return true;
}
fn = (a->fcond & 1 ? gen_helper_vfcmp_s_s : gen_helper_vfcmp_c_s);
flags = get_fcmp_flags(a->fcond >> 1);
- fn(cpu_env, oprsz, vd, vj, vk, tcg_constant_i32(flags));
+ fn(tcg_env, oprsz, vd, vj, vk, tcg_constant_i32(flags));
return true;
}
fn = (a->fcond & 1 ? gen_helper_vfcmp_s_d : gen_helper_vfcmp_c_d);
flags = get_fcmp_flags(a->fcond >> 1);
- fn(cpu_env, oprsz, vd, vj, vk, tcg_constant_i32(flags));
+ fn(tcg_env, oprsz, vd, vj, vk, tcg_constant_i32(flags));
return true;
}
\
tcg_gen_or_i64(t1, al, ah); \
tcg_gen_setcondi_i64(COND, t1, t1, 0); \
- tcg_gen_st8_tl(t1, cpu_env, offsetof(CPULoongArchState, cf[a->cd & 0x7])); \
+ tcg_gen_st8_tl(t1, tcg_env, offsetof(CPULoongArchState, cf[a->cd & 0x7])); \
\
return true; \
}
tcg_gen_or_i64(t2, d[2], d[3]); \
tcg_gen_or_i64(t1, t2, t1); \
tcg_gen_setcondi_i64(COND, t1, t1, 0); \
- tcg_gen_st8_tl(t1, cpu_env, offsetof(CPULoongArchState, cf[a->cd & 0x7])); \
+ tcg_gen_st8_tl(t1, tcg_env, offsetof(CPULoongArchState, cf[a->cd & 0x7])); \
\
return true; \
}
return true;
}
- func(src, cpu_env, vec_reg_offset(a->vd, a->imm, mop));
+ func(src, tcg_env, vec_reg_offset(a->vd, a->imm, mop));
return true;
}
return true;
}
- func(dst, cpu_env, vec_reg_offset(a->vj, a->imm, mop));
+ func(dst, tcg_env, vec_reg_offset(a->vj, a->imm, mop));
return true;
}
}
tcg_gen_trunc_i64_ptr(t1, t0);
- tcg_gen_add_ptr(t1, t1, cpu_env);
+ tcg_gen_add_ptr(t1, t1, tcg_env);
for (i = 0; i < oprsz; i += 16) {
func(t2, t1, vec_full_offset(a->vj) + i);
val = tcg_temp_new_i64();
addr = make_address_i(ctx, addr, a->imm);
- tcg_gen_ld_i64(val, cpu_env, vec_reg_offset(a->vd, a->imm2, mop));
+ tcg_gen_ld_i64(val, tcg_env, vec_reg_offset(a->vd, a->imm2, mop));
tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, mop);
return true;
}
static inline void get_vreg64(TCGv_i64 dest, int regno, int index)
{
- tcg_gen_ld_i64(dest, cpu_env,
+ tcg_gen_ld_i64(dest, tcg_env,
offsetof(CPULoongArchState, fpr[regno].vreg.D(index)));
}
static inline void set_vreg64(TCGv_i64 src, int regno, int index)
{
- tcg_gen_st_i64(src, cpu_env,
+ tcg_gen_st_i64(src, tcg_env,
offsetof(CPULoongArchState, fpr[regno].vreg.D(index)));
}
void generate_exception(DisasContext *ctx, int excp)
{
tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
- gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
+ gen_helper_raise_exception(tcg_env, tcg_constant_i32(excp));
ctx->base.is_jmp = DISAS_NORETURN;
}
static TCGv get_fpr(DisasContext *ctx, int reg_num)
{
TCGv t = tcg_temp_new();
- tcg_gen_ld_i64(t, cpu_env,
+ tcg_gen_ld_i64(t, tcg_env,
offsetof(CPULoongArchState, fpr[reg_num].vreg.D(0)));
return t;
}
static void set_fpr(int reg_num, TCGv val)
{
- tcg_gen_st_i64(val, cpu_env,
+ tcg_gen_st_i64(val, tcg_env,
offsetof(CPULoongArchState, fpr[reg_num].vreg.D(0)));
}
cpu_gpr[0] = NULL;
for (i = 1; i < 32; i++) {
- cpu_gpr[i] = tcg_global_mem_new(cpu_env,
+ cpu_gpr[i] = tcg_global_mem_new(tcg_env,
offsetof(CPULoongArchState, gpr[i]),
regnames[i]);
}
- cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPULoongArchState, pc), "pc");
- cpu_lladdr = tcg_global_mem_new(cpu_env,
+ cpu_pc = tcg_global_mem_new(tcg_env, offsetof(CPULoongArchState, pc), "pc");
+ cpu_lladdr = tcg_global_mem_new(tcg_env,
offsetof(CPULoongArchState, lladdr), "lladdr");
- cpu_llval = tcg_global_mem_new(cpu_env,
+ cpu_llval = tcg_global_mem_new(tcg_env,
offsetof(CPULoongArchState, llval), "llval");
}
int i;
#define DEFO32(name, offset) \
- QREG_##name = tcg_global_mem_new_i32(cpu_env, \
+ QREG_##name = tcg_global_mem_new_i32(tcg_env, \
offsetof(CPUM68KState, offset), #name);
#define DEFO64(name, offset) \
- QREG_##name = tcg_global_mem_new_i64(cpu_env, \
+ QREG_##name = tcg_global_mem_new_i64(tcg_env, \
offsetof(CPUM68KState, offset), #name);
#include "qregs.h.inc"
#undef DEFO32
#undef DEFO64
- cpu_halted = tcg_global_mem_new_i32(cpu_env,
+ cpu_halted = tcg_global_mem_new_i32(tcg_env,
-offsetof(M68kCPU, env) +
offsetof(CPUState, halted), "HALTED");
- cpu_exception_index = tcg_global_mem_new_i32(cpu_env,
+ cpu_exception_index = tcg_global_mem_new_i32(tcg_env,
-offsetof(M68kCPU, env) +
offsetof(CPUState, exception_index),
"EXCEPTION");
p = cpu_reg_names;
for (i = 0; i < 8; i++) {
sprintf(p, "D%d", i);
- cpu_dregs[i] = tcg_global_mem_new(cpu_env,
+ cpu_dregs[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUM68KState, dregs[i]), p);
p += 3;
sprintf(p, "A%d", i);
- cpu_aregs[i] = tcg_global_mem_new(cpu_env,
+ cpu_aregs[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUM68KState, aregs[i]), p);
p += 3;
}
for (i = 0; i < 4; i++) {
sprintf(p, "ACC%d", i);
- cpu_macc[i] = tcg_global_mem_new_i64(cpu_env,
+ cpu_macc[i] = tcg_global_mem_new_i64(tcg_env,
offsetof(CPUM68KState, macc[i]), p);
p += 5;
}
- NULL_QREG = tcg_global_mem_new(cpu_env, -4, "NULL");
- store_dummy = tcg_global_mem_new(cpu_env, -8, "NULL");
+ NULL_QREG = tcg_global_mem_new(tcg_env, -4, "NULL");
+ store_dummy = tcg_global_mem_new(tcg_env, -8, "NULL");
}
/* internal defines */
static void gen_raise_exception(int nr)
{
- gen_helper_raise_exception(cpu_env, tcg_constant_i32(nr));
+ gen_helper_raise_exception(tcg_env, tcg_constant_i32(nr));
}
static void gen_raise_exception_format2(DisasContext *s, int nr,
* Re-use mmu.ar for the purpose, since that's only valid
* after tlb_fill.
*/
- tcg_gen_st_i32(tcg_constant_i32(this_pc), cpu_env,
+ tcg_gen_st_i32(tcg_constant_i32(this_pc), tcg_env,
offsetof(CPUM68KState, mmu.ar));
gen_raise_exception(nr);
s->base.is_jmp = DISAS_NORETURN;
break;
case CC_OP_DYNAMIC:
- gen_helper_flush_flags(cpu_env, QREG_CC_OP);
+ gen_helper_flush_flags(tcg_env, QREG_CC_OP);
s->cc_op_synced = 1;
break;
default:
- gen_helper_flush_flags(cpu_env, tcg_constant_i32(s->cc_op));
+ gen_helper_flush_flags(tcg_env, tcg_constant_i32(s->cc_op));
s->cc_op_synced = 1;
break;
}
static TCGv_ptr gen_fp_ptr(int freg)
{
TCGv_ptr fp = tcg_temp_new_ptr();
- tcg_gen_addi_ptr(fp, cpu_env, offsetof(CPUM68KState, fregs[freg]));
+ tcg_gen_addi_ptr(fp, tcg_env, offsetof(CPUM68KState, fregs[freg]));
return fp;
}
static TCGv_ptr gen_fp_result_ptr(void)
{
TCGv_ptr fp = tcg_temp_new_ptr();
- tcg_gen_addi_ptr(fp, cpu_env, offsetof(CPUM68KState, fp_result));
+ tcg_gen_addi_ptr(fp, tcg_env, offsetof(CPUM68KState, fp_result));
return fp;
}
case OS_WORD:
case OS_LONG:
tcg_gen_qemu_ld_tl(tmp, addr, index, opsize | MO_SIGN | MO_TE);
- gen_helper_exts32(cpu_env, fp, tmp);
+ gen_helper_exts32(tcg_env, fp, tmp);
break;
case OS_SINGLE:
tcg_gen_qemu_ld_tl(tmp, addr, index, MO_TEUL);
- gen_helper_extf32(cpu_env, fp, tmp);
+ gen_helper_extf32(tcg_env, fp, tmp);
break;
case OS_DOUBLE:
tcg_gen_qemu_ld_i64(t64, addr, index, MO_TEUQ);
- gen_helper_extf64(cpu_env, fp, t64);
+ gen_helper_extf64(tcg_env, fp, t64);
break;
case OS_EXTENDED:
if (m68k_feature(s->env, M68K_FEATURE_CF_FPU)) {
case OS_BYTE:
case OS_WORD:
case OS_LONG:
- gen_helper_reds32(tmp, cpu_env, fp);
+ gen_helper_reds32(tmp, tcg_env, fp);
tcg_gen_qemu_st_tl(tmp, addr, index, opsize | MO_TE);
break;
case OS_SINGLE:
- gen_helper_redf32(tmp, cpu_env, fp);
+ gen_helper_redf32(tmp, tcg_env, fp);
tcg_gen_qemu_st_tl(tmp, addr, index, MO_TEUL);
break;
case OS_DOUBLE:
- gen_helper_redf64(t64, cpu_env, fp);
+ gen_helper_redf64(t64, tcg_env, fp);
tcg_gen_qemu_st_i64(t64, addr, index, MO_TEUQ);
break;
case OS_EXTENDED:
case OS_BYTE:
case OS_WORD:
case OS_LONG:
- gen_helper_reds32(reg, cpu_env, fp);
+ gen_helper_reds32(reg, tcg_env, fp);
break;
case OS_SINGLE:
- gen_helper_redf32(reg, cpu_env, fp);
+ gen_helper_redf32(reg, tcg_env, fp);
break;
default:
g_assert_not_reached();
switch (opsize) {
case OS_BYTE:
tcg_gen_ext8s_i32(tmp, reg);
- gen_helper_exts32(cpu_env, fp, tmp);
+ gen_helper_exts32(tcg_env, fp, tmp);
break;
case OS_WORD:
tcg_gen_ext16s_i32(tmp, reg);
- gen_helper_exts32(cpu_env, fp, tmp);
+ gen_helper_exts32(tcg_env, fp, tmp);
break;
case OS_LONG:
- gen_helper_exts32(cpu_env, fp, reg);
+ gen_helper_exts32(tcg_env, fp, reg);
break;
case OS_SINGLE:
- gen_helper_extf32(cpu_env, fp, reg);
+ gen_helper_extf32(tcg_env, fp, reg);
break;
default:
g_assert_not_reached();
switch (opsize) {
case OS_BYTE:
tmp = tcg_constant_i32((int8_t)read_im8(env, s));
- gen_helper_exts32(cpu_env, fp, tmp);
+ gen_helper_exts32(tcg_env, fp, tmp);
break;
case OS_WORD:
tmp = tcg_constant_i32((int16_t)read_im16(env, s));
- gen_helper_exts32(cpu_env, fp, tmp);
+ gen_helper_exts32(tcg_env, fp, tmp);
break;
case OS_LONG:
tmp = tcg_constant_i32(read_im32(env, s));
- gen_helper_exts32(cpu_env, fp, tmp);
+ gen_helper_exts32(tcg_env, fp, tmp);
break;
case OS_SINGLE:
tmp = tcg_constant_i32(read_im32(env, s));
- gen_helper_extf32(cpu_env, fp, tmp);
+ gen_helper_extf32(tcg_env, fp, tmp);
break;
case OS_DOUBLE:
t64 = tcg_constant_i64(read_im64(env, s));
- gen_helper_extf64(cpu_env, fp, t64);
+ gen_helper_extf64(tcg_env, fp, t64);
break;
case OS_EXTENDED:
if (m68k_feature(s->env, M68K_FEATURE_CF_FPU)) {
destr = tcg_constant_i32(REG(insn, 9));
ilen = tcg_constant_i32(s->pc - s->base.pc_next);
if (sign) {
- gen_helper_divsw(cpu_env, destr, src, ilen);
+ gen_helper_divsw(tcg_env, destr, src, ilen);
} else {
- gen_helper_divuw(cpu_env, destr, src, ilen);
+ gen_helper_divuw(tcg_env, destr, src, ilen);
}
set_cc_op(s, CC_OP_FLAGS);
reg = tcg_constant_i32(REG(ext, 0));
ilen = tcg_constant_i32(s->pc - s->base.pc_next);
if (sign) {
- gen_helper_divsll(cpu_env, num, reg, den, ilen);
+ gen_helper_divsll(tcg_env, num, reg, den, ilen);
} else {
- gen_helper_divull(cpu_env, num, reg, den, ilen);
+ gen_helper_divull(tcg_env, num, reg, den, ilen);
}
set_cc_op(s, CC_OP_FLAGS);
return;
reg = tcg_constant_i32(REG(ext, 0));
ilen = tcg_constant_i32(s->pc - s->base.pc_next);
if (sign) {
- gen_helper_divsl(cpu_env, num, reg, den, ilen);
+ gen_helper_divsl(tcg_env, num, reg, den, ilen);
} else {
- gen_helper_divul(cpu_env, num, reg, den, ilen);
+ gen_helper_divul(tcg_env, num, reg, den, ilen);
}
set_cc_op(s, CC_OP_FLAGS);
update_cc_op(s);
dest = tcg_temp_new();
- gen_helper_get_ccr(dest, cpu_env);
+ gen_helper_get_ccr(dest, tcg_env);
return dest;
}
} else {
/* Must writeback before changing security state. */
do_writebacks(s);
- gen_helper_set_sr(cpu_env, tcg_constant_i32(val));
+ gen_helper_set_sr(tcg_env, tcg_constant_i32(val));
}
set_cc_op(s, CC_OP_FLAGS);
}
static void gen_set_sr(DisasContext *s, TCGv val, int ccr_only)
{
if (ccr_only) {
- gen_helper_set_ccr(cpu_env, val);
+ gen_helper_set_ccr(tcg_env, val);
} else {
/* Must writeback before changing security state. */
do_writebacks(s);
- gen_helper_set_sr(cpu_env, val);
+ gen_helper_set_sr(tcg_env, val);
}
set_cc_op(s, CC_OP_FLAGS);
}
*/
if (tb_cflags(s->base.tb) & CF_PARALLEL) {
- gen_helper_exit_atomic(cpu_env);
+ gen_helper_exit_atomic(tcg_env);
} else {
TCGv regs = tcg_constant_i32(REG(ext2, 6) |
(REG(ext1, 6) << 3) |
(REG(ext2, 0) << 6) |
(REG(ext1, 0) << 9));
- gen_helper_cas2w(cpu_env, regs, addr1, addr2);
+ gen_helper_cas2w(tcg_env, regs, addr1, addr2);
}
/* Note that cas2w also assigned to env->cc_op. */
(REG(ext2, 0) << 6) |
(REG(ext1, 0) << 9));
if (tb_cflags(s->base.tb) & CF_PARALLEL) {
- gen_helper_cas2l_parallel(cpu_env, regs, addr1, addr2);
+ gen_helper_cas2l_parallel(tcg_env, regs, addr1, addr2);
} else {
- gen_helper_cas2l(cpu_env, regs, addr1, addr2);
+ gen_helper_cas2l(tcg_env, regs, addr1, addr2);
}
/* Note that cas2l also assigned to env->cc_op. */
return;
}
- gen_helper_reset(cpu_env);
+ gen_helper_reset(tcg_env);
}
#endif
}
if (is_sign) {
- gen_helper_bfexts_mem(dest, cpu_env, addr, ofs, len);
+ gen_helper_bfexts_mem(dest, tcg_env, addr, ofs, len);
tcg_gen_mov_i32(QREG_CC_N, dest);
} else {
TCGv_i64 tmp = tcg_temp_new_i64();
- gen_helper_bfextu_mem(tmp, cpu_env, addr, ofs, len);
+ gen_helper_bfextu_mem(tmp, tcg_env, addr, ofs, len);
tcg_gen_extr_i64_i32(dest, QREG_CC_N, tmp);
}
set_cc_op(s, CC_OP_LOGIC);
switch (insn & 0x0f00) {
case 0x0a00: /* bfchg */
- gen_helper_bfchg_mem(QREG_CC_N, cpu_env, addr, ofs, len);
+ gen_helper_bfchg_mem(QREG_CC_N, tcg_env, addr, ofs, len);
break;
case 0x0c00: /* bfclr */
- gen_helper_bfclr_mem(QREG_CC_N, cpu_env, addr, ofs, len);
+ gen_helper_bfclr_mem(QREG_CC_N, tcg_env, addr, ofs, len);
break;
case 0x0d00: /* bfffo */
t64 = tcg_temp_new_i64();
- gen_helper_bfffo_mem(t64, cpu_env, addr, ofs, len);
+ gen_helper_bfffo_mem(t64, tcg_env, addr, ofs, len);
tcg_gen_extr_i64_i32(DREG(ext, 12), QREG_CC_N, t64);
break;
case 0x0e00: /* bfset */
- gen_helper_bfset_mem(QREG_CC_N, cpu_env, addr, ofs, len);
+ gen_helper_bfset_mem(QREG_CC_N, tcg_env, addr, ofs, len);
break;
case 0x0800: /* bftst */
- gen_helper_bfexts_mem(QREG_CC_N, cpu_env, addr, ofs, len);
+ gen_helper_bfexts_mem(QREG_CC_N, tcg_env, addr, ofs, len);
break;
default:
g_assert_not_reached();
ofs = tcg_constant_i32(extract32(ext, 6, 5));
}
- gen_helper_bfins_mem(QREG_CC_N, cpu_env, addr, src, ofs, len);
+ gen_helper_bfins_mem(QREG_CC_N, tcg_env, addr, src, ofs, len);
set_cc_op(s, CC_OP_LOGIC);
}
reg = gen_extend(s, DREG(insn, 9), opsize, 1);
gen_flush_flags(s);
- gen_helper_chk(cpu_env, reg, src);
+ gen_helper_chk(tcg_env, reg, src);
}
DISAS_INSN(chk2)
}
gen_flush_flags(s);
- gen_helper_chk2(cpu_env, reg, bound1, bound2);
+ gen_helper_chk2(tcg_env, reg, bound1, bound2);
}
static void m68k_copy_line(TCGv dst, TCGv src, int index)
gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
return;
}
- tcg_gen_ld_i32(AREG(insn, 0), cpu_env,
+ tcg_gen_ld_i32(AREG(insn, 0), tcg_env,
offsetof(CPUM68KState, sp[M68K_USP]));
}
gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
return;
}
- tcg_gen_st_i32(AREG(insn, 0), cpu_env,
+ tcg_gen_st_i32(AREG(insn, 0), tcg_env,
offsetof(CPUM68KState, sp[M68K_USP]));
}
} else {
reg = DREG(ext, 12);
}
- gen_helper_cf_movec_to(cpu_env, tcg_constant_i32(ext & 0xfff), reg);
+ gen_helper_cf_movec_to(tcg_env, tcg_constant_i32(ext & 0xfff), reg);
gen_exit_tb(s);
}
}
creg = tcg_constant_i32(ext & 0xfff);
if (insn & 1) {
- gen_helper_m68k_movec_to(cpu_env, creg, reg);
+ gen_helper_m68k_movec_to(tcg_env, creg, reg);
} else {
- gen_helper_m68k_movec_from(reg, cpu_env, creg);
+ gen_helper_m68k_movec_from(reg, tcg_env, creg);
}
gen_exit_tb(s);
}
}
opmode = tcg_constant_i32((insn >> 3) & 3);
- gen_helper_pflush(cpu_env, AREG(insn, 0), opmode);
+ gen_helper_pflush(tcg_env, AREG(insn, 0), opmode);
}
DISAS_INSN(ptest)
return;
}
is_read = tcg_constant_i32((insn >> 5) & 1);
- gen_helper_ptest(cpu_env, AREG(insn, 0), is_read);
+ gen_helper_ptest(tcg_env, AREG(insn, 0), is_read);
}
#endif
tcg_gen_movi_i32(res, 0);
break;
case M68K_FPSR:
- tcg_gen_ld_i32(res, cpu_env, offsetof(CPUM68KState, fpsr));
+ tcg_gen_ld_i32(res, tcg_env, offsetof(CPUM68KState, fpsr));
break;
case M68K_FPCR:
- tcg_gen_ld_i32(res, cpu_env, offsetof(CPUM68KState, fpcr));
+ tcg_gen_ld_i32(res, tcg_env, offsetof(CPUM68KState, fpcr));
break;
}
}
case M68K_FPIAR:
break;
case M68K_FPSR:
- tcg_gen_st_i32(val, cpu_env, offsetof(CPUM68KState, fpsr));
+ tcg_gen_st_i32(val, tcg_env, offsetof(CPUM68KState, fpsr));
break;
case M68K_FPCR:
- gen_helper_set_fpcr(cpu_env, val);
+ gen_helper_set_fpcr(tcg_env, val);
break;
}
}
* only available to store register to memory
*/
if (opsize == OS_EXTENDED) {
- gen_helper_fmovemx_st_predec(tmp, cpu_env, addr, tmp);
+ gen_helper_fmovemx_st_predec(tmp, tcg_env, addr, tmp);
} else {
- gen_helper_fmovemd_st_predec(tmp, cpu_env, addr, tmp);
+ gen_helper_fmovemd_st_predec(tmp, tcg_env, addr, tmp);
}
} else {
/* postincrement addressing mode */
if (opsize == OS_EXTENDED) {
if (is_load) {
- gen_helper_fmovemx_ld_postinc(tmp, cpu_env, addr, tmp);
+ gen_helper_fmovemx_ld_postinc(tmp, tcg_env, addr, tmp);
} else {
- gen_helper_fmovemx_st_postinc(tmp, cpu_env, addr, tmp);
+ gen_helper_fmovemx_st_postinc(tmp, tcg_env, addr, tmp);
}
} else {
if (is_load) {
- gen_helper_fmovemd_ld_postinc(tmp, cpu_env, addr, tmp);
+ gen_helper_fmovemd_ld_postinc(tmp, tcg_env, addr, tmp);
} else {
- gen_helper_fmovemd_st_postinc(tmp, cpu_env, addr, tmp);
+ gen_helper_fmovemd_st_postinc(tmp, tcg_env, addr, tmp);
}
}
}
/* fmovecr */
TCGv rom_offset = tcg_constant_i32(opmode);
cpu_dest = gen_fp_ptr(REG(ext, 7));
- gen_helper_fconst(cpu_env, cpu_dest, rom_offset);
+ gen_helper_fconst(tcg_env, cpu_dest, rom_offset);
return;
}
break;
EA_STORE, IS_USER(s)) == -1) {
gen_addr_fault(s);
}
- gen_helper_ftst(cpu_env, cpu_src);
+ gen_helper_ftst(tcg_env, cpu_src);
return;
case 4: /* fmove to control register. */
case 5: /* fmove from control register. */
gen_fp_move(cpu_dest, cpu_src);
break;
case 0x40: /* fsmove */
- gen_helper_fsround(cpu_env, cpu_dest, cpu_src);
+ gen_helper_fsround(tcg_env, cpu_dest, cpu_src);
break;
case 0x44: /* fdmove */
- gen_helper_fdround(cpu_env, cpu_dest, cpu_src);
+ gen_helper_fdround(tcg_env, cpu_dest, cpu_src);
break;
case 1: /* fint */
- gen_helper_firound(cpu_env, cpu_dest, cpu_src);
+ gen_helper_firound(tcg_env, cpu_dest, cpu_src);
break;
case 2: /* fsinh */
- gen_helper_fsinh(cpu_env, cpu_dest, cpu_src);
+ gen_helper_fsinh(tcg_env, cpu_dest, cpu_src);
break;
case 3: /* fintrz */
- gen_helper_fitrunc(cpu_env, cpu_dest, cpu_src);
+ gen_helper_fitrunc(tcg_env, cpu_dest, cpu_src);
break;
case 4: /* fsqrt */
- gen_helper_fsqrt(cpu_env, cpu_dest, cpu_src);
+ gen_helper_fsqrt(tcg_env, cpu_dest, cpu_src);
break;
case 0x41: /* fssqrt */
- gen_helper_fssqrt(cpu_env, cpu_dest, cpu_src);
+ gen_helper_fssqrt(tcg_env, cpu_dest, cpu_src);
break;
case 0x45: /* fdsqrt */
- gen_helper_fdsqrt(cpu_env, cpu_dest, cpu_src);
+ gen_helper_fdsqrt(tcg_env, cpu_dest, cpu_src);
break;
case 0x06: /* flognp1 */
- gen_helper_flognp1(cpu_env, cpu_dest, cpu_src);
+ gen_helper_flognp1(tcg_env, cpu_dest, cpu_src);
break;
case 0x08: /* fetoxm1 */
- gen_helper_fetoxm1(cpu_env, cpu_dest, cpu_src);
+ gen_helper_fetoxm1(tcg_env, cpu_dest, cpu_src);
break;
case 0x09: /* ftanh */
- gen_helper_ftanh(cpu_env, cpu_dest, cpu_src);
+ gen_helper_ftanh(tcg_env, cpu_dest, cpu_src);
break;
case 0x0a: /* fatan */
- gen_helper_fatan(cpu_env, cpu_dest, cpu_src);
+ gen_helper_fatan(tcg_env, cpu_dest, cpu_src);
break;
case 0x0c: /* fasin */
- gen_helper_fasin(cpu_env, cpu_dest, cpu_src);
+ gen_helper_fasin(tcg_env, cpu_dest, cpu_src);
break;
case 0x0d: /* fatanh */
- gen_helper_fatanh(cpu_env, cpu_dest, cpu_src);
+ gen_helper_fatanh(tcg_env, cpu_dest, cpu_src);
break;
case 0x0e: /* fsin */
- gen_helper_fsin(cpu_env, cpu_dest, cpu_src);
+ gen_helper_fsin(tcg_env, cpu_dest, cpu_src);
break;
case 0x0f: /* ftan */
- gen_helper_ftan(cpu_env, cpu_dest, cpu_src);
+ gen_helper_ftan(tcg_env, cpu_dest, cpu_src);
break;
case 0x10: /* fetox */
- gen_helper_fetox(cpu_env, cpu_dest, cpu_src);
+ gen_helper_fetox(tcg_env, cpu_dest, cpu_src);
break;
case 0x11: /* ftwotox */
- gen_helper_ftwotox(cpu_env, cpu_dest, cpu_src);
+ gen_helper_ftwotox(tcg_env, cpu_dest, cpu_src);
break;
case 0x12: /* ftentox */
- gen_helper_ftentox(cpu_env, cpu_dest, cpu_src);
+ gen_helper_ftentox(tcg_env, cpu_dest, cpu_src);
break;
case 0x14: /* flogn */
- gen_helper_flogn(cpu_env, cpu_dest, cpu_src);
+ gen_helper_flogn(tcg_env, cpu_dest, cpu_src);
break;
case 0x15: /* flog10 */
- gen_helper_flog10(cpu_env, cpu_dest, cpu_src);
+ gen_helper_flog10(tcg_env, cpu_dest, cpu_src);
break;
case 0x16: /* flog2 */
- gen_helper_flog2(cpu_env, cpu_dest, cpu_src);
+ gen_helper_flog2(tcg_env, cpu_dest, cpu_src);
break;
case 0x18: /* fabs */
- gen_helper_fabs(cpu_env, cpu_dest, cpu_src);
+ gen_helper_fabs(tcg_env, cpu_dest, cpu_src);
break;
case 0x58: /* fsabs */
- gen_helper_fsabs(cpu_env, cpu_dest, cpu_src);
+ gen_helper_fsabs(tcg_env, cpu_dest, cpu_src);
break;
case 0x5c: /* fdabs */
- gen_helper_fdabs(cpu_env, cpu_dest, cpu_src);
+ gen_helper_fdabs(tcg_env, cpu_dest, cpu_src);
break;
case 0x19: /* fcosh */
- gen_helper_fcosh(cpu_env, cpu_dest, cpu_src);
+ gen_helper_fcosh(tcg_env, cpu_dest, cpu_src);
break;
case 0x1a: /* fneg */
- gen_helper_fneg(cpu_env, cpu_dest, cpu_src);
+ gen_helper_fneg(tcg_env, cpu_dest, cpu_src);
break;
case 0x5a: /* fsneg */
- gen_helper_fsneg(cpu_env, cpu_dest, cpu_src);
+ gen_helper_fsneg(tcg_env, cpu_dest, cpu_src);
break;
case 0x5e: /* fdneg */
- gen_helper_fdneg(cpu_env, cpu_dest, cpu_src);
+ gen_helper_fdneg(tcg_env, cpu_dest, cpu_src);
break;
case 0x1c: /* facos */
- gen_helper_facos(cpu_env, cpu_dest, cpu_src);
+ gen_helper_facos(tcg_env, cpu_dest, cpu_src);
break;
case 0x1d: /* fcos */
- gen_helper_fcos(cpu_env, cpu_dest, cpu_src);
+ gen_helper_fcos(tcg_env, cpu_dest, cpu_src);
break;
case 0x1e: /* fgetexp */
- gen_helper_fgetexp(cpu_env, cpu_dest, cpu_src);
+ gen_helper_fgetexp(tcg_env, cpu_dest, cpu_src);
break;
case 0x1f: /* fgetman */
- gen_helper_fgetman(cpu_env, cpu_dest, cpu_src);
+ gen_helper_fgetman(tcg_env, cpu_dest, cpu_src);
break;
case 0x20: /* fdiv */
- gen_helper_fdiv(cpu_env, cpu_dest, cpu_src, cpu_dest);
+ gen_helper_fdiv(tcg_env, cpu_dest, cpu_src, cpu_dest);
break;
case 0x60: /* fsdiv */
- gen_helper_fsdiv(cpu_env, cpu_dest, cpu_src, cpu_dest);
+ gen_helper_fsdiv(tcg_env, cpu_dest, cpu_src, cpu_dest);
break;
case 0x64: /* fddiv */
- gen_helper_fddiv(cpu_env, cpu_dest, cpu_src, cpu_dest);
+ gen_helper_fddiv(tcg_env, cpu_dest, cpu_src, cpu_dest);
break;
case 0x21: /* fmod */
- gen_helper_fmod(cpu_env, cpu_dest, cpu_src, cpu_dest);
+ gen_helper_fmod(tcg_env, cpu_dest, cpu_src, cpu_dest);
break;
case 0x22: /* fadd */
- gen_helper_fadd(cpu_env, cpu_dest, cpu_src, cpu_dest);
+ gen_helper_fadd(tcg_env, cpu_dest, cpu_src, cpu_dest);
break;
case 0x62: /* fsadd */
- gen_helper_fsadd(cpu_env, cpu_dest, cpu_src, cpu_dest);
+ gen_helper_fsadd(tcg_env, cpu_dest, cpu_src, cpu_dest);
break;
case 0x66: /* fdadd */
- gen_helper_fdadd(cpu_env, cpu_dest, cpu_src, cpu_dest);
+ gen_helper_fdadd(tcg_env, cpu_dest, cpu_src, cpu_dest);
break;
case 0x23: /* fmul */
- gen_helper_fmul(cpu_env, cpu_dest, cpu_src, cpu_dest);
+ gen_helper_fmul(tcg_env, cpu_dest, cpu_src, cpu_dest);
break;
case 0x63: /* fsmul */
- gen_helper_fsmul(cpu_env, cpu_dest, cpu_src, cpu_dest);
+ gen_helper_fsmul(tcg_env, cpu_dest, cpu_src, cpu_dest);
break;
case 0x67: /* fdmul */
- gen_helper_fdmul(cpu_env, cpu_dest, cpu_src, cpu_dest);
+ gen_helper_fdmul(tcg_env, cpu_dest, cpu_src, cpu_dest);
break;
case 0x24: /* fsgldiv */
- gen_helper_fsgldiv(cpu_env, cpu_dest, cpu_src, cpu_dest);
+ gen_helper_fsgldiv(tcg_env, cpu_dest, cpu_src, cpu_dest);
break;
case 0x25: /* frem */
- gen_helper_frem(cpu_env, cpu_dest, cpu_src, cpu_dest);
+ gen_helper_frem(tcg_env, cpu_dest, cpu_src, cpu_dest);
break;
case 0x26: /* fscale */
- gen_helper_fscale(cpu_env, cpu_dest, cpu_src, cpu_dest);
+ gen_helper_fscale(tcg_env, cpu_dest, cpu_src, cpu_dest);
break;
case 0x27: /* fsglmul */
- gen_helper_fsglmul(cpu_env, cpu_dest, cpu_src, cpu_dest);
+ gen_helper_fsglmul(tcg_env, cpu_dest, cpu_src, cpu_dest);
break;
case 0x28: /* fsub */
- gen_helper_fsub(cpu_env, cpu_dest, cpu_src, cpu_dest);
+ gen_helper_fsub(tcg_env, cpu_dest, cpu_src, cpu_dest);
break;
case 0x68: /* fssub */
- gen_helper_fssub(cpu_env, cpu_dest, cpu_src, cpu_dest);
+ gen_helper_fssub(tcg_env, cpu_dest, cpu_src, cpu_dest);
break;
case 0x6c: /* fdsub */
- gen_helper_fdsub(cpu_env, cpu_dest, cpu_src, cpu_dest);
+ gen_helper_fdsub(tcg_env, cpu_dest, cpu_src, cpu_dest);
break;
case 0x30: case 0x31: case 0x32:
case 0x33: case 0x34: case 0x35:
case 0x36: case 0x37: {
TCGv_ptr cpu_dest2 = gen_fp_ptr(REG(ext, 0));
- gen_helper_fsincos(cpu_env, cpu_dest, cpu_dest2, cpu_src);
+ gen_helper_fsincos(tcg_env, cpu_dest, cpu_dest2, cpu_src);
}
break;
case 0x38: /* fcmp */
- gen_helper_fcmp(cpu_env, cpu_src, cpu_dest);
+ gen_helper_fcmp(tcg_env, cpu_src, cpu_dest);
return;
case 0x3a: /* ftst */
- gen_helper_ftst(cpu_env, cpu_src);
+ gen_helper_ftst(tcg_env, cpu_src);
return;
default:
goto undef;
}
- gen_helper_ftst(cpu_env, cpu_dest);
+ gen_helper_ftst(tcg_env, cpu_dest);
return;
undef:
/* FIXME: Is this right for offset addressing modes? */
ry = gen_mac_extract_word(s, ry, (ext & 0x40) != 0);
}
if (s->env->macsr & MACSR_FI) {
- gen_helper_macmulf(s->mactmp, cpu_env, rx, ry);
+ gen_helper_macmulf(s->mactmp, tcg_env, rx, ry);
} else {
if (s->env->macsr & MACSR_SU)
- gen_helper_macmuls(s->mactmp, cpu_env, rx, ry);
+ gen_helper_macmuls(s->mactmp, tcg_env, rx, ry);
else
- gen_helper_macmulu(s->mactmp, cpu_env, rx, ry);
+ gen_helper_macmulu(s->mactmp, tcg_env, rx, ry);
switch ((ext >> 9) & 3) {
case 1:
tcg_gen_shli_i64(s->mactmp, s->mactmp, 1);
tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp);
if (s->env->macsr & MACSR_FI)
- gen_helper_macsatf(cpu_env, tcg_constant_i32(acc));
+ gen_helper_macsatf(tcg_env, tcg_constant_i32(acc));
else if (s->env->macsr & MACSR_SU)
- gen_helper_macsats(cpu_env, tcg_constant_i32(acc));
+ gen_helper_macsats(tcg_env, tcg_constant_i32(acc));
else
- gen_helper_macsatu(cpu_env, tcg_constant_i32(acc));
+ gen_helper_macsatu(tcg_env, tcg_constant_i32(acc));
#if 0
/* Disabled because conditional branches clobber temporary vars. */
else
tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp);
if (s->env->macsr & MACSR_FI)
- gen_helper_macsatf(cpu_env, tcg_constant_i32(acc));
+ gen_helper_macsatf(tcg_env, tcg_constant_i32(acc));
else if (s->env->macsr & MACSR_SU)
- gen_helper_macsats(cpu_env, tcg_constant_i32(acc));
+ gen_helper_macsats(tcg_env, tcg_constant_i32(acc));
else
- gen_helper_macsatu(cpu_env, tcg_constant_i32(acc));
+ gen_helper_macsatu(tcg_env, tcg_constant_i32(acc));
#if 0
/* Disabled because conditional branches clobber temporary vars. */
if (l1 != -1)
gen_set_label(l1);
#endif
}
- gen_helper_mac_set_flags(cpu_env, tcg_constant_i32(acc));
+ gen_helper_mac_set_flags(tcg_env, tcg_constant_i32(acc));
if (insn & 0x30) {
TCGv rw;
accnum = (insn >> 9) & 3;
acc = MACREG(accnum);
if (s->env->macsr & MACSR_FI) {
- gen_helper_get_macf(rx, cpu_env, acc);
+ gen_helper_get_macf(rx, tcg_env, acc);
} else if ((s->env->macsr & MACSR_OMC) == 0) {
tcg_gen_extrl_i64_i32(rx, acc);
} else if (s->env->macsr & MACSR_SU) {
TCGv dest;
src = insn & 3;
dest = tcg_constant_i32((insn >> 9) & 3);
- gen_helper_mac_move(cpu_env, dest, tcg_constant_i32(src));
+ gen_helper_mac_move(tcg_env, dest, tcg_constant_i32(src));
gen_mac_clear_flags();
- gen_helper_mac_set_flags(cpu_env, dest);
+ gen_helper_mac_set_flags(tcg_env, dest);
}
DISAS_INSN(from_macsr)
reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
acc = tcg_constant_i32((insn & 0x400) ? 2 : 0);
if (s->env->macsr & MACSR_FI)
- gen_helper_get_mac_extf(reg, cpu_env, acc);
+ gen_helper_get_mac_extf(reg, tcg_env, acc);
else
- gen_helper_get_mac_exti(reg, cpu_env, acc);
+ gen_helper_get_mac_exti(reg, tcg_env, acc);
}
DISAS_INSN(macsr_to_ccr)
/* Note that X and C are always cleared. */
tcg_gen_andi_i32(tmp, QREG_MACSR, CCF_N | CCF_Z | CCF_V);
- gen_helper_set_ccr(cpu_env, tmp);
+ gen_helper_set_ccr(tcg_env, tmp);
set_cc_op(s, CC_OP_FLAGS);
}
}
tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum));
gen_mac_clear_flags();
- gen_helper_mac_set_flags(cpu_env, tcg_constant_i32(accnum));
+ gen_helper_mac_set_flags(tcg_env, tcg_constant_i32(accnum));
}
DISAS_INSN(to_macsr)
{
TCGv val;
SRC_EA(env, val, OS_LONG, 0, NULL);
- gen_helper_set_macsr(cpu_env, val);
+ gen_helper_set_macsr(tcg_env, val);
gen_exit_tb(s);
}
SRC_EA(env, val, OS_LONG, 0, NULL);
acc = tcg_constant_i32((insn & 0x400) ? 2 : 0);
if (s->env->macsr & MACSR_FI)
- gen_helper_set_mac_extf(cpu_env, val, acc);
+ gen_helper_set_mac_extf(tcg_env, val, acc);
else if (s->env->macsr & MACSR_SU)
- gen_helper_set_mac_exts(cpu_env, val, acc);
+ gen_helper_set_mac_exts(tcg_env, val, acc);
else
- gen_helper_set_mac_extu(cpu_env, val, acc);
+ gen_helper_set_mac_extu(tcg_env, val, acc);
}
static disas_proc opcode_table[65536];
static void gen_raise_exception(DisasContext *dc, uint32_t index)
{
- gen_helper_raise_exception(cpu_env, tcg_constant_i32(index));
+ gen_helper_raise_exception(tcg_env, tcg_constant_i32(index));
dc->base.is_jmp = DISAS_NORETURN;
}
static void gen_raise_hw_excp(DisasContext *dc, uint32_t esr_ec)
{
TCGv_i32 tmp = tcg_constant_i32(esr_ec);
- tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUMBState, esr));
+ tcg_gen_st_i32(tmp, tcg_env, offsetof(CPUMBState, esr));
gen_raise_exception_sync(dc, EXCP_HW_EXCP);
}
#define ENV_WRAPPER2(NAME, HELPER) \
static void NAME(TCGv_i32 out, TCGv_i32 ina) \
- { HELPER(out, cpu_env, ina); }
+ { HELPER(out, tcg_env, ina); }
#define ENV_WRAPPER3(NAME, HELPER) \
static void NAME(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) \
- { HELPER(out, cpu_env, ina, inb); }
+ { HELPER(out, tcg_env, ina, inb); }
/* No input carry, but output carry. */
static void gen_add(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
/* Does not use ENV_WRAPPER3, because arguments are swapped as well. */
static void gen_idiv(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
{
- gen_helper_divs(out, cpu_env, inb, ina);
+ gen_helper_divs(out, tcg_env, inb, ina);
}
static void gen_idivu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
{
- gen_helper_divu(out, cpu_env, inb, ina);
+ gen_helper_divu(out, tcg_env, inb, ina);
}
DO_TYPEA_CFG(idiv, use_div, true, gen_idiv)
}
if ((ra == 1 || rb == 1) && dc->cfg->stackprot) {
- gen_helper_stackprot(cpu_env, ret);
+ gen_helper_stackprot(tcg_env, ret);
}
return ret;
}
}
if (ra == 1 && dc->cfg->stackprot) {
- gen_helper_stackprot(cpu_env, ret);
+ gen_helper_stackprot(tcg_env, ret);
}
return ret;
}
t_sync_flags(dc);
- tcg_gen_st_i32(tcg_constant_i32(1), cpu_env,
+ tcg_gen_st_i32(tcg_constant_i32(1), tcg_env,
-offsetof(MicroBlazeCPU, env)
+offsetof(CPUState, halted));
tcg_gen_andi_i32(cpu_msr, src, ~(MSR_C | MSR_CC | MSR_PVR));
break;
case SR_FSR:
- tcg_gen_st_i32(src, cpu_env, offsetof(CPUMBState, fsr));
+ tcg_gen_st_i32(src, tcg_env, offsetof(CPUMBState, fsr));
break;
case 0x800:
- tcg_gen_st_i32(src, cpu_env, offsetof(CPUMBState, slr));
+ tcg_gen_st_i32(src, tcg_env, offsetof(CPUMBState, slr));
break;
case 0x802:
- tcg_gen_st_i32(src, cpu_env, offsetof(CPUMBState, shr));
+ tcg_gen_st_i32(src, tcg_env, offsetof(CPUMBState, shr));
break;
case 0x1000: /* PID */
TCGv_i32 tmp_ext = tcg_constant_i32(arg->e);
TCGv_i32 tmp_reg = tcg_constant_i32(arg->rs & 7);
- gen_helper_mmu_write(cpu_env, tmp_ext, tmp_reg, src);
+ gen_helper_mmu_write(tcg_env, tmp_ext, tmp_reg, src);
}
break;
case SR_EAR:
{
TCGv_i64 t64 = tcg_temp_new_i64();
- tcg_gen_ld_i64(t64, cpu_env, offsetof(CPUMBState, ear));
+ tcg_gen_ld_i64(t64, tcg_env, offsetof(CPUMBState, ear));
tcg_gen_extrh_i64_i32(dest, t64);
}
return true;
case SR_EAR:
{
TCGv_i64 t64 = tcg_temp_new_i64();
- tcg_gen_ld_i64(t64, cpu_env, offsetof(CPUMBState, ear));
+ tcg_gen_ld_i64(t64, tcg_env, offsetof(CPUMBState, ear));
tcg_gen_extrl_i64_i32(dest, t64);
}
break;
case SR_ESR:
- tcg_gen_ld_i32(dest, cpu_env, offsetof(CPUMBState, esr));
+ tcg_gen_ld_i32(dest, tcg_env, offsetof(CPUMBState, esr));
break;
case SR_FSR:
- tcg_gen_ld_i32(dest, cpu_env, offsetof(CPUMBState, fsr));
+ tcg_gen_ld_i32(dest, tcg_env, offsetof(CPUMBState, fsr));
break;
case SR_BTR:
- tcg_gen_ld_i32(dest, cpu_env, offsetof(CPUMBState, btr));
+ tcg_gen_ld_i32(dest, tcg_env, offsetof(CPUMBState, btr));
break;
case SR_EDR:
- tcg_gen_ld_i32(dest, cpu_env, offsetof(CPUMBState, edr));
+ tcg_gen_ld_i32(dest, tcg_env, offsetof(CPUMBState, edr));
break;
case 0x800:
- tcg_gen_ld_i32(dest, cpu_env, offsetof(CPUMBState, slr));
+ tcg_gen_ld_i32(dest, tcg_env, offsetof(CPUMBState, slr));
break;
case 0x802:
- tcg_gen_ld_i32(dest, cpu_env, offsetof(CPUMBState, shr));
+ tcg_gen_ld_i32(dest, tcg_env, offsetof(CPUMBState, shr));
break;
#ifndef CONFIG_USER_ONLY
TCGv_i32 tmp_ext = tcg_constant_i32(arg->e);
TCGv_i32 tmp_reg = tcg_constant_i32(arg->rs & 7);
- gen_helper_mmu_read(dest, cpu_env, tmp_ext, tmp_reg);
+ gen_helper_mmu_read(dest, tcg_env, tmp_ext, tmp_reg);
}
break;
#endif
case 0x2000 ... 0x200c:
- tcg_gen_ld_i32(dest, cpu_env,
+ tcg_gen_ld_i32(dest, tcg_env,
offsetof(MicroBlazeCPU, cfg.pvr_regs[arg->rs - 0x2000])
- offsetof(MicroBlazeCPU, env));
break;
for (int i = 0; i < ARRAY_SIZE(i32s); ++i) {
*i32s[i].var =
- tcg_global_mem_new_i32(cpu_env, i32s[i].ofs, i32s[i].name);
+ tcg_global_mem_new_i32(tcg_env, i32s[i].ofs, i32s[i].name);
}
cpu_res_addr =
- tcg_global_mem_new(cpu_env, offsetof(CPUMBState, res_addr), "res_addr");
+ tcg_global_mem_new(tcg_env, offsetof(CPUMBState, res_addr), "res_addr");
}
TCGv src1 = tcg_temp_new();
gen_load_gpr(src1, a->rs);
- gen_helper_lcsr_cpucfg(dest, cpu_env, src1);
+ gen_helper_lcsr_cpucfg(dest, tcg_env, src1);
gen_store_gpr(dest, a->rd);
return true;
check_cp0_enabled(ctx);
gen_load_gpr(src1, a->rs);
- func(dest, cpu_env, src1);
+ func(dest, tcg_env, src1);
gen_store_gpr(dest, a->rd);
return true;
check_cp0_enabled(ctx);
gen_load_gpr(addr, a->rs);
gen_load_gpr(val, a->rd);
- func(cpu_env, addr, val);
+ func(tcg_env, addr, val);
return true;
}
save_cpu_state(ctx, 1);
switch (opc) {
case LWM32:
- gen_helper_lwm(cpu_env, t0, t1, t2);
+ gen_helper_lwm(tcg_env, t0, t1, t2);
break;
case SWM32:
- gen_helper_swm(cpu_env, t0, t1, t2);
+ gen_helper_swm(tcg_env, t0, t1, t2);
break;
#ifdef TARGET_MIPS64
case LDM:
- gen_helper_ldm(cpu_env, t0, t1, t2);
+ gen_helper_ldm(tcg_env, t0, t1, t2);
break;
case SDM:
- gen_helper_sdm(cpu_env, t0, t1, t2);
+ gen_helper_sdm(tcg_env, t0, t1, t2);
break;
#endif
}
TCGv t0 = tcg_temp_new();
save_cpu_state(ctx, 1);
- gen_helper_di(t0, cpu_env);
+ gen_helper_di(t0, tcg_env);
gen_store_gpr(t0, rs);
/*
* Stop translation as we may have switched the execution
TCGv t0 = tcg_temp_new();
save_cpu_state(ctx, 1);
- gen_helper_ei(t0, cpu_env);
+ gen_helper_ei(t0, tcg_env);
gen_store_gpr(t0, rs);
/*
* DISAS_STOP isn't sufficient, we need to ensure we break out
off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]);
msa_wr_d[i * 2 + 1] =
- tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1]);
+ tcg_global_mem_new_i64(tcg_env, off, msaregnames[i * 2 + 1]);
}
}
return true;
}
- gen_msa_i8(cpu_env,
+ gen_msa_i8(tcg_env,
tcg_constant_i32(a->wd),
tcg_constant_i32(a->ws),
tcg_constant_i32(a->sa));
return true;
}
- gen_helper_msa_shf_df(cpu_env,
+ gen_helper_msa_shf_df(tcg_env,
tcg_constant_i32(a->df),
tcg_constant_i32(a->wd),
tcg_constant_i32(a->ws),
return true;
}
- gen_msa_i5(cpu_env,
+ gen_msa_i5(tcg_env,
tcg_constant_i32(a->df),
tcg_constant_i32(a->wd),
tcg_constant_i32(a->ws),
return true;
}
- gen_helper_msa_ldi_df(cpu_env,
+ gen_helper_msa_ldi_df(tcg_env,
tcg_constant_i32(a->df),
tcg_constant_i32(a->wd),
tcg_constant_i32(a->sa));
return true;
}
- gen_msa_bit(cpu_env,
+ gen_msa_bit(tcg_env,
tcg_constant_i32(a->df),
tcg_constant_i32(a->wd),
tcg_constant_i32(a->ws),
return true;
}
- gen_msa_3rf(cpu_env,
+ gen_msa_3rf(tcg_env,
tcg_constant_i32(a->df),
tcg_constant_i32(a->wd),
tcg_constant_i32(a->ws),
return true;
}
- gen_msa_3r(cpu_env,
+ gen_msa_3r(tcg_env,
tcg_constant_i32(a->wd),
tcg_constant_i32(a->ws),
tcg_constant_i32(a->wt));
return true;
}
- gen_helper_msa_move_v(cpu_env,
+ gen_helper_msa_move_v(tcg_env,
tcg_constant_i32(a->wd),
tcg_constant_i32(a->ws));
telm = tcg_temp_new();
gen_load_gpr(telm, a->ws);
- gen_helper_msa_ctcmsa(cpu_env, telm, tcg_constant_i32(a->wd));
+ gen_helper_msa_ctcmsa(tcg_env, telm, tcg_constant_i32(a->wd));
return true;
}
telm = tcg_temp_new();
- gen_helper_msa_cfcmsa(telm, cpu_env, tcg_constant_i32(a->ws));
+ gen_helper_msa_cfcmsa(telm, tcg_env, tcg_constant_i32(a->ws));
gen_store_gpr(telm, a->wd);
return true;
return true;
}
- gen_msa_elm_df(cpu_env,
+ gen_msa_elm_df(tcg_env,
tcg_constant_i32(a->df),
tcg_constant_i32(a->wd),
tcg_constant_i32(a->ws),
return true;
}
- gen_msa_elm[a->df](cpu_env,
+ gen_msa_elm[a->df](tcg_env,
tcg_constant_i32(a->wd),
tcg_constant_i32(a->ws),
tcg_constant_i32(a->n));
return true;
}
- gen_msa_2r(cpu_env, tcg_constant_i32(a->wd), tcg_constant_i32(a->ws));
+ gen_msa_2r(tcg_env, tcg_constant_i32(a->wd), tcg_constant_i32(a->ws));
return true;
}
return true;
}
- gen_helper_msa_fill_df(cpu_env,
+ gen_helper_msa_fill_df(tcg_env,
tcg_constant_i32(a->df),
tcg_constant_i32(a->wd),
tcg_constant_i32(a->ws));
return true;
}
- gen_msa_2rf(cpu_env,
+ gen_msa_2rf(tcg_env,
tcg_constant_i32(a->df),
tcg_constant_i32(a->wd),
tcg_constant_i32(a->ws));
taddr = tcg_temp_new();
gen_base_offset_addr(ctx, taddr, a->ws, a->sa << a->df);
- gen_msa_ldst(cpu_env, tcg_constant_i32(a->wd), taddr);
+ gen_msa_ldst(tcg_env, tcg_constant_i32(a->wd), taddr);
return true;
}
void mxu_translate_init(void)
{
for (unsigned i = 0; i < NUMBER_OF_MXU_REGISTERS - 1; i++) {
- mxu_gpr[i] = tcg_global_mem_new(cpu_env,
+ mxu_gpr[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUMIPSState, active_tc.mxu_gpr[i]),
mxuregnames[i]);
}
- mxu_CR = tcg_global_mem_new(cpu_env,
+ mxu_CR = tcg_global_mem_new(tcg_env,
offsetof(CPUMIPSState, active_tc.mxu_cr),
mxuregnames[NUMBER_OF_MXU_REGISTERS - 1]);
}
}
gen_store_gpr(tmp1, reg1);
gen_store_gpr(tmp2, reg2);
- tcg_gen_st_i64(tval, cpu_env, offsetof(CPUMIPSState, llval_wp));
- tcg_gen_st_tl(taddr, cpu_env, offsetof(CPUMIPSState, lladdr));
+ tcg_gen_st_i64(tval, tcg_env, offsetof(CPUMIPSState, llval_wp));
+ tcg_gen_st_tl(taddr, tcg_env, offsetof(CPUMIPSState, lladdr));
}
static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset,
gen_base_offset_addr(ctx, taddr, base, offset);
- tcg_gen_ld_tl(lladdr, cpu_env, offsetof(CPUMIPSState, lladdr));
+ tcg_gen_ld_tl(lladdr, tcg_env, offsetof(CPUMIPSState, lladdr));
tcg_gen_brcond_tl(TCG_COND_NE, taddr, lladdr, lab_fail);
gen_load_gpr(tmp1, reg1);
tcg_gen_concat_tl_i64(tval, tmp1, tmp2);
}
- tcg_gen_ld_i64(llval, cpu_env, offsetof(CPUMIPSState, llval_wp));
+ tcg_gen_ld_i64(llval, tcg_env, offsetof(CPUMIPSState, llval_wp));
tcg_gen_atomic_cmpxchg_i64(val, taddr, llval, tval,
eva ? MIPS_HFLAG_UM : ctx->mem_idx,
MO_64 | MO_ALIGN);
}
gen_set_label(lab_done);
tcg_gen_movi_tl(lladdr, -1);
- tcg_gen_st_tl(lladdr, cpu_env, offsetof(CPUMIPSState, lladdr));
+ tcg_gen_st_tl(lladdr, tcg_env, offsetof(CPUMIPSState, lladdr));
}
static void gen_adjust_sp(DisasContext *ctx, int u)
case NM_DVP:
if (ctx->vp) {
check_cp0_enabled(ctx);
- gen_helper_dvp(t0, cpu_env);
+ gen_helper_dvp(t0, tcg_env);
gen_store_gpr(t0, rt);
}
break;
case NM_EVP:
if (ctx->vp) {
check_cp0_enabled(ctx);
- gen_helper_evp(t0, cpu_env);
+ gen_helper_evp(t0, tcg_env);
gen_store_gpr(t0, rt);
}
break;
} else if (rs == 0) {
/* DVPE */
check_cp0_mt(ctx);
- gen_helper_dvpe(t0, cpu_env);
+ gen_helper_dvpe(t0, tcg_env);
gen_store_gpr(t0, rt);
} else {
gen_reserved_instruction(ctx);
} else if (rs == 0) {
/* EVPE */
check_cp0_mt(ctx);
- gen_helper_evpe(t0, cpu_env);
+ gen_helper_evpe(t0, tcg_env);
gen_store_gpr(t0, rt);
} else {
gen_reserved_instruction(ctx);
TCGv t0 = tcg_temp_new();
gen_load_gpr(t0, rs);
- gen_helper_yield(t0, cpu_env, t0);
+ gen_helper_yield(t0, tcg_env, t0);
gen_store_gpr(t0, rt);
}
break;
switch (opc) {
case NM_MAQ_S_W_PHR:
check_dsp(ctx);
- gen_helper_maq_s_w_phr(t0, v1_t, v0_t, cpu_env);
+ gen_helper_maq_s_w_phr(t0, v1_t, v0_t, tcg_env);
break;
case NM_MAQ_S_W_PHL:
check_dsp(ctx);
- gen_helper_maq_s_w_phl(t0, v1_t, v0_t, cpu_env);
+ gen_helper_maq_s_w_phl(t0, v1_t, v0_t, tcg_env);
break;
case NM_MAQ_SA_W_PHR:
check_dsp(ctx);
- gen_helper_maq_sa_w_phr(t0, v1_t, v0_t, cpu_env);
+ gen_helper_maq_sa_w_phr(t0, v1_t, v0_t, tcg_env);
break;
case NM_MAQ_SA_W_PHL:
check_dsp(ctx);
- gen_helper_maq_sa_w_phl(t0, v1_t, v0_t, cpu_env);
+ gen_helper_maq_sa_w_phl(t0, v1_t, v0_t, tcg_env);
break;
default:
gen_reserved_instruction(ctx);
switch (extract32(ctx->opcode, 12, 2)) {
case NM_MTHLIP:
tcg_gen_movi_tl(t0, v2 >> 3);
- gen_helper_mthlip(t0, v0_t, cpu_env);
+ gen_helper_mthlip(t0, v0_t, tcg_env);
break;
case NM_SHILOV:
tcg_gen_movi_tl(t0, v2 >> 3);
- gen_helper_shilo(t0, v0_t, cpu_env);
+ gen_helper_shilo(t0, v0_t, tcg_env);
break;
default:
gen_reserved_instruction(ctx);
switch (extract32(ctx->opcode, 12, 2)) {
case NM_RDDSP:
tcg_gen_movi_tl(t0, imm);
- gen_helper_rddsp(t0, t0, cpu_env);
+ gen_helper_rddsp(t0, t0, tcg_env);
gen_store_gpr(t0, ret);
break;
case NM_WRDSP:
gen_load_gpr(t0, ret);
tcg_gen_movi_tl(t1, imm);
- gen_helper_wrdsp(t0, t1, cpu_env);
+ gen_helper_wrdsp(t0, t1, tcg_env);
break;
case NM_EXTP:
tcg_gen_movi_tl(t0, v2 >> 3);
tcg_gen_movi_tl(t1, v1);
- gen_helper_extp(t0, t0, t1, cpu_env);
+ gen_helper_extp(t0, t0, t1, tcg_env);
gen_store_gpr(t0, ret);
break;
case NM_EXTPDP:
tcg_gen_movi_tl(t0, v2 >> 3);
tcg_gen_movi_tl(t1, v1);
- gen_helper_extpdp(t0, t0, t1, cpu_env);
+ gen_helper_extpdp(t0, t0, t1, tcg_env);
gen_store_gpr(t0, ret);
break;
}
tcg_gen_movi_tl(t0, v2 >> 2);
switch (extract32(ctx->opcode, 12, 1)) {
case NM_SHLL_QB:
- gen_helper_shll_qb(t0, t0, v0_t, cpu_env);
+ gen_helper_shll_qb(t0, t0, v0_t, tcg_env);
gen_store_gpr(t0, ret);
break;
case NM_SHRL_QB:
tcg_gen_movi_tl(t1, v1);
switch (extract32(ctx->opcode, 12, 2)) {
case NM_EXTR_W:
- gen_helper_extr_w(t0, t0, t1, cpu_env);
+ gen_helper_extr_w(t0, t0, t1, tcg_env);
gen_store_gpr(t0, ret);
break;
case NM_EXTR_R_W:
- gen_helper_extr_r_w(t0, t0, t1, cpu_env);
+ gen_helper_extr_r_w(t0, t0, t1, tcg_env);
gen_store_gpr(t0, ret);
break;
case NM_EXTR_RS_W:
- gen_helper_extr_rs_w(t0, t0, t1, cpu_env);
+ gen_helper_extr_rs_w(t0, t0, t1, tcg_env);
gen_store_gpr(t0, ret);
break;
case NM_EXTR_S_H:
- gen_helper_extr_s_h(t0, t0, t1, cpu_env);
+ gen_helper_extr_s_h(t0, t0, t1, tcg_env);
gen_store_gpr(t0, ret);
break;
}
switch (extract32(ctx->opcode, 9, 3)) {
case NM_DPA_W_PH:
check_dsp_r2(ctx);
- gen_helper_dpa_w_ph(t0, v1, v0, cpu_env);
+ gen_helper_dpa_w_ph(t0, v1, v0, tcg_env);
break;
case NM_DPAQ_S_W_PH:
check_dsp(ctx);
- gen_helper_dpaq_s_w_ph(t0, v1, v0, cpu_env);
+ gen_helper_dpaq_s_w_ph(t0, v1, v0, tcg_env);
break;
case NM_DPS_W_PH:
check_dsp_r2(ctx);
- gen_helper_dps_w_ph(t0, v1, v0, cpu_env);
+ gen_helper_dps_w_ph(t0, v1, v0, tcg_env);
break;
case NM_DPSQ_S_W_PH:
check_dsp(ctx);
- gen_helper_dpsq_s_w_ph(t0, v1, v0, cpu_env);
+ gen_helper_dpsq_s_w_ph(t0, v1, v0, tcg_env);
break;
default:
gen_reserved_instruction(ctx);
switch (extract32(ctx->opcode, 9, 3)) {
case NM_DPAX_W_PH:
check_dsp_r2(ctx);
- gen_helper_dpax_w_ph(t0, v0, v1, cpu_env);
+ gen_helper_dpax_w_ph(t0, v0, v1, tcg_env);
break;
case NM_DPAQ_SA_L_W:
check_dsp(ctx);
- gen_helper_dpaq_sa_l_w(t0, v0, v1, cpu_env);
+ gen_helper_dpaq_sa_l_w(t0, v0, v1, tcg_env);
break;
case NM_DPSX_W_PH:
check_dsp_r2(ctx);
- gen_helper_dpsx_w_ph(t0, v0, v1, cpu_env);
+ gen_helper_dpsx_w_ph(t0, v0, v1, tcg_env);
break;
case NM_DPSQ_SA_L_W:
check_dsp(ctx);
- gen_helper_dpsq_sa_l_w(t0, v0, v1, cpu_env);
+ gen_helper_dpsq_sa_l_w(t0, v0, v1, tcg_env);
break;
default:
gen_reserved_instruction(ctx);
switch (extract32(ctx->opcode, 9, 3)) {
case NM_DPAU_H_QBL:
check_dsp(ctx);
- gen_helper_dpau_h_qbl(t0, v0, v1, cpu_env);
+ gen_helper_dpau_h_qbl(t0, v0, v1, tcg_env);
break;
case NM_DPAQX_S_W_PH:
check_dsp_r2(ctx);
- gen_helper_dpaqx_s_w_ph(t0, v0, v1, cpu_env);
+ gen_helper_dpaqx_s_w_ph(t0, v0, v1, tcg_env);
break;
case NM_DPSU_H_QBL:
check_dsp(ctx);
- gen_helper_dpsu_h_qbl(t0, v0, v1, cpu_env);
+ gen_helper_dpsu_h_qbl(t0, v0, v1, tcg_env);
break;
case NM_DPSQX_S_W_PH:
check_dsp_r2(ctx);
- gen_helper_dpsqx_s_w_ph(t0, v0, v1, cpu_env);
+ gen_helper_dpsqx_s_w_ph(t0, v0, v1, tcg_env);
break;
case NM_MULSA_W_PH:
check_dsp_r2(ctx);
- gen_helper_mulsa_w_ph(t0, v0, v1, cpu_env);
+ gen_helper_mulsa_w_ph(t0, v0, v1, tcg_env);
break;
default:
gen_reserved_instruction(ctx);
switch (extract32(ctx->opcode, 9, 3)) {
case NM_DPAU_H_QBR:
check_dsp(ctx);
- gen_helper_dpau_h_qbr(t0, v1, v0, cpu_env);
+ gen_helper_dpau_h_qbr(t0, v1, v0, tcg_env);
break;
case NM_DPAQX_SA_W_PH:
check_dsp_r2(ctx);
- gen_helper_dpaqx_sa_w_ph(t0, v1, v0, cpu_env);
+ gen_helper_dpaqx_sa_w_ph(t0, v1, v0, tcg_env);
break;
case NM_DPSU_H_QBR:
check_dsp(ctx);
- gen_helper_dpsu_h_qbr(t0, v1, v0, cpu_env);
+ gen_helper_dpsu_h_qbr(t0, v1, v0, tcg_env);
break;
case NM_DPSQX_SA_W_PH:
check_dsp_r2(ctx);
- gen_helper_dpsqx_sa_w_ph(t0, v1, v0, cpu_env);
+ gen_helper_dpsqx_sa_w_ph(t0, v1, v0, tcg_env);
break;
case NM_MULSAQ_S_W_PH:
check_dsp(ctx);
- gen_helper_mulsaq_s_w_ph(t0, v1, v0, cpu_env);
+ gen_helper_mulsaq_s_w_ph(t0, v1, v0, tcg_env);
break;
default:
gen_reserved_instruction(ctx);
check_dsp(ctx);
gen_load_gpr(v1_t, rs);
tcg_gen_movi_tl(t0, rd >> 3);
- gen_helper_extr_w(t0, t0, v1_t, cpu_env);
+ gen_helper_extr_w(t0, t0, v1_t, tcg_env);
gen_store_gpr(t0, ret);
break;
}
case NM_EXTRV_R_W:
check_dsp(ctx);
tcg_gen_movi_tl(t0, rd >> 3);
- gen_helper_extr_r_w(t0, t0, v1_t, cpu_env);
+ gen_helper_extr_r_w(t0, t0, v1_t, tcg_env);
gen_store_gpr(t0, ret);
break;
default:
case NM_EXTPV:
check_dsp(ctx);
tcg_gen_movi_tl(t0, rd >> 3);
- gen_helper_extp(t0, t0, v1_t, cpu_env);
+ gen_helper_extp(t0, t0, v1_t, tcg_env);
gen_store_gpr(t0, ret);
break;
case NM_MSUB:
case NM_EXTRV_RS_W:
check_dsp(ctx);
tcg_gen_movi_tl(t0, rd >> 3);
- gen_helper_extr_rs_w(t0, t0, v1_t, cpu_env);
+ gen_helper_extr_rs_w(t0, t0, v1_t, tcg_env);
gen_store_gpr(t0, ret);
break;
}
case NM_EXTPDPV:
check_dsp(ctx);
tcg_gen_movi_tl(t0, rd >> 3);
- gen_helper_extpdp(t0, t0, v1_t, cpu_env);
+ gen_helper_extpdp(t0, t0, v1_t, tcg_env);
gen_store_gpr(t0, ret);
break;
case NM_MSUBU:
case NM_EXTRV_S_H:
check_dsp(ctx);
tcg_gen_movi_tl(t0, rd >> 3);
- gen_helper_extr_s_h(t0, t0, v1_t, cpu_env);
+ gen_helper_extr_s_h(t0, t0, v1_t, tcg_env);
gen_store_gpr(t0, ret);
break;
}
switch (opc) {
case NM_ABSQ_S_QB:
check_dsp_r2(ctx);
- gen_helper_absq_s_qb(v0_t, v0_t, cpu_env);
+ gen_helper_absq_s_qb(v0_t, v0_t, tcg_env);
gen_store_gpr(v0_t, ret);
break;
case NM_ABSQ_S_PH:
check_dsp(ctx);
- gen_helper_absq_s_ph(v0_t, v0_t, cpu_env);
+ gen_helper_absq_s_ph(v0_t, v0_t, tcg_env);
gen_store_gpr(v0_t, ret);
break;
case NM_ABSQ_S_W:
check_dsp(ctx);
- gen_helper_absq_s_w(v0_t, v0_t, cpu_env);
+ gen_helper_absq_s_w(v0_t, v0_t, tcg_env);
gen_store_gpr(v0_t, ret);
break;
case NM_PRECEQ_W_PHL:
TCGv tv0 = tcg_temp_new();
gen_load_gpr(tv0, rt);
- gen_helper_insv(v0_t, cpu_env, v0_t, tv0);
+ gen_helper_insv(v0_t, tcg_env, v0_t, tv0);
gen_store_gpr(v0_t, ret);
}
break;
TCGv t0 = tcg_temp_new();
save_cpu_state(ctx, 1);
- gen_helper_di(t0, cpu_env);
+ gen_helper_di(t0, tcg_env);
gen_store_gpr(t0, rt);
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
TCGv t0 = tcg_temp_new();
save_cpu_state(ctx, 1);
- gen_helper_ei(t0, cpu_env);
+ gen_helper_ei(t0, tcg_env);
gen_store_gpr(t0, rt);
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
switch (opc) {
case NM_CMP_EQ_PH:
check_dsp(ctx);
- gen_helper_cmp_eq_ph(v1_t, v2_t, cpu_env);
+ gen_helper_cmp_eq_ph(v1_t, v2_t, tcg_env);
break;
case NM_CMP_LT_PH:
check_dsp(ctx);
- gen_helper_cmp_lt_ph(v1_t, v2_t, cpu_env);
+ gen_helper_cmp_lt_ph(v1_t, v2_t, tcg_env);
break;
case NM_CMP_LE_PH:
check_dsp(ctx);
- gen_helper_cmp_le_ph(v1_t, v2_t, cpu_env);
+ gen_helper_cmp_le_ph(v1_t, v2_t, tcg_env);
break;
case NM_CMPU_EQ_QB:
check_dsp(ctx);
- gen_helper_cmpu_eq_qb(v1_t, v2_t, cpu_env);
+ gen_helper_cmpu_eq_qb(v1_t, v2_t, tcg_env);
break;
case NM_CMPU_LT_QB:
check_dsp(ctx);
- gen_helper_cmpu_lt_qb(v1_t, v2_t, cpu_env);
+ gen_helper_cmpu_lt_qb(v1_t, v2_t, tcg_env);
break;
case NM_CMPU_LE_QB:
check_dsp(ctx);
- gen_helper_cmpu_le_qb(v1_t, v2_t, cpu_env);
+ gen_helper_cmpu_le_qb(v1_t, v2_t, tcg_env);
break;
case NM_CMPGU_EQ_QB:
check_dsp(ctx);
break;
case NM_PICK_QB:
check_dsp(ctx);
- gen_helper_pick_qb(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_pick_qb(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
case NM_PICK_PH:
check_dsp(ctx);
- gen_helper_pick_ph(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_pick_ph(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
case NM_ADDQ_S_W:
check_dsp(ctx);
- gen_helper_addq_s_w(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_addq_s_w(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
case NM_SUBQ_S_W:
check_dsp(ctx);
- gen_helper_subq_s_w(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_subq_s_w(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
case NM_ADDSC:
check_dsp(ctx);
- gen_helper_addsc(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_addsc(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
case NM_ADDWC:
check_dsp(ctx);
- gen_helper_addwc(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_addwc(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
case NM_ADDQ_S_PH:
switch (extract32(ctx->opcode, 10, 1)) {
case 0:
/* ADDQ_PH */
- gen_helper_addq_ph(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_addq_ph(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
case 1:
/* ADDQ_S_PH */
- gen_helper_addq_s_ph(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_addq_s_ph(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
}
switch (extract32(ctx->opcode, 10, 1)) {
case 0:
/* ADDU_QB */
- gen_helper_addu_qb(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_addu_qb(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
case 1:
/* ADDU_S_QB */
- gen_helper_addu_s_qb(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_addu_s_qb(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
}
switch (extract32(ctx->opcode, 10, 1)) {
case 0:
/* ADDU_PH */
- gen_helper_addu_ph(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_addu_ph(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
case 1:
/* ADDU_S_PH */
- gen_helper_addu_s_ph(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_addu_s_ph(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
}
switch (extract32(ctx->opcode, 10, 1)) {
case 0:
/* SUBQ_PH */
- gen_helper_subq_ph(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_subq_ph(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
case 1:
/* SUBQ_S_PH */
- gen_helper_subq_s_ph(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_subq_s_ph(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
}
switch (extract32(ctx->opcode, 10, 1)) {
case 0:
/* SUBU_QB */
- gen_helper_subu_qb(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_subu_qb(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
case 1:
/* SUBU_S_QB */
- gen_helper_subu_s_qb(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_subu_s_qb(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
}
switch (extract32(ctx->opcode, 10, 1)) {
case 0:
/* SUBU_PH */
- gen_helper_subu_ph(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_subu_ph(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
case 1:
/* SUBU_S_PH */
- gen_helper_subu_s_ph(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_subu_s_ph(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
}
switch (extract32(ctx->opcode, 10, 1)) {
case 0:
/* SHLLV_PH */
- gen_helper_shll_ph(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_shll_ph(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
case 1:
/* SHLLV_S_PH */
- gen_helper_shll_s_ph(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_shll_s_ph(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
}
break;
case NM_MULEU_S_PH_QBL:
check_dsp(ctx);
- gen_helper_muleu_s_ph_qbl(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_muleu_s_ph_qbl(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
case NM_MULEU_S_PH_QBR:
check_dsp(ctx);
- gen_helper_muleu_s_ph_qbr(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_muleu_s_ph_qbr(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
case NM_MULQ_RS_PH:
check_dsp(ctx);
- gen_helper_mulq_rs_ph(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_mulq_rs_ph(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
case NM_MULQ_S_PH:
check_dsp_r2(ctx);
- gen_helper_mulq_s_ph(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_mulq_s_ph(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
case NM_MULQ_RS_W:
check_dsp_r2(ctx);
- gen_helper_mulq_rs_w(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_mulq_rs_w(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
case NM_MULQ_S_W:
check_dsp_r2(ctx);
- gen_helper_mulq_s_w(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_mulq_s_w(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
case NM_APPEND:
break;
case NM_SHLLV_QB:
check_dsp(ctx);
- gen_helper_shll_qb(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_shll_qb(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
case NM_SHLLV_S_W:
check_dsp(ctx);
- gen_helper_shll_s_w(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_shll_s_w(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
case NM_SHILO:
tcg_gen_movi_tl(tv0, rd >> 3);
tcg_gen_movi_tl(tv1, imm);
- gen_helper_shilo(tv0, tv1, cpu_env);
+ gen_helper_shilo(tv0, tv1, tcg_env);
}
break;
case NM_MULEQ_S_W_PHL:
check_dsp(ctx);
- gen_helper_muleq_s_w_phl(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_muleq_s_w_phl(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
case NM_MULEQ_S_W_PHR:
check_dsp(ctx);
- gen_helper_muleq_s_w_phr(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_muleq_s_w_phr(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
case NM_MUL_S_PH:
switch (extract32(ctx->opcode, 10, 1)) {
case 0:
/* MUL_PH */
- gen_helper_mul_ph(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_mul_ph(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
case 1:
/* MUL_S_PH */
- gen_helper_mul_s_ph(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_mul_s_ph(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
}
break;
case NM_PRECRQ_RS_PH_W:
check_dsp(ctx);
- gen_helper_precrq_rs_ph_w(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_precrq_rs_ph_w(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
case NM_PRECRQU_S_QB_PH:
check_dsp(ctx);
- gen_helper_precrqu_s_qb_ph(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_precrqu_s_qb_ph(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
case NM_SHRA_R_W:
switch (extract32(ctx->opcode, 10, 2)) {
case 0:
/* SHLL_PH */
- gen_helper_shll_ph(v1_t, t0, v1_t, cpu_env);
+ gen_helper_shll_ph(v1_t, t0, v1_t, tcg_env);
gen_store_gpr(v1_t, rt);
break;
case 2:
/* SHLL_S_PH */
- gen_helper_shll_s_ph(v1_t, t0, v1_t, cpu_env);
+ gen_helper_shll_s_ph(v1_t, t0, v1_t, tcg_env);
gen_store_gpr(v1_t, rt);
break;
default:
case NM_SHLL_S_W:
check_dsp(ctx);
tcg_gen_movi_tl(t0, rd);
- gen_helper_shll_s_w(v1_t, t0, v1_t, cpu_env);
+ gen_helper_shll_s_w(v1_t, t0, v1_t, tcg_env);
gen_store_gpr(v1_t, rt);
break;
case NM_REPL_PH:
/* make sure instructions are on a halfword boundary */
if (ctx->base.pc_next & 0x1) {
TCGv tmp = tcg_constant_tl(ctx->base.pc_next);
- tcg_gen_st_tl(tmp, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr));
+ tcg_gen_st_tl(tmp, tcg_env, offsetof(CPUMIPSState, CP0_BadVAddr));
generate_exception_end(ctx, EXCP_AdEL);
return 2;
}
TCGv_i32 t2 = tcg_temp_new_i32();
TCGv_ptr addr = tcg_temp_new_ptr();
- tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUMIPSState, CP0_SRSCtl));
+ tcg_gen_ld_i32(t2, tcg_env, offsetof(CPUMIPSState, CP0_SRSCtl));
tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS);
tcg_gen_andi_i32(t2, t2, 0xf);
tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32);
tcg_gen_ext_i32_ptr(addr, t2);
- tcg_gen_add_ptr(addr, cpu_env, addr);
+ tcg_gen_add_ptr(addr, tcg_env, addr);
tcg_gen_ld_tl(t0, addr, sizeof(target_ulong) * from);
}
TCGv_ptr addr = tcg_temp_new_ptr();
gen_load_gpr(t0, from);
- tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUMIPSState, CP0_SRSCtl));
+ tcg_gen_ld_i32(t2, tcg_env, offsetof(CPUMIPSState, CP0_SRSCtl));
tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS);
tcg_gen_andi_i32(t2, t2, 0xf);
tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32);
tcg_gen_ext_i32_ptr(addr, t2);
- tcg_gen_add_ptr(addr, cpu_env, addr);
+ tcg_gen_add_ptr(addr, tcg_env, addr);
tcg_gen_st_tl(t0, addr, sizeof(target_ulong) * to);
}
void generate_exception_err(DisasContext *ctx, int excp, int err)
{
save_cpu_state(ctx, 1);
- gen_helper_raise_exception_err(cpu_env, tcg_constant_i32(excp),
+ gen_helper_raise_exception_err(tcg_env, tcg_constant_i32(excp),
tcg_constant_i32(err));
ctx->base.is_jmp = DISAS_NORETURN;
}
void generate_exception(DisasContext *ctx, int excp)
{
- gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
+ gen_helper_raise_exception(tcg_env, tcg_constant_i32(excp));
}
void generate_exception_end(DisasContext *ctx, int excp)
{
#ifdef CONFIG_USER_ONLY
/* Pass the break code along to cpu_loop. */
- tcg_gen_st_i32(tcg_constant_i32(code), cpu_env,
+ tcg_gen_st_i32(tcg_constant_i32(code), tcg_env,
offsetof(CPUMIPSState, error_code));
#endif
generate_exception_end(ctx, EXCP_BREAK);
gen_ldcmp_fpr ## bits(ctx, fp1, ft); \
switch (n) { \
case 0: \
- gen_helper_r6_cmp_ ## fmt ## _af(fp0, cpu_env, fp0, fp1); \
+ gen_helper_r6_cmp_ ## fmt ## _af(fp0, tcg_env, fp0, fp1); \
break; \
case 1: \
- gen_helper_r6_cmp_ ## fmt ## _un(fp0, cpu_env, fp0, fp1); \
+ gen_helper_r6_cmp_ ## fmt ## _un(fp0, tcg_env, fp0, fp1); \
break; \
case 2: \
- gen_helper_r6_cmp_ ## fmt ## _eq(fp0, cpu_env, fp0, fp1); \
+ gen_helper_r6_cmp_ ## fmt ## _eq(fp0, tcg_env, fp0, fp1); \
break; \
case 3: \
- gen_helper_r6_cmp_ ## fmt ## _ueq(fp0, cpu_env, fp0, fp1); \
+ gen_helper_r6_cmp_ ## fmt ## _ueq(fp0, tcg_env, fp0, fp1); \
break; \
case 4: \
- gen_helper_r6_cmp_ ## fmt ## _lt(fp0, cpu_env, fp0, fp1); \
+ gen_helper_r6_cmp_ ## fmt ## _lt(fp0, tcg_env, fp0, fp1); \
break; \
case 5: \
- gen_helper_r6_cmp_ ## fmt ## _ult(fp0, cpu_env, fp0, fp1); \
+ gen_helper_r6_cmp_ ## fmt ## _ult(fp0, tcg_env, fp0, fp1); \
break; \
case 6: \
- gen_helper_r6_cmp_ ## fmt ## _le(fp0, cpu_env, fp0, fp1); \
+ gen_helper_r6_cmp_ ## fmt ## _le(fp0, tcg_env, fp0, fp1); \
break; \
case 7: \
- gen_helper_r6_cmp_ ## fmt ## _ule(fp0, cpu_env, fp0, fp1); \
+ gen_helper_r6_cmp_ ## fmt ## _ule(fp0, tcg_env, fp0, fp1); \
break; \
case 8: \
- gen_helper_r6_cmp_ ## fmt ## _saf(fp0, cpu_env, fp0, fp1); \
+ gen_helper_r6_cmp_ ## fmt ## _saf(fp0, tcg_env, fp0, fp1); \
break; \
case 9: \
- gen_helper_r6_cmp_ ## fmt ## _sun(fp0, cpu_env, fp0, fp1); \
+ gen_helper_r6_cmp_ ## fmt ## _sun(fp0, tcg_env, fp0, fp1); \
break; \
case 10: \
- gen_helper_r6_cmp_ ## fmt ## _seq(fp0, cpu_env, fp0, fp1); \
+ gen_helper_r6_cmp_ ## fmt ## _seq(fp0, tcg_env, fp0, fp1); \
break; \
case 11: \
- gen_helper_r6_cmp_ ## fmt ## _sueq(fp0, cpu_env, fp0, fp1); \
+ gen_helper_r6_cmp_ ## fmt ## _sueq(fp0, tcg_env, fp0, fp1); \
break; \
case 12: \
- gen_helper_r6_cmp_ ## fmt ## _slt(fp0, cpu_env, fp0, fp1); \
+ gen_helper_r6_cmp_ ## fmt ## _slt(fp0, tcg_env, fp0, fp1); \
break; \
case 13: \
- gen_helper_r6_cmp_ ## fmt ## _sult(fp0, cpu_env, fp0, fp1); \
+ gen_helper_r6_cmp_ ## fmt ## _sult(fp0, tcg_env, fp0, fp1); \
break; \
case 14: \
- gen_helper_r6_cmp_ ## fmt ## _sle(fp0, cpu_env, fp0, fp1); \
+ gen_helper_r6_cmp_ ## fmt ## _sle(fp0, tcg_env, fp0, fp1); \
break; \
case 15: \
- gen_helper_r6_cmp_ ## fmt ## _sule(fp0, cpu_env, fp0, fp1); \
+ gen_helper_r6_cmp_ ## fmt ## _sule(fp0, tcg_env, fp0, fp1); \
break; \
case 17: \
- gen_helper_r6_cmp_ ## fmt ## _or(fp0, cpu_env, fp0, fp1); \
+ gen_helper_r6_cmp_ ## fmt ## _or(fp0, tcg_env, fp0, fp1); \
break; \
case 18: \
- gen_helper_r6_cmp_ ## fmt ## _une(fp0, cpu_env, fp0, fp1); \
+ gen_helper_r6_cmp_ ## fmt ## _une(fp0, tcg_env, fp0, fp1); \
break; \
case 19: \
- gen_helper_r6_cmp_ ## fmt ## _ne(fp0, cpu_env, fp0, fp1); \
+ gen_helper_r6_cmp_ ## fmt ## _ne(fp0, tcg_env, fp0, fp1); \
break; \
case 25: \
- gen_helper_r6_cmp_ ## fmt ## _sor(fp0, cpu_env, fp0, fp1); \
+ gen_helper_r6_cmp_ ## fmt ## _sor(fp0, tcg_env, fp0, fp1); \
break; \
case 26: \
- gen_helper_r6_cmp_ ## fmt ## _sune(fp0, cpu_env, fp0, fp1); \
+ gen_helper_r6_cmp_ ## fmt ## _sune(fp0, tcg_env, fp0, fp1); \
break; \
case 27: \
- gen_helper_r6_cmp_ ## fmt ## _sne(fp0, cpu_env, fp0, fp1); \
+ gen_helper_r6_cmp_ ## fmt ## _sne(fp0, tcg_env, fp0, fp1); \
break; \
default: \
abort(); \
TCGv t0 = tcg_temp_new(); \
tcg_gen_mov_tl(t0, arg1); \
tcg_gen_qemu_ld_tl(ret, arg1, ctx->mem_idx, memop); \
- tcg_gen_st_tl(t0, cpu_env, offsetof(CPUMIPSState, lladdr)); \
- tcg_gen_st_tl(ret, cpu_env, offsetof(CPUMIPSState, llval)); \
+ tcg_gen_st_tl(t0, tcg_env, offsetof(CPUMIPSState, lladdr)); \
+ tcg_gen_st_tl(ret, tcg_env, offsetof(CPUMIPSState, llval)); \
}
#else
#define OP_LD_ATOMIC(insn, fname) \
static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \
DisasContext *ctx) \
{ \
- gen_helper_##insn(ret, cpu_env, arg1, tcg_constant_i32(mem_idx)); \
+ gen_helper_##insn(ret, tcg_env, arg1, tcg_constant_i32(mem_idx)); \
}
#endif
OP_LD_ATOMIC(ll, MO_TESL);
/* Always trap */
#ifdef CONFIG_USER_ONLY
/* Pass the break code along to cpu_loop. */
- tcg_gen_st_i32(tcg_constant_i32(code), cpu_env,
+ tcg_gen_st_i32(tcg_constant_i32(code), tcg_env,
offsetof(CPUMIPSState, error_code));
#endif
generate_exception_end(ctx, EXCP_TRAP);
}
#ifdef CONFIG_USER_ONLY
/* Pass the break code along to cpu_loop. */
- tcg_gen_st_i32(tcg_constant_i32(code), cpu_env,
+ tcg_gen_st_i32(tcg_constant_i32(code), tcg_env,
offsetof(CPUMIPSState, error_code));
#endif
/* Like save_cpu_state, only don't update saved values. */
TCGv_i64 t1 = tcg_temp_new_i64();
tcg_gen_ext_tl_i64(t0, arg);
- tcg_gen_ld_i64(t1, cpu_env, off);
+ tcg_gen_ld_i64(t1, tcg_env, off);
#if defined(TARGET_MIPS64)
tcg_gen_deposit_i64(t1, t1, t0, 30, 32);
#else
tcg_gen_concat32_i64(t1, t1, t0);
#endif
- tcg_gen_st_i64(t1, cpu_env, off);
+ tcg_gen_st_i64(t1, tcg_env, off);
}
static inline void gen_mthc0_store64(TCGv arg, target_ulong off)
TCGv_i64 t1 = tcg_temp_new_i64();
tcg_gen_ext_tl_i64(t0, arg);
- tcg_gen_ld_i64(t1, cpu_env, off);
+ tcg_gen_ld_i64(t1, tcg_env, off);
tcg_gen_concat32_i64(t1, t1, t0);
- tcg_gen_st_i64(t1, cpu_env, off);
+ tcg_gen_st_i64(t1, tcg_env, off);
}
static inline void gen_mfhc0_entrylo(TCGv arg, target_ulong off)
{
TCGv_i64 t0 = tcg_temp_new_i64();
- tcg_gen_ld_i64(t0, cpu_env, off);
+ tcg_gen_ld_i64(t0, tcg_env, off);
#if defined(TARGET_MIPS64)
tcg_gen_shri_i64(t0, t0, 30);
#else
{
TCGv_i64 t0 = tcg_temp_new_i64();
- tcg_gen_ld_i64(t0, cpu_env, off);
+ tcg_gen_ld_i64(t0, tcg_env, off);
tcg_gen_shri_i64(t0, t0, 32 + shift);
gen_move_low32(arg, t0);
}
{
TCGv_i32 t0 = tcg_temp_new_i32();
- tcg_gen_ld_i32(t0, cpu_env, off);
+ tcg_gen_ld_i32(t0, tcg_env, off);
tcg_gen_ext_i32_tl(arg, t0);
}
static inline void gen_mfc0_load64(TCGv arg, target_ulong off)
{
- tcg_gen_ld_tl(arg, cpu_env, off);
+ tcg_gen_ld_tl(arg, tcg_env, off);
tcg_gen_ext32s_tl(arg, arg);
}
TCGv_i32 t0 = tcg_temp_new_i32();
tcg_gen_trunc_tl_i32(t0, arg);
- tcg_gen_st_i32(t0, cpu_env, off);
+ tcg_gen_st_i32(t0, tcg_env, off);
}
#define CP0_CHECK(c) \
switch (sel) {
case CP0_REG09__SAAR:
CP0_CHECK(ctx->saar);
- gen_helper_mfhc0_saar(arg, cpu_env);
+ gen_helper_mfhc0_saar(arg, tcg_env);
register_name = "SAAR";
break;
default:
break;
case CP0_REG17__MAAR:
CP0_CHECK(ctx->mrp);
- gen_helper_mfhc0_maar(arg, cpu_env);
+ gen_helper_mfhc0_maar(arg, tcg_env);
register_name = "MAAR";
break;
default:
switch (sel) {
case CP0_REG09__SAAR:
CP0_CHECK(ctx->saar);
- gen_helper_mthc0_saar(cpu_env, arg);
+ gen_helper_mthc0_saar(tcg_env, arg);
register_name = "SAAR";
break;
default:
break;
case CP0_REG17__MAAR:
CP0_CHECK(ctx->mrp);
- gen_helper_mthc0_maar(cpu_env, arg);
+ gen_helper_mthc0_maar(tcg_env, arg);
register_name = "MAAR";
break;
default:
break;
case CP0_REG00__MVPCONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mfc0_mvpcontrol(arg, cpu_env);
+ gen_helper_mfc0_mvpcontrol(arg, tcg_env);
register_name = "MVPControl";
break;
case CP0_REG00__MVPCONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mfc0_mvpconf0(arg, cpu_env);
+ gen_helper_mfc0_mvpconf0(arg, tcg_env);
register_name = "MVPConf0";
break;
case CP0_REG00__MVPCONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mfc0_mvpconf1(arg, cpu_env);
+ gen_helper_mfc0_mvpconf1(arg, tcg_env);
register_name = "MVPConf1";
break;
case CP0_REG00__VPCONTROL:
switch (sel) {
case CP0_REG01__RANDOM:
CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6));
- gen_helper_mfc0_random(arg, cpu_env);
+ gen_helper_mfc0_random(arg, tcg_env);
register_name = "Random";
break;
case CP0_REG01__VPECONTROL:
case CP0_REG02__ENTRYLO0:
{
TCGv_i64 tmp = tcg_temp_new_i64();
- tcg_gen_ld_i64(tmp, cpu_env,
+ tcg_gen_ld_i64(tmp, tcg_env,
offsetof(CPUMIPSState, CP0_EntryLo0));
#if defined(TARGET_MIPS64)
if (ctx->rxi) {
break;
case CP0_REG02__TCSTATUS:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mfc0_tcstatus(arg, cpu_env);
+ gen_helper_mfc0_tcstatus(arg, tcg_env);
register_name = "TCStatus";
break;
case CP0_REG02__TCBIND:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mfc0_tcbind(arg, cpu_env);
+ gen_helper_mfc0_tcbind(arg, tcg_env);
register_name = "TCBind";
break;
case CP0_REG02__TCRESTART:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mfc0_tcrestart(arg, cpu_env);
+ gen_helper_mfc0_tcrestart(arg, tcg_env);
register_name = "TCRestart";
break;
case CP0_REG02__TCHALT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mfc0_tchalt(arg, cpu_env);
+ gen_helper_mfc0_tchalt(arg, tcg_env);
register_name = "TCHalt";
break;
case CP0_REG02__TCCONTEXT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mfc0_tccontext(arg, cpu_env);
+ gen_helper_mfc0_tccontext(arg, tcg_env);
register_name = "TCContext";
break;
case CP0_REG02__TCSCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mfc0_tcschedule(arg, cpu_env);
+ gen_helper_mfc0_tcschedule(arg, tcg_env);
register_name = "TCSchedule";
break;
case CP0_REG02__TCSCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mfc0_tcschefback(arg, cpu_env);
+ gen_helper_mfc0_tcschefback(arg, tcg_env);
register_name = "TCScheFBack";
break;
default:
case CP0_REG03__ENTRYLO1:
{
TCGv_i64 tmp = tcg_temp_new_i64();
- tcg_gen_ld_i64(tmp, cpu_env,
+ tcg_gen_ld_i64(tmp, tcg_env,
offsetof(CPUMIPSState, CP0_EntryLo1));
#if defined(TARGET_MIPS64)
if (ctx->rxi) {
case CP0_REGISTER_04:
switch (sel) {
case CP0_REG04__CONTEXT:
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_Context));
+ tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_Context));
tcg_gen_ext32s_tl(arg, arg);
register_name = "Context";
break;
goto cp0_unimplemented;
case CP0_REG04__USERLOCAL:
CP0_CHECK(ctx->ulri);
- tcg_gen_ld_tl(arg, cpu_env,
+ tcg_gen_ld_tl(arg, tcg_env,
offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
tcg_gen_ext32s_tl(arg, arg);
register_name = "UserLocal";
break;
case CP0_REG04__MMID:
CP0_CHECK(ctx->mi);
- gen_helper_mtc0_memorymapid(cpu_env, arg);
+ gen_helper_mtc0_memorymapid(tcg_env, arg);
register_name = "MMID";
break;
default:
break;
case CP0_REG05__SEGCTL0:
CP0_CHECK(ctx->sc);
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl0));
+ tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_SegCtl0));
tcg_gen_ext32s_tl(arg, arg);
register_name = "SegCtl0";
break;
case CP0_REG05__SEGCTL1:
CP0_CHECK(ctx->sc);
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl1));
+ tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_SegCtl1));
tcg_gen_ext32s_tl(arg, arg);
register_name = "SegCtl1";
break;
case CP0_REG05__SEGCTL2:
CP0_CHECK(ctx->sc);
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl2));
+ tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_SegCtl2));
tcg_gen_ext32s_tl(arg, arg);
register_name = "SegCtl2";
break;
case CP0_REGISTER_08:
switch (sel) {
case CP0_REG08__BADVADDR:
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr));
+ tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_BadVAddr));
tcg_gen_ext32s_tl(arg, arg);
register_name = "BadVAddr";
break;
/* Mark as an IO operation because we read the time. */
translator_io_start(&ctx->base);
- gen_helper_mfc0_count(arg, cpu_env);
+ gen_helper_mfc0_count(arg, tcg_env);
/*
* Break the TB to be able to take timer interrupts immediately
* after reading count. DISAS_STOP isn't sufficient, we need to
break;
case CP0_REG09__SAAR:
CP0_CHECK(ctx->saar);
- gen_helper_mfc0_saar(arg, cpu_env);
+ gen_helper_mfc0_saar(arg, tcg_env);
register_name = "SAAR";
break;
default:
case CP0_REGISTER_10:
switch (sel) {
case CP0_REG10__ENTRYHI:
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryHi));
+ tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_EntryHi));
tcg_gen_ext32s_tl(arg, arg);
register_name = "EntryHi";
break;
case CP0_REGISTER_14:
switch (sel) {
case CP0_REG14__EPC:
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
+ tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_EPC));
tcg_gen_ext32s_tl(arg, arg);
register_name = "EPC";
break;
break;
case CP0_REG15__EBASE:
check_insn(ctx, ISA_MIPS_R2);
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase));
+ tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_EBase));
tcg_gen_ext32s_tl(arg, arg);
register_name = "EBase";
break;
case CP0_REG15__CMGCRBASE:
check_insn(ctx, ISA_MIPS_R2);
CP0_CHECK(ctx->cmgcr);
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase));
+ tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_CMGCRBase));
tcg_gen_ext32s_tl(arg, arg);
register_name = "CMGCRBase";
break;
case CP0_REGISTER_17:
switch (sel) {
case CP0_REG17__LLADDR:
- gen_helper_mfc0_lladdr(arg, cpu_env);
+ gen_helper_mfc0_lladdr(arg, tcg_env);
register_name = "LLAddr";
break;
case CP0_REG17__MAAR:
CP0_CHECK(ctx->mrp);
- gen_helper_mfc0_maar(arg, cpu_env);
+ gen_helper_mfc0_maar(arg, tcg_env);
register_name = "MAAR";
break;
case CP0_REG17__MAARI:
case CP0_REG20__XCONTEXT:
#if defined(TARGET_MIPS64)
check_insn(ctx, ISA_MIPS3);
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_XContext));
+ tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_XContext));
tcg_gen_ext32s_tl(arg, arg);
register_name = "XContext";
break;
case CP0_REGISTER_23:
switch (sel) {
case CP0_REG23__DEBUG:
- gen_helper_mfc0_debug(arg, cpu_env); /* EJTAG support */
+ gen_helper_mfc0_debug(arg, tcg_env); /* EJTAG support */
register_name = "Debug";
break;
case CP0_REG23__TRACECONTROL:
switch (sel) {
case CP0_REG24__DEPC:
/* EJTAG support */
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
+ tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_DEPC));
tcg_gen_ext32s_tl(arg, arg);
register_name = "DEPC";
break;
case CP0_REG28__TAGLO3:
{
TCGv_i64 tmp = tcg_temp_new_i64();
- tcg_gen_ld_i64(tmp, cpu_env, offsetof(CPUMIPSState, CP0_TagLo));
+ tcg_gen_ld_i64(tmp, tcg_env, offsetof(CPUMIPSState, CP0_TagLo));
gen_move_low32(arg, tmp);
}
register_name = "TagLo";
case CP0_REGISTER_30:
switch (sel) {
case CP0_REG30__ERROREPC:
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
+ tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
tcg_gen_ext32s_tl(arg, arg);
register_name = "ErrorEPC";
break;
case CP0_REG31__KSCRATCH5:
case CP0_REG31__KSCRATCH6:
CP0_CHECK(ctx->kscrexist & (1 << sel));
- tcg_gen_ld_tl(arg, cpu_env,
+ tcg_gen_ld_tl(arg, tcg_env,
offsetof(CPUMIPSState, CP0_KScratch[sel - 2]));
tcg_gen_ext32s_tl(arg, arg);
register_name = "KScratch";
case CP0_REGISTER_00:
switch (sel) {
case CP0_REG00__INDEX:
- gen_helper_mtc0_index(cpu_env, arg);
+ gen_helper_mtc0_index(tcg_env, arg);
register_name = "Index";
break;
case CP0_REG00__MVPCONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mtc0_mvpcontrol(cpu_env, arg);
+ gen_helper_mtc0_mvpcontrol(tcg_env, arg);
register_name = "MVPControl";
break;
case CP0_REG00__MVPCONF0:
break;
case CP0_REG01__VPECONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mtc0_vpecontrol(cpu_env, arg);
+ gen_helper_mtc0_vpecontrol(tcg_env, arg);
register_name = "VPEControl";
break;
case CP0_REG01__VPECONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mtc0_vpeconf0(cpu_env, arg);
+ gen_helper_mtc0_vpeconf0(tcg_env, arg);
register_name = "VPEConf0";
break;
case CP0_REG01__VPECONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mtc0_vpeconf1(cpu_env, arg);
+ gen_helper_mtc0_vpeconf1(tcg_env, arg);
register_name = "VPEConf1";
break;
case CP0_REG01__YQMASK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mtc0_yqmask(cpu_env, arg);
+ gen_helper_mtc0_yqmask(tcg_env, arg);
register_name = "YQMask";
break;
case CP0_REG01__VPESCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- tcg_gen_st_tl(arg, cpu_env,
+ tcg_gen_st_tl(arg, tcg_env,
offsetof(CPUMIPSState, CP0_VPESchedule));
register_name = "VPESchedule";
break;
case CP0_REG01__VPESCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- tcg_gen_st_tl(arg, cpu_env,
+ tcg_gen_st_tl(arg, tcg_env,
offsetof(CPUMIPSState, CP0_VPEScheFBack));
register_name = "VPEScheFBack";
break;
case CP0_REG01__VPEOPT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mtc0_vpeopt(cpu_env, arg);
+ gen_helper_mtc0_vpeopt(tcg_env, arg);
register_name = "VPEOpt";
break;
default:
case CP0_REGISTER_02:
switch (sel) {
case CP0_REG02__ENTRYLO0:
- gen_helper_mtc0_entrylo0(cpu_env, arg);
+ gen_helper_mtc0_entrylo0(tcg_env, arg);
register_name = "EntryLo0";
break;
case CP0_REG02__TCSTATUS:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mtc0_tcstatus(cpu_env, arg);
+ gen_helper_mtc0_tcstatus(tcg_env, arg);
register_name = "TCStatus";
break;
case CP0_REG02__TCBIND:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mtc0_tcbind(cpu_env, arg);
+ gen_helper_mtc0_tcbind(tcg_env, arg);
register_name = "TCBind";
break;
case CP0_REG02__TCRESTART:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mtc0_tcrestart(cpu_env, arg);
+ gen_helper_mtc0_tcrestart(tcg_env, arg);
register_name = "TCRestart";
break;
case CP0_REG02__TCHALT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mtc0_tchalt(cpu_env, arg);
+ gen_helper_mtc0_tchalt(tcg_env, arg);
register_name = "TCHalt";
break;
case CP0_REG02__TCCONTEXT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mtc0_tccontext(cpu_env, arg);
+ gen_helper_mtc0_tccontext(tcg_env, arg);
register_name = "TCContext";
break;
case CP0_REG02__TCSCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mtc0_tcschedule(cpu_env, arg);
+ gen_helper_mtc0_tcschedule(tcg_env, arg);
register_name = "TCSchedule";
break;
case CP0_REG02__TCSCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mtc0_tcschefback(cpu_env, arg);
+ gen_helper_mtc0_tcschefback(tcg_env, arg);
register_name = "TCScheFBack";
break;
default:
case CP0_REGISTER_03:
switch (sel) {
case CP0_REG03__ENTRYLO1:
- gen_helper_mtc0_entrylo1(cpu_env, arg);
+ gen_helper_mtc0_entrylo1(tcg_env, arg);
register_name = "EntryLo1";
break;
case CP0_REG03__GLOBALNUM:
case CP0_REGISTER_04:
switch (sel) {
case CP0_REG04__CONTEXT:
- gen_helper_mtc0_context(cpu_env, arg);
+ gen_helper_mtc0_context(tcg_env, arg);
register_name = "Context";
break;
case CP0_REG04__CONTEXTCONFIG:
goto cp0_unimplemented;
case CP0_REG04__USERLOCAL:
CP0_CHECK(ctx->ulri);
- tcg_gen_st_tl(arg, cpu_env,
+ tcg_gen_st_tl(arg, tcg_env,
offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
register_name = "UserLocal";
break;
case CP0_REGISTER_05:
switch (sel) {
case CP0_REG05__PAGEMASK:
- gen_helper_mtc0_pagemask(cpu_env, arg);
+ gen_helper_mtc0_pagemask(tcg_env, arg);
register_name = "PageMask";
break;
case CP0_REG05__PAGEGRAIN:
check_insn(ctx, ISA_MIPS_R2);
- gen_helper_mtc0_pagegrain(cpu_env, arg);
+ gen_helper_mtc0_pagegrain(tcg_env, arg);
register_name = "PageGrain";
ctx->base.is_jmp = DISAS_STOP;
break;
case CP0_REG05__SEGCTL0:
CP0_CHECK(ctx->sc);
- gen_helper_mtc0_segctl0(cpu_env, arg);
+ gen_helper_mtc0_segctl0(tcg_env, arg);
register_name = "SegCtl0";
break;
case CP0_REG05__SEGCTL1:
CP0_CHECK(ctx->sc);
- gen_helper_mtc0_segctl1(cpu_env, arg);
+ gen_helper_mtc0_segctl1(tcg_env, arg);
register_name = "SegCtl1";
break;
case CP0_REG05__SEGCTL2:
CP0_CHECK(ctx->sc);
- gen_helper_mtc0_segctl2(cpu_env, arg);
+ gen_helper_mtc0_segctl2(tcg_env, arg);
register_name = "SegCtl2";
break;
case CP0_REG05__PWBASE:
break;
case CP0_REG05__PWFIELD:
check_pw(ctx);
- gen_helper_mtc0_pwfield(cpu_env, arg);
+ gen_helper_mtc0_pwfield(tcg_env, arg);
register_name = "PWField";
break;
case CP0_REG05__PWSIZE:
check_pw(ctx);
- gen_helper_mtc0_pwsize(cpu_env, arg);
+ gen_helper_mtc0_pwsize(tcg_env, arg);
register_name = "PWSize";
break;
default:
case CP0_REGISTER_06:
switch (sel) {
case CP0_REG06__WIRED:
- gen_helper_mtc0_wired(cpu_env, arg);
+ gen_helper_mtc0_wired(tcg_env, arg);
register_name = "Wired";
break;
case CP0_REG06__SRSCONF0:
check_insn(ctx, ISA_MIPS_R2);
- gen_helper_mtc0_srsconf0(cpu_env, arg);
+ gen_helper_mtc0_srsconf0(tcg_env, arg);
register_name = "SRSConf0";
break;
case CP0_REG06__SRSCONF1:
check_insn(ctx, ISA_MIPS_R2);
- gen_helper_mtc0_srsconf1(cpu_env, arg);
+ gen_helper_mtc0_srsconf1(tcg_env, arg);
register_name = "SRSConf1";
break;
case CP0_REG06__SRSCONF2:
check_insn(ctx, ISA_MIPS_R2);
- gen_helper_mtc0_srsconf2(cpu_env, arg);
+ gen_helper_mtc0_srsconf2(tcg_env, arg);
register_name = "SRSConf2";
break;
case CP0_REG06__SRSCONF3:
check_insn(ctx, ISA_MIPS_R2);
- gen_helper_mtc0_srsconf3(cpu_env, arg);
+ gen_helper_mtc0_srsconf3(tcg_env, arg);
register_name = "SRSConf3";
break;
case CP0_REG06__SRSCONF4:
check_insn(ctx, ISA_MIPS_R2);
- gen_helper_mtc0_srsconf4(cpu_env, arg);
+ gen_helper_mtc0_srsconf4(tcg_env, arg);
register_name = "SRSConf4";
break;
case CP0_REG06__PWCTL:
check_pw(ctx);
- gen_helper_mtc0_pwctl(cpu_env, arg);
+ gen_helper_mtc0_pwctl(tcg_env, arg);
register_name = "PWCtl";
break;
default:
switch (sel) {
case CP0_REG07__HWRENA:
check_insn(ctx, ISA_MIPS_R2);
- gen_helper_mtc0_hwrena(cpu_env, arg);
+ gen_helper_mtc0_hwrena(tcg_env, arg);
ctx->base.is_jmp = DISAS_STOP;
register_name = "HWREna";
break;
case CP0_REGISTER_09:
switch (sel) {
case CP0_REG09__COUNT:
- gen_helper_mtc0_count(cpu_env, arg);
+ gen_helper_mtc0_count(tcg_env, arg);
register_name = "Count";
break;
case CP0_REG09__SAARI:
CP0_CHECK(ctx->saar);
- gen_helper_mtc0_saari(cpu_env, arg);
+ gen_helper_mtc0_saari(tcg_env, arg);
register_name = "SAARI";
break;
case CP0_REG09__SAAR:
CP0_CHECK(ctx->saar);
- gen_helper_mtc0_saar(cpu_env, arg);
+ gen_helper_mtc0_saar(tcg_env, arg);
register_name = "SAAR";
break;
default:
case CP0_REGISTER_10:
switch (sel) {
case CP0_REG10__ENTRYHI:
- gen_helper_mtc0_entryhi(cpu_env, arg);
+ gen_helper_mtc0_entryhi(tcg_env, arg);
register_name = "EntryHi";
break;
default:
case CP0_REGISTER_11:
switch (sel) {
case CP0_REG11__COMPARE:
- gen_helper_mtc0_compare(cpu_env, arg);
+ gen_helper_mtc0_compare(tcg_env, arg);
register_name = "Compare";
break;
/* 6,7 are implementation dependent */
switch (sel) {
case CP0_REG12__STATUS:
save_cpu_state(ctx, 1);
- gen_helper_mtc0_status(cpu_env, arg);
+ gen_helper_mtc0_status(tcg_env, arg);
/* DISAS_STOP isn't good enough here, hflags may have changed. */
gen_save_pc(ctx->base.pc_next + 4);
ctx->base.is_jmp = DISAS_EXIT;
break;
case CP0_REG12__INTCTL:
check_insn(ctx, ISA_MIPS_R2);
- gen_helper_mtc0_intctl(cpu_env, arg);
+ gen_helper_mtc0_intctl(tcg_env, arg);
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "IntCtl";
break;
case CP0_REG12__SRSCTL:
check_insn(ctx, ISA_MIPS_R2);
- gen_helper_mtc0_srsctl(cpu_env, arg);
+ gen_helper_mtc0_srsctl(tcg_env, arg);
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "SRSCtl";
switch (sel) {
case CP0_REG13__CAUSE:
save_cpu_state(ctx, 1);
- gen_helper_mtc0_cause(cpu_env, arg);
+ gen_helper_mtc0_cause(tcg_env, arg);
/*
* Stop translation as we may have triggered an interrupt.
* DISAS_STOP isn't sufficient, we need to ensure we break out of
case CP0_REGISTER_14:
switch (sel) {
case CP0_REG14__EPC:
- tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
+ tcg_gen_st_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_EPC));
register_name = "EPC";
break;
default:
break;
case CP0_REG15__EBASE:
check_insn(ctx, ISA_MIPS_R2);
- gen_helper_mtc0_ebase(cpu_env, arg);
+ gen_helper_mtc0_ebase(tcg_env, arg);
register_name = "EBase";
break;
default:
case CP0_REGISTER_16:
switch (sel) {
case CP0_REG16__CONFIG:
- gen_helper_mtc0_config0(cpu_env, arg);
+ gen_helper_mtc0_config0(tcg_env, arg);
register_name = "Config";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "Config1";
break;
case CP0_REG16__CONFIG2:
- gen_helper_mtc0_config2(cpu_env, arg);
+ gen_helper_mtc0_config2(tcg_env, arg);
register_name = "Config2";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
case CP0_REG16__CONFIG3:
- gen_helper_mtc0_config3(cpu_env, arg);
+ gen_helper_mtc0_config3(tcg_env, arg);
register_name = "Config3";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
case CP0_REG16__CONFIG4:
- gen_helper_mtc0_config4(cpu_env, arg);
+ gen_helper_mtc0_config4(tcg_env, arg);
register_name = "Config4";
ctx->base.is_jmp = DISAS_STOP;
break;
case CP0_REG16__CONFIG5:
- gen_helper_mtc0_config5(cpu_env, arg);
+ gen_helper_mtc0_config5(tcg_env, arg);
register_name = "Config5";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
case CP0_REGISTER_17:
switch (sel) {
case CP0_REG17__LLADDR:
- gen_helper_mtc0_lladdr(cpu_env, arg);
+ gen_helper_mtc0_lladdr(tcg_env, arg);
register_name = "LLAddr";
break;
case CP0_REG17__MAAR:
CP0_CHECK(ctx->mrp);
- gen_helper_mtc0_maar(cpu_env, arg);
+ gen_helper_mtc0_maar(tcg_env, arg);
register_name = "MAAR";
break;
case CP0_REG17__MAARI:
CP0_CHECK(ctx->mrp);
- gen_helper_mtc0_maari(cpu_env, arg);
+ gen_helper_mtc0_maari(tcg_env, arg);
register_name = "MAARI";
break;
default:
case CP0_REG20__XCONTEXT:
#if defined(TARGET_MIPS64)
check_insn(ctx, ISA_MIPS3);
- gen_helper_mtc0_xcontext(cpu_env, arg);
+ gen_helper_mtc0_xcontext(tcg_env, arg);
register_name = "XContext";
break;
#endif
CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6));
switch (sel) {
case 0:
- gen_helper_mtc0_framemask(cpu_env, arg);
+ gen_helper_mtc0_framemask(tcg_env, arg);
register_name = "Framemask";
break;
default:
case CP0_REGISTER_23:
switch (sel) {
case CP0_REG23__DEBUG:
- gen_helper_mtc0_debug(cpu_env, arg); /* EJTAG support */
+ gen_helper_mtc0_debug(tcg_env, arg); /* EJTAG support */
/* DISAS_STOP isn't good enough here, hflags may have changed. */
gen_save_pc(ctx->base.pc_next + 4);
ctx->base.is_jmp = DISAS_EXIT;
break;
case CP0_REG23__TRACECONTROL:
/* PDtrace support */
- /* gen_helper_mtc0_tracecontrol(cpu_env, arg); */
+ /* gen_helper_mtc0_tracecontrol(tcg_env, arg); */
register_name = "TraceControl";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
goto cp0_unimplemented;
case CP0_REG23__TRACECONTROL2:
/* PDtrace support */
- /* gen_helper_mtc0_tracecontrol2(cpu_env, arg); */
+ /* gen_helper_mtc0_tracecontrol2(tcg_env, arg); */
register_name = "TraceControl2";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
/* PDtrace support */
- /* gen_helper_mtc0_usertracedata1(cpu_env, arg);*/
+ /* gen_helper_mtc0_usertracedata1(tcg_env, arg);*/
register_name = "UserTraceData";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
goto cp0_unimplemented;
case CP0_REG23__TRACEIBPC:
/* PDtrace support */
- /* gen_helper_mtc0_traceibpc(cpu_env, arg); */
+ /* gen_helper_mtc0_traceibpc(tcg_env, arg); */
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "TraceIBPC";
goto cp0_unimplemented;
case CP0_REG23__TRACEDBPC:
/* PDtrace support */
- /* gen_helper_mtc0_tracedbpc(cpu_env, arg); */
+ /* gen_helper_mtc0_tracedbpc(tcg_env, arg); */
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "TraceDBPC";
switch (sel) {
case CP0_REG24__DEPC:
/* EJTAG support */
- tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
+ tcg_gen_st_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_DEPC));
register_name = "DEPC";
break;
default:
case CP0_REGISTER_25:
switch (sel) {
case CP0_REG25__PERFCTL0:
- gen_helper_mtc0_performance0(cpu_env, arg);
+ gen_helper_mtc0_performance0(tcg_env, arg);
register_name = "Performance0";
break;
case CP0_REG25__PERFCNT0:
case CP0_REGISTER_26:
switch (sel) {
case CP0_REG26__ERRCTL:
- gen_helper_mtc0_errctl(cpu_env, arg);
+ gen_helper_mtc0_errctl(tcg_env, arg);
ctx->base.is_jmp = DISAS_STOP;
register_name = "ErrCtl";
break;
case CP0_REG28__TAGLO1:
case CP0_REG28__TAGLO2:
case CP0_REG28__TAGLO3:
- gen_helper_mtc0_taglo(cpu_env, arg);
+ gen_helper_mtc0_taglo(tcg_env, arg);
register_name = "TagLo";
break;
case CP0_REG28__DATALO:
case CP0_REG28__DATALO1:
case CP0_REG28__DATALO2:
case CP0_REG28__DATALO3:
- gen_helper_mtc0_datalo(cpu_env, arg);
+ gen_helper_mtc0_datalo(tcg_env, arg);
register_name = "DataLo";
break;
default:
case CP0_REG29__TAGHI1:
case CP0_REG29__TAGHI2:
case CP0_REG29__TAGHI3:
- gen_helper_mtc0_taghi(cpu_env, arg);
+ gen_helper_mtc0_taghi(tcg_env, arg);
register_name = "TagHi";
break;
case CP0_REG29__DATAHI:
case CP0_REG29__DATAHI1:
case CP0_REG29__DATAHI2:
case CP0_REG29__DATAHI3:
- gen_helper_mtc0_datahi(cpu_env, arg);
+ gen_helper_mtc0_datahi(tcg_env, arg);
register_name = "DataHi";
break;
default:
case CP0_REGISTER_30:
switch (sel) {
case CP0_REG30__ERROREPC:
- tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
+ tcg_gen_st_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
register_name = "ErrorEPC";
break;
default:
case CP0_REG31__KSCRATCH5:
case CP0_REG31__KSCRATCH6:
CP0_CHECK(ctx->kscrexist & (1 << sel));
- tcg_gen_st_tl(arg, cpu_env,
+ tcg_gen_st_tl(arg, tcg_env,
offsetof(CPUMIPSState, CP0_KScratch[sel - 2]));
register_name = "KScratch";
break;
break;
case CP0_REG00__MVPCONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mfc0_mvpcontrol(arg, cpu_env);
+ gen_helper_mfc0_mvpcontrol(arg, tcg_env);
register_name = "MVPControl";
break;
case CP0_REG00__MVPCONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mfc0_mvpconf0(arg, cpu_env);
+ gen_helper_mfc0_mvpconf0(arg, tcg_env);
register_name = "MVPConf0";
break;
case CP0_REG00__MVPCONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mfc0_mvpconf1(arg, cpu_env);
+ gen_helper_mfc0_mvpconf1(arg, tcg_env);
register_name = "MVPConf1";
break;
case CP0_REG00__VPCONTROL:
switch (sel) {
case CP0_REG01__RANDOM:
CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6));
- gen_helper_mfc0_random(arg, cpu_env);
+ gen_helper_mfc0_random(arg, tcg_env);
register_name = "Random";
break;
case CP0_REG01__VPECONTROL:
break;
case CP0_REG01__YQMASK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- tcg_gen_ld_tl(arg, cpu_env,
+ tcg_gen_ld_tl(arg, tcg_env,
offsetof(CPUMIPSState, CP0_YQMask));
register_name = "YQMask";
break;
case CP0_REG01__VPESCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- tcg_gen_ld_tl(arg, cpu_env,
+ tcg_gen_ld_tl(arg, tcg_env,
offsetof(CPUMIPSState, CP0_VPESchedule));
register_name = "VPESchedule";
break;
case CP0_REG01__VPESCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- tcg_gen_ld_tl(arg, cpu_env,
+ tcg_gen_ld_tl(arg, tcg_env,
offsetof(CPUMIPSState, CP0_VPEScheFBack));
register_name = "VPEScheFBack";
break;
case CP0_REGISTER_02:
switch (sel) {
case CP0_REG02__ENTRYLO0:
- tcg_gen_ld_tl(arg, cpu_env,
+ tcg_gen_ld_tl(arg, tcg_env,
offsetof(CPUMIPSState, CP0_EntryLo0));
register_name = "EntryLo0";
break;
case CP0_REG02__TCSTATUS:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mfc0_tcstatus(arg, cpu_env);
+ gen_helper_mfc0_tcstatus(arg, tcg_env);
register_name = "TCStatus";
break;
case CP0_REG02__TCBIND:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mfc0_tcbind(arg, cpu_env);
+ gen_helper_mfc0_tcbind(arg, tcg_env);
register_name = "TCBind";
break;
case CP0_REG02__TCRESTART:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_dmfc0_tcrestart(arg, cpu_env);
+ gen_helper_dmfc0_tcrestart(arg, tcg_env);
register_name = "TCRestart";
break;
case CP0_REG02__TCHALT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_dmfc0_tchalt(arg, cpu_env);
+ gen_helper_dmfc0_tchalt(arg, tcg_env);
register_name = "TCHalt";
break;
case CP0_REG02__TCCONTEXT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_dmfc0_tccontext(arg, cpu_env);
+ gen_helper_dmfc0_tccontext(arg, tcg_env);
register_name = "TCContext";
break;
case CP0_REG02__TCSCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_dmfc0_tcschedule(arg, cpu_env);
+ gen_helper_dmfc0_tcschedule(arg, tcg_env);
register_name = "TCSchedule";
break;
case CP0_REG02__TCSCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_dmfc0_tcschefback(arg, cpu_env);
+ gen_helper_dmfc0_tcschefback(arg, tcg_env);
register_name = "TCScheFBack";
break;
default:
case CP0_REGISTER_03:
switch (sel) {
case CP0_REG03__ENTRYLO1:
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo1));
+ tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_EntryLo1));
register_name = "EntryLo1";
break;
case CP0_REG03__GLOBALNUM:
case CP0_REGISTER_04:
switch (sel) {
case CP0_REG04__CONTEXT:
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_Context));
+ tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_Context));
register_name = "Context";
break;
case CP0_REG04__CONTEXTCONFIG:
goto cp0_unimplemented;
case CP0_REG04__USERLOCAL:
CP0_CHECK(ctx->ulri);
- tcg_gen_ld_tl(arg, cpu_env,
+ tcg_gen_ld_tl(arg, tcg_env,
offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
register_name = "UserLocal";
break;
case CP0_REG04__MMID:
CP0_CHECK(ctx->mi);
- gen_helper_mtc0_memorymapid(cpu_env, arg);
+ gen_helper_mtc0_memorymapid(tcg_env, arg);
register_name = "MMID";
break;
default:
break;
case CP0_REG05__SEGCTL0:
CP0_CHECK(ctx->sc);
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl0));
+ tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_SegCtl0));
register_name = "SegCtl0";
break;
case CP0_REG05__SEGCTL1:
CP0_CHECK(ctx->sc);
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl1));
+ tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_SegCtl1));
register_name = "SegCtl1";
break;
case CP0_REG05__SEGCTL2:
CP0_CHECK(ctx->sc);
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl2));
+ tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_SegCtl2));
register_name = "SegCtl2";
break;
case CP0_REG05__PWBASE:
check_pw(ctx);
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWBase));
+ tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_PWBase));
register_name = "PWBase";
break;
case CP0_REG05__PWFIELD:
check_pw(ctx);
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWField));
+ tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_PWField));
register_name = "PWField";
break;
case CP0_REG05__PWSIZE:
check_pw(ctx);
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWSize));
+ tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_PWSize));
register_name = "PWSize";
break;
default:
case CP0_REGISTER_08:
switch (sel) {
case CP0_REG08__BADVADDR:
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr));
+ tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_BadVAddr));
register_name = "BadVAddr";
break;
case CP0_REG08__BADINSTR:
case CP0_REG09__COUNT:
/* Mark as an IO operation because we read the time. */
translator_io_start(&ctx->base);
- gen_helper_mfc0_count(arg, cpu_env);
+ gen_helper_mfc0_count(arg, tcg_env);
/*
* Break the TB to be able to take timer interrupts immediately
* after reading count. DISAS_STOP isn't sufficient, we need to
break;
case CP0_REG09__SAAR:
CP0_CHECK(ctx->saar);
- gen_helper_dmfc0_saar(arg, cpu_env);
+ gen_helper_dmfc0_saar(arg, tcg_env);
register_name = "SAAR";
break;
default:
case CP0_REGISTER_10:
switch (sel) {
case CP0_REG10__ENTRYHI:
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryHi));
+ tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_EntryHi));
register_name = "EntryHi";
break;
default:
case CP0_REGISTER_14:
switch (sel) {
case CP0_REG14__EPC:
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
+ tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_EPC));
register_name = "EPC";
break;
default:
break;
case CP0_REG15__EBASE:
check_insn(ctx, ISA_MIPS_R2);
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase));
+ tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_EBase));
register_name = "EBase";
break;
case CP0_REG15__CMGCRBASE:
check_insn(ctx, ISA_MIPS_R2);
CP0_CHECK(ctx->cmgcr);
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase));
+ tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_CMGCRBase));
register_name = "CMGCRBase";
break;
default:
case CP0_REGISTER_17:
switch (sel) {
case CP0_REG17__LLADDR:
- gen_helper_dmfc0_lladdr(arg, cpu_env);
+ gen_helper_dmfc0_lladdr(arg, tcg_env);
register_name = "LLAddr";
break;
case CP0_REG17__MAAR:
CP0_CHECK(ctx->mrp);
- gen_helper_dmfc0_maar(arg, cpu_env);
+ gen_helper_dmfc0_maar(arg, tcg_env);
register_name = "MAAR";
break;
case CP0_REG17__MAARI:
switch (sel) {
case CP0_REG20__XCONTEXT:
check_insn(ctx, ISA_MIPS3);
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_XContext));
+ tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_XContext));
register_name = "XContext";
break;
default:
case CP0_REGISTER_23:
switch (sel) {
case CP0_REG23__DEBUG:
- gen_helper_mfc0_debug(arg, cpu_env); /* EJTAG support */
+ gen_helper_mfc0_debug(arg, tcg_env); /* EJTAG support */
register_name = "Debug";
break;
case CP0_REG23__TRACECONTROL:
/* PDtrace support */
- /* gen_helper_dmfc0_tracecontrol(arg, cpu_env); */
+ /* gen_helper_dmfc0_tracecontrol(arg, tcg_env); */
register_name = "TraceControl";
goto cp0_unimplemented;
case CP0_REG23__TRACECONTROL2:
/* PDtrace support */
- /* gen_helper_dmfc0_tracecontrol2(arg, cpu_env); */
+ /* gen_helper_dmfc0_tracecontrol2(arg, tcg_env); */
register_name = "TraceControl2";
goto cp0_unimplemented;
case CP0_REG23__USERTRACEDATA1:
/* PDtrace support */
- /* gen_helper_dmfc0_usertracedata1(arg, cpu_env);*/
+ /* gen_helper_dmfc0_usertracedata1(arg, tcg_env);*/
register_name = "UserTraceData1";
goto cp0_unimplemented;
case CP0_REG23__TRACEIBPC:
/* PDtrace support */
- /* gen_helper_dmfc0_traceibpc(arg, cpu_env); */
+ /* gen_helper_dmfc0_traceibpc(arg, tcg_env); */
register_name = "TraceIBPC";
goto cp0_unimplemented;
case CP0_REG23__TRACEDBPC:
/* PDtrace support */
- /* gen_helper_dmfc0_tracedbpc(arg, cpu_env); */
+ /* gen_helper_dmfc0_tracedbpc(arg, tcg_env); */
register_name = "TraceDBPC";
goto cp0_unimplemented;
default:
switch (sel) {
case CP0_REG24__DEPC:
/* EJTAG support */
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
+ tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_DEPC));
register_name = "DEPC";
break;
default:
case CP0_REGISTER_30:
switch (sel) {
case CP0_REG30__ERROREPC:
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
+ tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
register_name = "ErrorEPC";
break;
default:
case CP0_REG31__KSCRATCH5:
case CP0_REG31__KSCRATCH6:
CP0_CHECK(ctx->kscrexist & (1 << sel));
- tcg_gen_ld_tl(arg, cpu_env,
+ tcg_gen_ld_tl(arg, tcg_env,
offsetof(CPUMIPSState, CP0_KScratch[sel - 2]));
register_name = "KScratch";
break;
case CP0_REGISTER_00:
switch (sel) {
case CP0_REG00__INDEX:
- gen_helper_mtc0_index(cpu_env, arg);
+ gen_helper_mtc0_index(tcg_env, arg);
register_name = "Index";
break;
case CP0_REG00__MVPCONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mtc0_mvpcontrol(cpu_env, arg);
+ gen_helper_mtc0_mvpcontrol(tcg_env, arg);
register_name = "MVPControl";
break;
case CP0_REG00__MVPCONF0:
break;
case CP0_REG01__VPECONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mtc0_vpecontrol(cpu_env, arg);
+ gen_helper_mtc0_vpecontrol(tcg_env, arg);
register_name = "VPEControl";
break;
case CP0_REG01__VPECONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mtc0_vpeconf0(cpu_env, arg);
+ gen_helper_mtc0_vpeconf0(tcg_env, arg);
register_name = "VPEConf0";
break;
case CP0_REG01__VPECONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mtc0_vpeconf1(cpu_env, arg);
+ gen_helper_mtc0_vpeconf1(tcg_env, arg);
register_name = "VPEConf1";
break;
case CP0_REG01__YQMASK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mtc0_yqmask(cpu_env, arg);
+ gen_helper_mtc0_yqmask(tcg_env, arg);
register_name = "YQMask";
break;
case CP0_REG01__VPESCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- tcg_gen_st_tl(arg, cpu_env,
+ tcg_gen_st_tl(arg, tcg_env,
offsetof(CPUMIPSState, CP0_VPESchedule));
register_name = "VPESchedule";
break;
case CP0_REG01__VPESCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- tcg_gen_st_tl(arg, cpu_env,
+ tcg_gen_st_tl(arg, tcg_env,
offsetof(CPUMIPSState, CP0_VPEScheFBack));
register_name = "VPEScheFBack";
break;
case CP0_REG01__VPEOPT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mtc0_vpeopt(cpu_env, arg);
+ gen_helper_mtc0_vpeopt(tcg_env, arg);
register_name = "VPEOpt";
break;
default:
case CP0_REGISTER_02:
switch (sel) {
case CP0_REG02__ENTRYLO0:
- gen_helper_dmtc0_entrylo0(cpu_env, arg);
+ gen_helper_dmtc0_entrylo0(tcg_env, arg);
register_name = "EntryLo0";
break;
case CP0_REG02__TCSTATUS:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mtc0_tcstatus(cpu_env, arg);
+ gen_helper_mtc0_tcstatus(tcg_env, arg);
register_name = "TCStatus";
break;
case CP0_REG02__TCBIND:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mtc0_tcbind(cpu_env, arg);
+ gen_helper_mtc0_tcbind(tcg_env, arg);
register_name = "TCBind";
break;
case CP0_REG02__TCRESTART:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mtc0_tcrestart(cpu_env, arg);
+ gen_helper_mtc0_tcrestart(tcg_env, arg);
register_name = "TCRestart";
break;
case CP0_REG02__TCHALT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mtc0_tchalt(cpu_env, arg);
+ gen_helper_mtc0_tchalt(tcg_env, arg);
register_name = "TCHalt";
break;
case CP0_REG02__TCCONTEXT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mtc0_tccontext(cpu_env, arg);
+ gen_helper_mtc0_tccontext(tcg_env, arg);
register_name = "TCContext";
break;
case CP0_REG02__TCSCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mtc0_tcschedule(cpu_env, arg);
+ gen_helper_mtc0_tcschedule(tcg_env, arg);
register_name = "TCSchedule";
break;
case CP0_REG02__TCSCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mtc0_tcschefback(cpu_env, arg);
+ gen_helper_mtc0_tcschefback(tcg_env, arg);
register_name = "TCScheFBack";
break;
default:
case CP0_REGISTER_03:
switch (sel) {
case CP0_REG03__ENTRYLO1:
- gen_helper_dmtc0_entrylo1(cpu_env, arg);
+ gen_helper_dmtc0_entrylo1(tcg_env, arg);
register_name = "EntryLo1";
break;
case CP0_REG03__GLOBALNUM:
case CP0_REGISTER_04:
switch (sel) {
case CP0_REG04__CONTEXT:
- gen_helper_mtc0_context(cpu_env, arg);
+ gen_helper_mtc0_context(tcg_env, arg);
register_name = "Context";
break;
case CP0_REG04__CONTEXTCONFIG:
goto cp0_unimplemented;
case CP0_REG04__USERLOCAL:
CP0_CHECK(ctx->ulri);
- tcg_gen_st_tl(arg, cpu_env,
+ tcg_gen_st_tl(arg, tcg_env,
offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
register_name = "UserLocal";
break;
case CP0_REGISTER_05:
switch (sel) {
case CP0_REG05__PAGEMASK:
- gen_helper_mtc0_pagemask(cpu_env, arg);
+ gen_helper_mtc0_pagemask(tcg_env, arg);
register_name = "PageMask";
break;
case CP0_REG05__PAGEGRAIN:
check_insn(ctx, ISA_MIPS_R2);
- gen_helper_mtc0_pagegrain(cpu_env, arg);
+ gen_helper_mtc0_pagegrain(tcg_env, arg);
register_name = "PageGrain";
break;
case CP0_REG05__SEGCTL0:
CP0_CHECK(ctx->sc);
- gen_helper_mtc0_segctl0(cpu_env, arg);
+ gen_helper_mtc0_segctl0(tcg_env, arg);
register_name = "SegCtl0";
break;
case CP0_REG05__SEGCTL1:
CP0_CHECK(ctx->sc);
- gen_helper_mtc0_segctl1(cpu_env, arg);
+ gen_helper_mtc0_segctl1(tcg_env, arg);
register_name = "SegCtl1";
break;
case CP0_REG05__SEGCTL2:
CP0_CHECK(ctx->sc);
- gen_helper_mtc0_segctl2(cpu_env, arg);
+ gen_helper_mtc0_segctl2(tcg_env, arg);
register_name = "SegCtl2";
break;
case CP0_REG05__PWBASE:
check_pw(ctx);
- tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWBase));
+ tcg_gen_st_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_PWBase));
register_name = "PWBase";
break;
case CP0_REG05__PWFIELD:
check_pw(ctx);
- gen_helper_mtc0_pwfield(cpu_env, arg);
+ gen_helper_mtc0_pwfield(tcg_env, arg);
register_name = "PWField";
break;
case CP0_REG05__PWSIZE:
check_pw(ctx);
- gen_helper_mtc0_pwsize(cpu_env, arg);
+ gen_helper_mtc0_pwsize(tcg_env, arg);
register_name = "PWSize";
break;
default:
case CP0_REGISTER_06:
switch (sel) {
case CP0_REG06__WIRED:
- gen_helper_mtc0_wired(cpu_env, arg);
+ gen_helper_mtc0_wired(tcg_env, arg);
register_name = "Wired";
break;
case CP0_REG06__SRSCONF0:
check_insn(ctx, ISA_MIPS_R2);
- gen_helper_mtc0_srsconf0(cpu_env, arg);
+ gen_helper_mtc0_srsconf0(tcg_env, arg);
register_name = "SRSConf0";
break;
case CP0_REG06__SRSCONF1:
check_insn(ctx, ISA_MIPS_R2);
- gen_helper_mtc0_srsconf1(cpu_env, arg);
+ gen_helper_mtc0_srsconf1(tcg_env, arg);
register_name = "SRSConf1";
break;
case CP0_REG06__SRSCONF2:
check_insn(ctx, ISA_MIPS_R2);
- gen_helper_mtc0_srsconf2(cpu_env, arg);
+ gen_helper_mtc0_srsconf2(tcg_env, arg);
register_name = "SRSConf2";
break;
case CP0_REG06__SRSCONF3:
check_insn(ctx, ISA_MIPS_R2);
- gen_helper_mtc0_srsconf3(cpu_env, arg);
+ gen_helper_mtc0_srsconf3(tcg_env, arg);
register_name = "SRSConf3";
break;
case CP0_REG06__SRSCONF4:
check_insn(ctx, ISA_MIPS_R2);
- gen_helper_mtc0_srsconf4(cpu_env, arg);
+ gen_helper_mtc0_srsconf4(tcg_env, arg);
register_name = "SRSConf4";
break;
case CP0_REG06__PWCTL:
check_pw(ctx);
- gen_helper_mtc0_pwctl(cpu_env, arg);
+ gen_helper_mtc0_pwctl(tcg_env, arg);
register_name = "PWCtl";
break;
default:
switch (sel) {
case CP0_REG07__HWRENA:
check_insn(ctx, ISA_MIPS_R2);
- gen_helper_mtc0_hwrena(cpu_env, arg);
+ gen_helper_mtc0_hwrena(tcg_env, arg);
ctx->base.is_jmp = DISAS_STOP;
register_name = "HWREna";
break;
case CP0_REGISTER_09:
switch (sel) {
case CP0_REG09__COUNT:
- gen_helper_mtc0_count(cpu_env, arg);
+ gen_helper_mtc0_count(tcg_env, arg);
register_name = "Count";
break;
case CP0_REG09__SAARI:
CP0_CHECK(ctx->saar);
- gen_helper_mtc0_saari(cpu_env, arg);
+ gen_helper_mtc0_saari(tcg_env, arg);
register_name = "SAARI";
break;
case CP0_REG09__SAAR:
CP0_CHECK(ctx->saar);
- gen_helper_mtc0_saar(cpu_env, arg);
+ gen_helper_mtc0_saar(tcg_env, arg);
register_name = "SAAR";
break;
default:
case CP0_REGISTER_10:
switch (sel) {
case CP0_REG10__ENTRYHI:
- gen_helper_mtc0_entryhi(cpu_env, arg);
+ gen_helper_mtc0_entryhi(tcg_env, arg);
register_name = "EntryHi";
break;
default:
case CP0_REGISTER_11:
switch (sel) {
case CP0_REG11__COMPARE:
- gen_helper_mtc0_compare(cpu_env, arg);
+ gen_helper_mtc0_compare(tcg_env, arg);
register_name = "Compare";
break;
/* 6,7 are implementation dependent */
switch (sel) {
case CP0_REG12__STATUS:
save_cpu_state(ctx, 1);
- gen_helper_mtc0_status(cpu_env, arg);
+ gen_helper_mtc0_status(tcg_env, arg);
/* DISAS_STOP isn't good enough here, hflags may have changed. */
gen_save_pc(ctx->base.pc_next + 4);
ctx->base.is_jmp = DISAS_EXIT;
break;
case CP0_REG12__INTCTL:
check_insn(ctx, ISA_MIPS_R2);
- gen_helper_mtc0_intctl(cpu_env, arg);
+ gen_helper_mtc0_intctl(tcg_env, arg);
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "IntCtl";
break;
case CP0_REG12__SRSCTL:
check_insn(ctx, ISA_MIPS_R2);
- gen_helper_mtc0_srsctl(cpu_env, arg);
+ gen_helper_mtc0_srsctl(tcg_env, arg);
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "SRSCtl";
switch (sel) {
case CP0_REG13__CAUSE:
save_cpu_state(ctx, 1);
- gen_helper_mtc0_cause(cpu_env, arg);
+ gen_helper_mtc0_cause(tcg_env, arg);
/*
* Stop translation as we may have triggered an interrupt.
* DISAS_STOP isn't sufficient, we need to ensure we break out of
case CP0_REGISTER_14:
switch (sel) {
case CP0_REG14__EPC:
- tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
+ tcg_gen_st_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_EPC));
register_name = "EPC";
break;
default:
break;
case CP0_REG15__EBASE:
check_insn(ctx, ISA_MIPS_R2);
- gen_helper_mtc0_ebase(cpu_env, arg);
+ gen_helper_mtc0_ebase(tcg_env, arg);
register_name = "EBase";
break;
default:
case CP0_REGISTER_16:
switch (sel) {
case CP0_REG16__CONFIG:
- gen_helper_mtc0_config0(cpu_env, arg);
+ gen_helper_mtc0_config0(tcg_env, arg);
register_name = "Config";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "Config1";
break;
case CP0_REG16__CONFIG2:
- gen_helper_mtc0_config2(cpu_env, arg);
+ gen_helper_mtc0_config2(tcg_env, arg);
register_name = "Config2";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
case CP0_REG16__CONFIG3:
- gen_helper_mtc0_config3(cpu_env, arg);
+ gen_helper_mtc0_config3(tcg_env, arg);
register_name = "Config3";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "Config4";
break;
case CP0_REG16__CONFIG5:
- gen_helper_mtc0_config5(cpu_env, arg);
+ gen_helper_mtc0_config5(tcg_env, arg);
register_name = "Config5";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
case CP0_REGISTER_17:
switch (sel) {
case CP0_REG17__LLADDR:
- gen_helper_mtc0_lladdr(cpu_env, arg);
+ gen_helper_mtc0_lladdr(tcg_env, arg);
register_name = "LLAddr";
break;
case CP0_REG17__MAAR:
CP0_CHECK(ctx->mrp);
- gen_helper_mtc0_maar(cpu_env, arg);
+ gen_helper_mtc0_maar(tcg_env, arg);
register_name = "MAAR";
break;
case CP0_REG17__MAARI:
CP0_CHECK(ctx->mrp);
- gen_helper_mtc0_maari(cpu_env, arg);
+ gen_helper_mtc0_maari(tcg_env, arg);
register_name = "MAARI";
break;
default:
switch (sel) {
case CP0_REG20__XCONTEXT:
check_insn(ctx, ISA_MIPS3);
- gen_helper_mtc0_xcontext(cpu_env, arg);
+ gen_helper_mtc0_xcontext(tcg_env, arg);
register_name = "XContext";
break;
default:
CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6));
switch (sel) {
case 0:
- gen_helper_mtc0_framemask(cpu_env, arg);
+ gen_helper_mtc0_framemask(tcg_env, arg);
register_name = "Framemask";
break;
default:
case CP0_REGISTER_23:
switch (sel) {
case CP0_REG23__DEBUG:
- gen_helper_mtc0_debug(cpu_env, arg); /* EJTAG support */
+ gen_helper_mtc0_debug(tcg_env, arg); /* EJTAG support */
/* DISAS_STOP isn't good enough here, hflags may have changed. */
gen_save_pc(ctx->base.pc_next + 4);
ctx->base.is_jmp = DISAS_EXIT;
break;
case CP0_REG23__TRACECONTROL:
/* PDtrace support */
- /* gen_helper_mtc0_tracecontrol(cpu_env, arg); */
+ /* gen_helper_mtc0_tracecontrol(tcg_env, arg); */
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "TraceControl";
goto cp0_unimplemented;
case CP0_REG23__TRACECONTROL2:
/* PDtrace support */
- /* gen_helper_mtc0_tracecontrol2(cpu_env, arg); */
+ /* gen_helper_mtc0_tracecontrol2(tcg_env, arg); */
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "TraceControl2";
goto cp0_unimplemented;
case CP0_REG23__USERTRACEDATA1:
/* PDtrace support */
- /* gen_helper_mtc0_usertracedata1(cpu_env, arg);*/
+ /* gen_helper_mtc0_usertracedata1(tcg_env, arg);*/
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "UserTraceData1";
goto cp0_unimplemented;
case CP0_REG23__TRACEIBPC:
/* PDtrace support */
- /* gen_helper_mtc0_traceibpc(cpu_env, arg); */
+ /* gen_helper_mtc0_traceibpc(tcg_env, arg); */
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "TraceIBPC";
goto cp0_unimplemented;
case CP0_REG23__TRACEDBPC:
/* PDtrace support */
- /* gen_helper_mtc0_tracedbpc(cpu_env, arg); */
+ /* gen_helper_mtc0_tracedbpc(tcg_env, arg); */
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "TraceDBPC";
switch (sel) {
case CP0_REG24__DEPC:
/* EJTAG support */
- tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
+ tcg_gen_st_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_DEPC));
register_name = "DEPC";
break;
default:
case CP0_REGISTER_25:
switch (sel) {
case CP0_REG25__PERFCTL0:
- gen_helper_mtc0_performance0(cpu_env, arg);
+ gen_helper_mtc0_performance0(tcg_env, arg);
register_name = "Performance0";
break;
case CP0_REG25__PERFCNT0:
- /* gen_helper_mtc0_performance1(cpu_env, arg); */
+ /* gen_helper_mtc0_performance1(tcg_env, arg); */
register_name = "Performance1";
goto cp0_unimplemented;
case CP0_REG25__PERFCTL1:
- /* gen_helper_mtc0_performance2(cpu_env, arg); */
+ /* gen_helper_mtc0_performance2(tcg_env, arg); */
register_name = "Performance2";
goto cp0_unimplemented;
case CP0_REG25__PERFCNT1:
- /* gen_helper_mtc0_performance3(cpu_env, arg); */
+ /* gen_helper_mtc0_performance3(tcg_env, arg); */
register_name = "Performance3";
goto cp0_unimplemented;
case CP0_REG25__PERFCTL2:
- /* gen_helper_mtc0_performance4(cpu_env, arg); */
+ /* gen_helper_mtc0_performance4(tcg_env, arg); */
register_name = "Performance4";
goto cp0_unimplemented;
case CP0_REG25__PERFCNT2:
- /* gen_helper_mtc0_performance5(cpu_env, arg); */
+ /* gen_helper_mtc0_performance5(tcg_env, arg); */
register_name = "Performance5";
goto cp0_unimplemented;
case CP0_REG25__PERFCTL3:
- /* gen_helper_mtc0_performance6(cpu_env, arg); */
+ /* gen_helper_mtc0_performance6(tcg_env, arg); */
register_name = "Performance6";
goto cp0_unimplemented;
case CP0_REG25__PERFCNT3:
- /* gen_helper_mtc0_performance7(cpu_env, arg); */
+ /* gen_helper_mtc0_performance7(tcg_env, arg); */
register_name = "Performance7";
goto cp0_unimplemented;
default:
case CP0_REGISTER_26:
switch (sel) {
case CP0_REG26__ERRCTL:
- gen_helper_mtc0_errctl(cpu_env, arg);
+ gen_helper_mtc0_errctl(tcg_env, arg);
ctx->base.is_jmp = DISAS_STOP;
register_name = "ErrCtl";
break;
case CP0_REG28__TAGLO1:
case CP0_REG28__TAGLO2:
case CP0_REG28__TAGLO3:
- gen_helper_mtc0_taglo(cpu_env, arg);
+ gen_helper_mtc0_taglo(tcg_env, arg);
register_name = "TagLo";
break;
case CP0_REG28__DATALO:
case CP0_REG28__DATALO1:
case CP0_REG28__DATALO2:
case CP0_REG28__DATALO3:
- gen_helper_mtc0_datalo(cpu_env, arg);
+ gen_helper_mtc0_datalo(tcg_env, arg);
register_name = "DataLo";
break;
default:
case CP0_REG29__TAGHI1:
case CP0_REG29__TAGHI2:
case CP0_REG29__TAGHI3:
- gen_helper_mtc0_taghi(cpu_env, arg);
+ gen_helper_mtc0_taghi(tcg_env, arg);
register_name = "TagHi";
break;
case CP0_REG29__DATAHI:
case CP0_REG29__DATAHI1:
case CP0_REG29__DATAHI2:
case CP0_REG29__DATAHI3:
- gen_helper_mtc0_datahi(cpu_env, arg);
+ gen_helper_mtc0_datahi(tcg_env, arg);
register_name = "DataHi";
break;
default:
case CP0_REGISTER_30:
switch (sel) {
case CP0_REG30__ERROREPC:
- tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
+ tcg_gen_st_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
register_name = "ErrorEPC";
break;
default:
case CP0_REG31__KSCRATCH5:
case CP0_REG31__KSCRATCH6:
CP0_CHECK(ctx->kscrexist & (1 << sel));
- tcg_gen_st_tl(arg, cpu_env,
+ tcg_gen_st_tl(arg, tcg_env,
offsetof(CPUMIPSState, CP0_KScratch[sel - 2]));
register_name = "KScratch";
break;
case 1:
switch (sel) {
case 1:
- gen_helper_mftc0_vpecontrol(t0, cpu_env);
+ gen_helper_mftc0_vpecontrol(t0, tcg_env);
break;
case 2:
- gen_helper_mftc0_vpeconf0(t0, cpu_env);
+ gen_helper_mftc0_vpeconf0(t0, tcg_env);
break;
default:
goto die;
case 2:
switch (sel) {
case 1:
- gen_helper_mftc0_tcstatus(t0, cpu_env);
+ gen_helper_mftc0_tcstatus(t0, tcg_env);
break;
case 2:
- gen_helper_mftc0_tcbind(t0, cpu_env);
+ gen_helper_mftc0_tcbind(t0, tcg_env);
break;
case 3:
- gen_helper_mftc0_tcrestart(t0, cpu_env);
+ gen_helper_mftc0_tcrestart(t0, tcg_env);
break;
case 4:
- gen_helper_mftc0_tchalt(t0, cpu_env);
+ gen_helper_mftc0_tchalt(t0, tcg_env);
break;
case 5:
- gen_helper_mftc0_tccontext(t0, cpu_env);
+ gen_helper_mftc0_tccontext(t0, tcg_env);
break;
case 6:
- gen_helper_mftc0_tcschedule(t0, cpu_env);
+ gen_helper_mftc0_tcschedule(t0, tcg_env);
break;
case 7:
- gen_helper_mftc0_tcschefback(t0, cpu_env);
+ gen_helper_mftc0_tcschefback(t0, tcg_env);
break;
default:
gen_mfc0(ctx, t0, rt, sel);
case 10:
switch (sel) {
case 0:
- gen_helper_mftc0_entryhi(t0, cpu_env);
+ gen_helper_mftc0_entryhi(t0, tcg_env);
break;
default:
gen_mfc0(ctx, t0, rt, sel);
case 12:
switch (sel) {
case 0:
- gen_helper_mftc0_status(t0, cpu_env);
+ gen_helper_mftc0_status(t0, tcg_env);
break;
default:
gen_mfc0(ctx, t0, rt, sel);
case 13:
switch (sel) {
case 0:
- gen_helper_mftc0_cause(t0, cpu_env);
+ gen_helper_mftc0_cause(t0, tcg_env);
break;
default:
goto die;
case 14:
switch (sel) {
case 0:
- gen_helper_mftc0_epc(t0, cpu_env);
+ gen_helper_mftc0_epc(t0, tcg_env);
break;
default:
goto die;
case 15:
switch (sel) {
case 1:
- gen_helper_mftc0_ebase(t0, cpu_env);
+ gen_helper_mftc0_ebase(t0, tcg_env);
break;
default:
goto die;
case 5:
case 6:
case 7:
- gen_helper_mftc0_configx(t0, cpu_env, tcg_constant_tl(sel));
+ gen_helper_mftc0_configx(t0, tcg_env, tcg_constant_tl(sel));
break;
default:
goto die;
case 23:
switch (sel) {
case 0:
- gen_helper_mftc0_debug(t0, cpu_env);
+ gen_helper_mftc0_debug(t0, tcg_env);
break;
default:
gen_mfc0(ctx, t0, rt, sel);
gen_helper_1e0i(mftacx, t0, 3);
break;
case 16:
- gen_helper_mftdsp(t0, cpu_env);
+ gen_helper_mftdsp(t0, tcg_env);
break;
default:
goto die;
case 1:
switch (sel) {
case 1:
- gen_helper_mttc0_vpecontrol(cpu_env, t0);
+ gen_helper_mttc0_vpecontrol(tcg_env, t0);
break;
case 2:
- gen_helper_mttc0_vpeconf0(cpu_env, t0);
+ gen_helper_mttc0_vpeconf0(tcg_env, t0);
break;
default:
goto die;
case 2:
switch (sel) {
case 1:
- gen_helper_mttc0_tcstatus(cpu_env, t0);
+ gen_helper_mttc0_tcstatus(tcg_env, t0);
break;
case 2:
- gen_helper_mttc0_tcbind(cpu_env, t0);
+ gen_helper_mttc0_tcbind(tcg_env, t0);
break;
case 3:
- gen_helper_mttc0_tcrestart(cpu_env, t0);
+ gen_helper_mttc0_tcrestart(tcg_env, t0);
break;
case 4:
- gen_helper_mttc0_tchalt(cpu_env, t0);
+ gen_helper_mttc0_tchalt(tcg_env, t0);
break;
case 5:
- gen_helper_mttc0_tccontext(cpu_env, t0);
+ gen_helper_mttc0_tccontext(tcg_env, t0);
break;
case 6:
- gen_helper_mttc0_tcschedule(cpu_env, t0);
+ gen_helper_mttc0_tcschedule(tcg_env, t0);
break;
case 7:
- gen_helper_mttc0_tcschefback(cpu_env, t0);
+ gen_helper_mttc0_tcschefback(tcg_env, t0);
break;
default:
gen_mtc0(ctx, t0, rd, sel);
case 10:
switch (sel) {
case 0:
- gen_helper_mttc0_entryhi(cpu_env, t0);
+ gen_helper_mttc0_entryhi(tcg_env, t0);
break;
default:
gen_mtc0(ctx, t0, rd, sel);
case 12:
switch (sel) {
case 0:
- gen_helper_mttc0_status(cpu_env, t0);
+ gen_helper_mttc0_status(tcg_env, t0);
break;
default:
gen_mtc0(ctx, t0, rd, sel);
case 13:
switch (sel) {
case 0:
- gen_helper_mttc0_cause(cpu_env, t0);
+ gen_helper_mttc0_cause(tcg_env, t0);
break;
default:
goto die;
case 15:
switch (sel) {
case 1:
- gen_helper_mttc0_ebase(cpu_env, t0);
+ gen_helper_mttc0_ebase(tcg_env, t0);
break;
default:
goto die;
case 23:
switch (sel) {
case 0:
- gen_helper_mttc0_debug(cpu_env, t0);
+ gen_helper_mttc0_debug(tcg_env, t0);
break;
default:
gen_mtc0(ctx, t0, rd, sel);
gen_helper_0e1i(mttacx, t0, 3);
break;
case 16:
- gen_helper_mttdsp(cpu_env, t0);
+ gen_helper_mttdsp(tcg_env, t0);
break;
default:
goto die;
if (!env->tlb->helper_tlbwi) {
goto die;
}
- gen_helper_tlbwi(cpu_env);
+ gen_helper_tlbwi(tcg_env);
break;
case OPC_TLBINV:
opn = "tlbinv";
if (!env->tlb->helper_tlbinv) {
goto die;
}
- gen_helper_tlbinv(cpu_env);
+ gen_helper_tlbinv(tcg_env);
} /* treat as nop if TLBINV not supported */
break;
case OPC_TLBINVF:
if (!env->tlb->helper_tlbinvf) {
goto die;
}
- gen_helper_tlbinvf(cpu_env);
+ gen_helper_tlbinvf(tcg_env);
} /* treat as nop if TLBINV not supported */
break;
case OPC_TLBWR:
if (!env->tlb->helper_tlbwr) {
goto die;
}
- gen_helper_tlbwr(cpu_env);
+ gen_helper_tlbwr(tcg_env);
break;
case OPC_TLBP:
opn = "tlbp";
if (!env->tlb->helper_tlbp) {
goto die;
}
- gen_helper_tlbp(cpu_env);
+ gen_helper_tlbp(tcg_env);
break;
case OPC_TLBR:
opn = "tlbr";
if (!env->tlb->helper_tlbr) {
goto die;
}
- gen_helper_tlbr(cpu_env);
+ gen_helper_tlbr(tcg_env);
break;
case OPC_ERET: /* OPC_ERETNC */
if ((ctx->insn_flags & ISA_MIPS_R6) &&
/* OPC_ERETNC */
opn = "eretnc";
check_insn(ctx, ISA_MIPS_R5);
- gen_helper_eretnc(cpu_env);
+ gen_helper_eretnc(tcg_env);
} else {
/* OPC_ERET */
opn = "eret";
check_insn(ctx, ISA_MIPS2);
- gen_helper_eret(cpu_env);
+ gen_helper_eret(tcg_env);
}
ctx->base.is_jmp = DISAS_EXIT;
}
MIPS_INVAL(opn);
gen_reserved_instruction(ctx);
} else {
- gen_helper_deret(cpu_env);
+ gen_helper_deret(tcg_env);
ctx->base.is_jmp = DISAS_EXIT;
}
break;
ctx->base.pc_next += 4;
save_cpu_state(ctx, 1);
ctx->base.pc_next -= 4;
- gen_helper_wait(cpu_env);
+ gen_helper_wait(tcg_env);
ctx->base.is_jmp = DISAS_NORETURN;
break;
default:
gen_load_fpr32(ctx, fp0, fs);
gen_load_fpr32(ctx, fp1, ft);
- gen_helper_float_add_s(fp0, cpu_env, fp0, fp1);
+ gen_helper_float_add_s(fp0, tcg_env, fp0, fp1);
gen_store_fpr32(ctx, fp0, fd);
}
break;
gen_load_fpr32(ctx, fp0, fs);
gen_load_fpr32(ctx, fp1, ft);
- gen_helper_float_sub_s(fp0, cpu_env, fp0, fp1);
+ gen_helper_float_sub_s(fp0, tcg_env, fp0, fp1);
gen_store_fpr32(ctx, fp0, fd);
}
break;
gen_load_fpr32(ctx, fp0, fs);
gen_load_fpr32(ctx, fp1, ft);
- gen_helper_float_mul_s(fp0, cpu_env, fp0, fp1);
+ gen_helper_float_mul_s(fp0, tcg_env, fp0, fp1);
gen_store_fpr32(ctx, fp0, fd);
}
break;
gen_load_fpr32(ctx, fp0, fs);
gen_load_fpr32(ctx, fp1, ft);
- gen_helper_float_div_s(fp0, cpu_env, fp0, fp1);
+ gen_helper_float_div_s(fp0, tcg_env, fp0, fp1);
gen_store_fpr32(ctx, fp0, fd);
}
break;
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, fs);
- gen_helper_float_sqrt_s(fp0, cpu_env, fp0);
+ gen_helper_float_sqrt_s(fp0, tcg_env, fp0);
gen_store_fpr32(ctx, fp0, fd);
}
break;
gen_load_fpr32(ctx, fp32, fs);
if (ctx->nan2008) {
- gen_helper_float_round_2008_l_s(fp64, cpu_env, fp32);
+ gen_helper_float_round_2008_l_s(fp64, tcg_env, fp32);
} else {
- gen_helper_float_round_l_s(fp64, cpu_env, fp32);
+ gen_helper_float_round_l_s(fp64, tcg_env, fp32);
}
gen_store_fpr64(ctx, fp64, fd);
}
gen_load_fpr32(ctx, fp32, fs);
if (ctx->nan2008) {
- gen_helper_float_trunc_2008_l_s(fp64, cpu_env, fp32);
+ gen_helper_float_trunc_2008_l_s(fp64, tcg_env, fp32);
} else {
- gen_helper_float_trunc_l_s(fp64, cpu_env, fp32);
+ gen_helper_float_trunc_l_s(fp64, tcg_env, fp32);
}
gen_store_fpr64(ctx, fp64, fd);
}
gen_load_fpr32(ctx, fp32, fs);
if (ctx->nan2008) {
- gen_helper_float_ceil_2008_l_s(fp64, cpu_env, fp32);
+ gen_helper_float_ceil_2008_l_s(fp64, tcg_env, fp32);
} else {
- gen_helper_float_ceil_l_s(fp64, cpu_env, fp32);
+ gen_helper_float_ceil_l_s(fp64, tcg_env, fp32);
}
gen_store_fpr64(ctx, fp64, fd);
}
gen_load_fpr32(ctx, fp32, fs);
if (ctx->nan2008) {
- gen_helper_float_floor_2008_l_s(fp64, cpu_env, fp32);
+ gen_helper_float_floor_2008_l_s(fp64, tcg_env, fp32);
} else {
- gen_helper_float_floor_l_s(fp64, cpu_env, fp32);
+ gen_helper_float_floor_l_s(fp64, tcg_env, fp32);
}
gen_store_fpr64(ctx, fp64, fd);
}
gen_load_fpr32(ctx, fp0, fs);
if (ctx->nan2008) {
- gen_helper_float_round_2008_w_s(fp0, cpu_env, fp0);
+ gen_helper_float_round_2008_w_s(fp0, tcg_env, fp0);
} else {
- gen_helper_float_round_w_s(fp0, cpu_env, fp0);
+ gen_helper_float_round_w_s(fp0, tcg_env, fp0);
}
gen_store_fpr32(ctx, fp0, fd);
}
gen_load_fpr32(ctx, fp0, fs);
if (ctx->nan2008) {
- gen_helper_float_trunc_2008_w_s(fp0, cpu_env, fp0);
+ gen_helper_float_trunc_2008_w_s(fp0, tcg_env, fp0);
} else {
- gen_helper_float_trunc_w_s(fp0, cpu_env, fp0);
+ gen_helper_float_trunc_w_s(fp0, tcg_env, fp0);
}
gen_store_fpr32(ctx, fp0, fd);
}
gen_load_fpr32(ctx, fp0, fs);
if (ctx->nan2008) {
- gen_helper_float_ceil_2008_w_s(fp0, cpu_env, fp0);
+ gen_helper_float_ceil_2008_w_s(fp0, tcg_env, fp0);
} else {
- gen_helper_float_ceil_w_s(fp0, cpu_env, fp0);
+ gen_helper_float_ceil_w_s(fp0, tcg_env, fp0);
}
gen_store_fpr32(ctx, fp0, fd);
}
gen_load_fpr32(ctx, fp0, fs);
if (ctx->nan2008) {
- gen_helper_float_floor_2008_w_s(fp0, cpu_env, fp0);
+ gen_helper_float_floor_2008_w_s(fp0, tcg_env, fp0);
} else {
- gen_helper_float_floor_w_s(fp0, cpu_env, fp0);
+ gen_helper_float_floor_w_s(fp0, tcg_env, fp0);
}
gen_store_fpr32(ctx, fp0, fd);
}
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, fs);
- gen_helper_float_recip_s(fp0, cpu_env, fp0);
+ gen_helper_float_recip_s(fp0, tcg_env, fp0);
gen_store_fpr32(ctx, fp0, fd);
}
break;
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, fs);
- gen_helper_float_rsqrt_s(fp0, cpu_env, fp0);
+ gen_helper_float_rsqrt_s(fp0, tcg_env, fp0);
gen_store_fpr32(ctx, fp0, fd);
}
break;
gen_load_fpr32(ctx, fp0, fs);
gen_load_fpr32(ctx, fp1, ft);
gen_load_fpr32(ctx, fp2, fd);
- gen_helper_float_maddf_s(fp2, cpu_env, fp0, fp1, fp2);
+ gen_helper_float_maddf_s(fp2, tcg_env, fp0, fp1, fp2);
gen_store_fpr32(ctx, fp2, fd);
}
break;
gen_load_fpr32(ctx, fp0, fs);
gen_load_fpr32(ctx, fp1, ft);
gen_load_fpr32(ctx, fp2, fd);
- gen_helper_float_msubf_s(fp2, cpu_env, fp0, fp1, fp2);
+ gen_helper_float_msubf_s(fp2, tcg_env, fp0, fp1, fp2);
gen_store_fpr32(ctx, fp2, fd);
}
break;
{
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, fs);
- gen_helper_float_rint_s(fp0, cpu_env, fp0);
+ gen_helper_float_rint_s(fp0, tcg_env, fp0);
gen_store_fpr32(ctx, fp0, fd);
}
break;
{
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, fs);
- gen_helper_float_class_s(fp0, cpu_env, fp0);
+ gen_helper_float_class_s(fp0, tcg_env, fp0);
gen_store_fpr32(ctx, fp0, fd);
}
break;
TCGv_i32 fp2 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, fs);
gen_load_fpr32(ctx, fp1, ft);
- gen_helper_float_min_s(fp2, cpu_env, fp0, fp1);
+ gen_helper_float_min_s(fp2, tcg_env, fp0, fp1);
gen_store_fpr32(ctx, fp2, fd);
} else {
/* OPC_RECIP2_S */
gen_load_fpr32(ctx, fp0, fs);
gen_load_fpr32(ctx, fp1, ft);
- gen_helper_float_recip2_s(fp0, cpu_env, fp0, fp1);
+ gen_helper_float_recip2_s(fp0, tcg_env, fp0, fp1);
gen_store_fpr32(ctx, fp0, fd);
}
}
TCGv_i32 fp2 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, fs);
gen_load_fpr32(ctx, fp1, ft);
- gen_helper_float_mina_s(fp2, cpu_env, fp0, fp1);
+ gen_helper_float_mina_s(fp2, tcg_env, fp0, fp1);
gen_store_fpr32(ctx, fp2, fd);
} else {
/* OPC_RECIP1_S */
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, fs);
- gen_helper_float_recip1_s(fp0, cpu_env, fp0);
+ gen_helper_float_recip1_s(fp0, tcg_env, fp0);
gen_store_fpr32(ctx, fp0, fd);
}
}
TCGv_i32 fp1 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, fs);
gen_load_fpr32(ctx, fp1, ft);
- gen_helper_float_max_s(fp1, cpu_env, fp0, fp1);
+ gen_helper_float_max_s(fp1, tcg_env, fp0, fp1);
gen_store_fpr32(ctx, fp1, fd);
} else {
/* OPC_RSQRT1_S */
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, fs);
- gen_helper_float_rsqrt1_s(fp0, cpu_env, fp0);
+ gen_helper_float_rsqrt1_s(fp0, tcg_env, fp0);
gen_store_fpr32(ctx, fp0, fd);
}
}
TCGv_i32 fp1 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, fs);
gen_load_fpr32(ctx, fp1, ft);
- gen_helper_float_maxa_s(fp1, cpu_env, fp0, fp1);
+ gen_helper_float_maxa_s(fp1, tcg_env, fp0, fp1);
gen_store_fpr32(ctx, fp1, fd);
} else {
/* OPC_RSQRT2_S */
gen_load_fpr32(ctx, fp0, fs);
gen_load_fpr32(ctx, fp1, ft);
- gen_helper_float_rsqrt2_s(fp0, cpu_env, fp0, fp1);
+ gen_helper_float_rsqrt2_s(fp0, tcg_env, fp0, fp1);
gen_store_fpr32(ctx, fp0, fd);
}
}
TCGv_i64 fp64 = tcg_temp_new_i64();
gen_load_fpr32(ctx, fp32, fs);
- gen_helper_float_cvtd_s(fp64, cpu_env, fp32);
+ gen_helper_float_cvtd_s(fp64, tcg_env, fp32);
gen_store_fpr64(ctx, fp64, fd);
}
break;
gen_load_fpr32(ctx, fp0, fs);
if (ctx->nan2008) {
- gen_helper_float_cvt_2008_w_s(fp0, cpu_env, fp0);
+ gen_helper_float_cvt_2008_w_s(fp0, tcg_env, fp0);
} else {
- gen_helper_float_cvt_w_s(fp0, cpu_env, fp0);
+ gen_helper_float_cvt_w_s(fp0, tcg_env, fp0);
}
gen_store_fpr32(ctx, fp0, fd);
}
gen_load_fpr32(ctx, fp32, fs);
if (ctx->nan2008) {
- gen_helper_float_cvt_2008_l_s(fp64, cpu_env, fp32);
+ gen_helper_float_cvt_2008_l_s(fp64, tcg_env, fp32);
} else {
- gen_helper_float_cvt_l_s(fp64, cpu_env, fp32);
+ gen_helper_float_cvt_l_s(fp64, tcg_env, fp32);
}
gen_store_fpr64(ctx, fp64, fd);
}
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
- gen_helper_float_add_d(fp0, cpu_env, fp0, fp1);
+ gen_helper_float_add_d(fp0, tcg_env, fp0, fp1);
gen_store_fpr64(ctx, fp0, fd);
}
break;
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
- gen_helper_float_sub_d(fp0, cpu_env, fp0, fp1);
+ gen_helper_float_sub_d(fp0, tcg_env, fp0, fp1);
gen_store_fpr64(ctx, fp0, fd);
}
break;
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
- gen_helper_float_mul_d(fp0, cpu_env, fp0, fp1);
+ gen_helper_float_mul_d(fp0, tcg_env, fp0, fp1);
gen_store_fpr64(ctx, fp0, fd);
}
break;
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
- gen_helper_float_div_d(fp0, cpu_env, fp0, fp1);
+ gen_helper_float_div_d(fp0, tcg_env, fp0, fp1);
gen_store_fpr64(ctx, fp0, fd);
}
break;
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- gen_helper_float_sqrt_d(fp0, cpu_env, fp0);
+ gen_helper_float_sqrt_d(fp0, tcg_env, fp0);
gen_store_fpr64(ctx, fp0, fd);
}
break;
gen_load_fpr64(ctx, fp0, fs);
if (ctx->nan2008) {
- gen_helper_float_round_2008_l_d(fp0, cpu_env, fp0);
+ gen_helper_float_round_2008_l_d(fp0, tcg_env, fp0);
} else {
- gen_helper_float_round_l_d(fp0, cpu_env, fp0);
+ gen_helper_float_round_l_d(fp0, tcg_env, fp0);
}
gen_store_fpr64(ctx, fp0, fd);
}
gen_load_fpr64(ctx, fp0, fs);
if (ctx->nan2008) {
- gen_helper_float_trunc_2008_l_d(fp0, cpu_env, fp0);
+ gen_helper_float_trunc_2008_l_d(fp0, tcg_env, fp0);
} else {
- gen_helper_float_trunc_l_d(fp0, cpu_env, fp0);
+ gen_helper_float_trunc_l_d(fp0, tcg_env, fp0);
}
gen_store_fpr64(ctx, fp0, fd);
}
gen_load_fpr64(ctx, fp0, fs);
if (ctx->nan2008) {
- gen_helper_float_ceil_2008_l_d(fp0, cpu_env, fp0);
+ gen_helper_float_ceil_2008_l_d(fp0, tcg_env, fp0);
} else {
- gen_helper_float_ceil_l_d(fp0, cpu_env, fp0);
+ gen_helper_float_ceil_l_d(fp0, tcg_env, fp0);
}
gen_store_fpr64(ctx, fp0, fd);
}
gen_load_fpr64(ctx, fp0, fs);
if (ctx->nan2008) {
- gen_helper_float_floor_2008_l_d(fp0, cpu_env, fp0);
+ gen_helper_float_floor_2008_l_d(fp0, tcg_env, fp0);
} else {
- gen_helper_float_floor_l_d(fp0, cpu_env, fp0);
+ gen_helper_float_floor_l_d(fp0, tcg_env, fp0);
}
gen_store_fpr64(ctx, fp0, fd);
}
gen_load_fpr64(ctx, fp64, fs);
if (ctx->nan2008) {
- gen_helper_float_round_2008_w_d(fp32, cpu_env, fp64);
+ gen_helper_float_round_2008_w_d(fp32, tcg_env, fp64);
} else {
- gen_helper_float_round_w_d(fp32, cpu_env, fp64);
+ gen_helper_float_round_w_d(fp32, tcg_env, fp64);
}
gen_store_fpr32(ctx, fp32, fd);
}
gen_load_fpr64(ctx, fp64, fs);
if (ctx->nan2008) {
- gen_helper_float_trunc_2008_w_d(fp32, cpu_env, fp64);
+ gen_helper_float_trunc_2008_w_d(fp32, tcg_env, fp64);
} else {
- gen_helper_float_trunc_w_d(fp32, cpu_env, fp64);
+ gen_helper_float_trunc_w_d(fp32, tcg_env, fp64);
}
gen_store_fpr32(ctx, fp32, fd);
}
gen_load_fpr64(ctx, fp64, fs);
if (ctx->nan2008) {
- gen_helper_float_ceil_2008_w_d(fp32, cpu_env, fp64);
+ gen_helper_float_ceil_2008_w_d(fp32, tcg_env, fp64);
} else {
- gen_helper_float_ceil_w_d(fp32, cpu_env, fp64);
+ gen_helper_float_ceil_w_d(fp32, tcg_env, fp64);
}
gen_store_fpr32(ctx, fp32, fd);
}
gen_load_fpr64(ctx, fp64, fs);
if (ctx->nan2008) {
- gen_helper_float_floor_2008_w_d(fp32, cpu_env, fp64);
+ gen_helper_float_floor_2008_w_d(fp32, tcg_env, fp64);
} else {
- gen_helper_float_floor_w_d(fp32, cpu_env, fp64);
+ gen_helper_float_floor_w_d(fp32, tcg_env, fp64);
}
gen_store_fpr32(ctx, fp32, fd);
}
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- gen_helper_float_recip_d(fp0, cpu_env, fp0);
+ gen_helper_float_recip_d(fp0, tcg_env, fp0);
gen_store_fpr64(ctx, fp0, fd);
}
break;
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- gen_helper_float_rsqrt_d(fp0, cpu_env, fp0);
+ gen_helper_float_rsqrt_d(fp0, tcg_env, fp0);
gen_store_fpr64(ctx, fp0, fd);
}
break;
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
gen_load_fpr64(ctx, fp2, fd);
- gen_helper_float_maddf_d(fp2, cpu_env, fp0, fp1, fp2);
+ gen_helper_float_maddf_d(fp2, tcg_env, fp0, fp1, fp2);
gen_store_fpr64(ctx, fp2, fd);
}
break;
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
gen_load_fpr64(ctx, fp2, fd);
- gen_helper_float_msubf_d(fp2, cpu_env, fp0, fp1, fp2);
+ gen_helper_float_msubf_d(fp2, tcg_env, fp0, fp1, fp2);
gen_store_fpr64(ctx, fp2, fd);
}
break;
{
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- gen_helper_float_rint_d(fp0, cpu_env, fp0);
+ gen_helper_float_rint_d(fp0, tcg_env, fp0);
gen_store_fpr64(ctx, fp0, fd);
}
break;
{
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- gen_helper_float_class_d(fp0, cpu_env, fp0);
+ gen_helper_float_class_d(fp0, tcg_env, fp0);
gen_store_fpr64(ctx, fp0, fd);
}
break;
TCGv_i64 fp1 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
- gen_helper_float_min_d(fp1, cpu_env, fp0, fp1);
+ gen_helper_float_min_d(fp1, tcg_env, fp0, fp1);
gen_store_fpr64(ctx, fp1, fd);
} else {
/* OPC_RECIP2_D */
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
- gen_helper_float_recip2_d(fp0, cpu_env, fp0, fp1);
+ gen_helper_float_recip2_d(fp0, tcg_env, fp0, fp1);
gen_store_fpr64(ctx, fp0, fd);
}
}
TCGv_i64 fp1 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
- gen_helper_float_mina_d(fp1, cpu_env, fp0, fp1);
+ gen_helper_float_mina_d(fp1, tcg_env, fp0, fp1);
gen_store_fpr64(ctx, fp1, fd);
} else {
/* OPC_RECIP1_D */
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- gen_helper_float_recip1_d(fp0, cpu_env, fp0);
+ gen_helper_float_recip1_d(fp0, tcg_env, fp0);
gen_store_fpr64(ctx, fp0, fd);
}
}
TCGv_i64 fp1 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
- gen_helper_float_max_d(fp1, cpu_env, fp0, fp1);
+ gen_helper_float_max_d(fp1, tcg_env, fp0, fp1);
gen_store_fpr64(ctx, fp1, fd);
} else {
/* OPC_RSQRT1_D */
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- gen_helper_float_rsqrt1_d(fp0, cpu_env, fp0);
+ gen_helper_float_rsqrt1_d(fp0, tcg_env, fp0);
gen_store_fpr64(ctx, fp0, fd);
}
}
TCGv_i64 fp1 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
- gen_helper_float_maxa_d(fp1, cpu_env, fp0, fp1);
+ gen_helper_float_maxa_d(fp1, tcg_env, fp0, fp1);
gen_store_fpr64(ctx, fp1, fd);
} else {
/* OPC_RSQRT2_D */
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
- gen_helper_float_rsqrt2_d(fp0, cpu_env, fp0, fp1);
+ gen_helper_float_rsqrt2_d(fp0, tcg_env, fp0, fp1);
gen_store_fpr64(ctx, fp0, fd);
}
}
TCGv_i64 fp64 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp64, fs);
- gen_helper_float_cvts_d(fp32, cpu_env, fp64);
+ gen_helper_float_cvts_d(fp32, tcg_env, fp64);
gen_store_fpr32(ctx, fp32, fd);
}
break;
gen_load_fpr64(ctx, fp64, fs);
if (ctx->nan2008) {
- gen_helper_float_cvt_2008_w_d(fp32, cpu_env, fp64);
+ gen_helper_float_cvt_2008_w_d(fp32, tcg_env, fp64);
} else {
- gen_helper_float_cvt_w_d(fp32, cpu_env, fp64);
+ gen_helper_float_cvt_w_d(fp32, tcg_env, fp64);
}
gen_store_fpr32(ctx, fp32, fd);
}
gen_load_fpr64(ctx, fp0, fs);
if (ctx->nan2008) {
- gen_helper_float_cvt_2008_l_d(fp0, cpu_env, fp0);
+ gen_helper_float_cvt_2008_l_d(fp0, tcg_env, fp0);
} else {
- gen_helper_float_cvt_l_d(fp0, cpu_env, fp0);
+ gen_helper_float_cvt_l_d(fp0, tcg_env, fp0);
}
gen_store_fpr64(ctx, fp0, fd);
}
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, fs);
- gen_helper_float_cvts_w(fp0, cpu_env, fp0);
+ gen_helper_float_cvts_w(fp0, tcg_env, fp0);
gen_store_fpr32(ctx, fp0, fd);
}
break;
TCGv_i64 fp64 = tcg_temp_new_i64();
gen_load_fpr32(ctx, fp32, fs);
- gen_helper_float_cvtd_w(fp64, cpu_env, fp32);
+ gen_helper_float_cvtd_w(fp64, tcg_env, fp32);
gen_store_fpr64(ctx, fp64, fd);
}
break;
TCGv_i64 fp64 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp64, fs);
- gen_helper_float_cvts_l(fp32, cpu_env, fp64);
+ gen_helper_float_cvts_l(fp32, tcg_env, fp64);
gen_store_fpr32(ctx, fp32, fd);
}
break;
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- gen_helper_float_cvtd_l(fp0, cpu_env, fp0);
+ gen_helper_float_cvtd_l(fp0, tcg_env, fp0);
gen_store_fpr64(ctx, fp0, fd);
}
break;
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- gen_helper_float_cvtps_pw(fp0, cpu_env, fp0);
+ gen_helper_float_cvtps_pw(fp0, tcg_env, fp0);
gen_store_fpr64(ctx, fp0, fd);
}
break;
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
- gen_helper_float_add_ps(fp0, cpu_env, fp0, fp1);
+ gen_helper_float_add_ps(fp0, tcg_env, fp0, fp1);
gen_store_fpr64(ctx, fp0, fd);
}
break;
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
- gen_helper_float_sub_ps(fp0, cpu_env, fp0, fp1);
+ gen_helper_float_sub_ps(fp0, tcg_env, fp0, fp1);
gen_store_fpr64(ctx, fp0, fd);
}
break;
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
- gen_helper_float_mul_ps(fp0, cpu_env, fp0, fp1);
+ gen_helper_float_mul_ps(fp0, tcg_env, fp0, fp1);
gen_store_fpr64(ctx, fp0, fd);
}
break;
gen_load_fpr64(ctx, fp0, ft);
gen_load_fpr64(ctx, fp1, fs);
- gen_helper_float_addr_ps(fp0, cpu_env, fp0, fp1);
+ gen_helper_float_addr_ps(fp0, tcg_env, fp0, fp1);
gen_store_fpr64(ctx, fp0, fd);
}
break;
gen_load_fpr64(ctx, fp0, ft);
gen_load_fpr64(ctx, fp1, fs);
- gen_helper_float_mulr_ps(fp0, cpu_env, fp0, fp1);
+ gen_helper_float_mulr_ps(fp0, tcg_env, fp0, fp1);
gen_store_fpr64(ctx, fp0, fd);
}
break;
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
- gen_helper_float_recip2_ps(fp0, cpu_env, fp0, fp1);
+ gen_helper_float_recip2_ps(fp0, tcg_env, fp0, fp1);
gen_store_fpr64(ctx, fp0, fd);
}
break;
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- gen_helper_float_recip1_ps(fp0, cpu_env, fp0);
+ gen_helper_float_recip1_ps(fp0, tcg_env, fp0);
gen_store_fpr64(ctx, fp0, fd);
}
break;
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- gen_helper_float_rsqrt1_ps(fp0, cpu_env, fp0);
+ gen_helper_float_rsqrt1_ps(fp0, tcg_env, fp0);
gen_store_fpr64(ctx, fp0, fd);
}
break;
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
- gen_helper_float_rsqrt2_ps(fp0, cpu_env, fp0, fp1);
+ gen_helper_float_rsqrt2_ps(fp0, tcg_env, fp0, fp1);
gen_store_fpr64(ctx, fp0, fd);
}
break;
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32h(ctx, fp0, fs);
- gen_helper_float_cvts_pu(fp0, cpu_env, fp0);
+ gen_helper_float_cvts_pu(fp0, tcg_env, fp0);
gen_store_fpr32(ctx, fp0, fd);
}
break;
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- gen_helper_float_cvtpw_ps(fp0, cpu_env, fp0);
+ gen_helper_float_cvtpw_ps(fp0, tcg_env, fp0);
gen_store_fpr64(ctx, fp0, fd);
}
break;
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, fs);
- gen_helper_float_cvts_pl(fp0, cpu_env, fp0);
+ gen_helper_float_cvts_pl(fp0, tcg_env, fp0);
gen_store_fpr32(ctx, fp0, fd);
}
break;
gen_load_fpr32(ctx, fp0, fs);
gen_load_fpr32(ctx, fp1, ft);
gen_load_fpr32(ctx, fp2, fr);
- gen_helper_float_madd_s(fp2, cpu_env, fp0, fp1, fp2);
+ gen_helper_float_madd_s(fp2, tcg_env, fp0, fp1, fp2);
gen_store_fpr32(ctx, fp2, fd);
}
break;
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
gen_load_fpr64(ctx, fp2, fr);
- gen_helper_float_madd_d(fp2, cpu_env, fp0, fp1, fp2);
+ gen_helper_float_madd_d(fp2, tcg_env, fp0, fp1, fp2);
gen_store_fpr64(ctx, fp2, fd);
}
break;
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
gen_load_fpr64(ctx, fp2, fr);
- gen_helper_float_madd_ps(fp2, cpu_env, fp0, fp1, fp2);
+ gen_helper_float_madd_ps(fp2, tcg_env, fp0, fp1, fp2);
gen_store_fpr64(ctx, fp2, fd);
}
break;
gen_load_fpr32(ctx, fp0, fs);
gen_load_fpr32(ctx, fp1, ft);
gen_load_fpr32(ctx, fp2, fr);
- gen_helper_float_msub_s(fp2, cpu_env, fp0, fp1, fp2);
+ gen_helper_float_msub_s(fp2, tcg_env, fp0, fp1, fp2);
gen_store_fpr32(ctx, fp2, fd);
}
break;
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
gen_load_fpr64(ctx, fp2, fr);
- gen_helper_float_msub_d(fp2, cpu_env, fp0, fp1, fp2);
+ gen_helper_float_msub_d(fp2, tcg_env, fp0, fp1, fp2);
gen_store_fpr64(ctx, fp2, fd);
}
break;
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
gen_load_fpr64(ctx, fp2, fr);
- gen_helper_float_msub_ps(fp2, cpu_env, fp0, fp1, fp2);
+ gen_helper_float_msub_ps(fp2, tcg_env, fp0, fp1, fp2);
gen_store_fpr64(ctx, fp2, fd);
}
break;
gen_load_fpr32(ctx, fp0, fs);
gen_load_fpr32(ctx, fp1, ft);
gen_load_fpr32(ctx, fp2, fr);
- gen_helper_float_nmadd_s(fp2, cpu_env, fp0, fp1, fp2);
+ gen_helper_float_nmadd_s(fp2, tcg_env, fp0, fp1, fp2);
gen_store_fpr32(ctx, fp2, fd);
}
break;
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
gen_load_fpr64(ctx, fp2, fr);
- gen_helper_float_nmadd_d(fp2, cpu_env, fp0, fp1, fp2);
+ gen_helper_float_nmadd_d(fp2, tcg_env, fp0, fp1, fp2);
gen_store_fpr64(ctx, fp2, fd);
}
break;
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
gen_load_fpr64(ctx, fp2, fr);
- gen_helper_float_nmadd_ps(fp2, cpu_env, fp0, fp1, fp2);
+ gen_helper_float_nmadd_ps(fp2, tcg_env, fp0, fp1, fp2);
gen_store_fpr64(ctx, fp2, fd);
}
break;
gen_load_fpr32(ctx, fp0, fs);
gen_load_fpr32(ctx, fp1, ft);
gen_load_fpr32(ctx, fp2, fr);
- gen_helper_float_nmsub_s(fp2, cpu_env, fp0, fp1, fp2);
+ gen_helper_float_nmsub_s(fp2, tcg_env, fp0, fp1, fp2);
gen_store_fpr32(ctx, fp2, fd);
}
break;
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
gen_load_fpr64(ctx, fp2, fr);
- gen_helper_float_nmsub_d(fp2, cpu_env, fp0, fp1, fp2);
+ gen_helper_float_nmsub_d(fp2, tcg_env, fp0, fp1, fp2);
gen_store_fpr64(ctx, fp2, fd);
}
break;
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
gen_load_fpr64(ctx, fp2, fr);
- gen_helper_float_nmsub_ps(fp2, cpu_env, fp0, fp1, fp2);
+ gen_helper_float_nmsub_ps(fp2, tcg_env, fp0, fp1, fp2);
gen_store_fpr64(ctx, fp2, fd);
}
break;
switch (rd) {
case 0:
- gen_helper_rdhwr_cpunum(t0, cpu_env);
+ gen_helper_rdhwr_cpunum(t0, tcg_env);
gen_store_gpr(t0, rt);
break;
case 1:
- gen_helper_rdhwr_synci_step(t0, cpu_env);
+ gen_helper_rdhwr_synci_step(t0, tcg_env);
gen_store_gpr(t0, rt);
break;
case 2:
translator_io_start(&ctx->base);
- gen_helper_rdhwr_cc(t0, cpu_env);
+ gen_helper_rdhwr_cc(t0, tcg_env);
gen_store_gpr(t0, rt);
/*
* Break the TB to be able to take timer interrupts immediately
ctx->base.is_jmp = DISAS_EXIT;
break;
case 3:
- gen_helper_rdhwr_ccres(t0, cpu_env);
+ gen_helper_rdhwr_ccres(t0, tcg_env);
gen_store_gpr(t0, rt);
break;
case 4:
*/
generate_exception(ctx, EXCP_RI);
}
- gen_helper_rdhwr_performance(t0, cpu_env);
+ gen_helper_rdhwr_performance(t0, tcg_env);
gen_store_gpr(t0, rt);
break;
case 5:
check_insn(ctx, ISA_MIPS_R6);
- gen_helper_rdhwr_xnp(t0, cpu_env);
+ gen_helper_rdhwr_xnp(t0, tcg_env);
gen_store_gpr(t0, rt);
break;
case 29:
#if defined(CONFIG_USER_ONLY)
- tcg_gen_ld_tl(t0, cpu_env,
+ tcg_gen_ld_tl(t0, tcg_env,
offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
gen_store_gpr(t0, rt);
break;
#else
if ((ctx->hflags & MIPS_HFLAG_CP0) ||
(ctx->hflags & MIPS_HFLAG_HWRENA_ULR)) {
- tcg_gen_ld_tl(t0, cpu_env,
+ tcg_gen_ld_tl(t0, tcg_env,
offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
gen_store_gpr(t0, rt);
} else {
TCGv_i32 t0 = tcg_constant_i32(op);
TCGv t1 = tcg_temp_new();
gen_base_offset_addr(ctx, t1, base, offset);
- gen_helper_cache(cpu_env, t1, t0);
+ gen_helper_cache(tcg_env, t1, t0);
}
static inline bool is_uhi(DisasContext *ctx, int sdbbp_code)
switch (op2) {
case OPC_ABSQ_S_QB:
check_dsp_r2(ctx);
- gen_helper_absq_s_qb(cpu_gpr[ret], v2_t, cpu_env);
+ gen_helper_absq_s_qb(cpu_gpr[ret], v2_t, tcg_env);
break;
case OPC_ABSQ_S_PH:
check_dsp(ctx);
- gen_helper_absq_s_ph(cpu_gpr[ret], v2_t, cpu_env);
+ gen_helper_absq_s_ph(cpu_gpr[ret], v2_t, tcg_env);
break;
case OPC_ABSQ_S_W:
check_dsp(ctx);
- gen_helper_absq_s_w(cpu_gpr[ret], v2_t, cpu_env);
+ gen_helper_absq_s_w(cpu_gpr[ret], v2_t, tcg_env);
break;
case OPC_PRECEQ_W_PHL:
check_dsp(ctx);
switch (op2) {
case OPC_ADDQ_PH:
check_dsp(ctx);
- gen_helper_addq_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_addq_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_ADDQ_S_PH:
check_dsp(ctx);
- gen_helper_addq_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_addq_s_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_ADDQ_S_W:
check_dsp(ctx);
- gen_helper_addq_s_w(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_addq_s_w(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_ADDU_QB:
check_dsp(ctx);
- gen_helper_addu_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_addu_qb(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_ADDU_S_QB:
check_dsp(ctx);
- gen_helper_addu_s_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_addu_s_qb(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_ADDU_PH:
check_dsp_r2(ctx);
- gen_helper_addu_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_addu_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_ADDU_S_PH:
check_dsp_r2(ctx);
- gen_helper_addu_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_addu_s_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_SUBQ_PH:
check_dsp(ctx);
- gen_helper_subq_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_subq_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_SUBQ_S_PH:
check_dsp(ctx);
- gen_helper_subq_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_subq_s_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_SUBQ_S_W:
check_dsp(ctx);
- gen_helper_subq_s_w(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_subq_s_w(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_SUBU_QB:
check_dsp(ctx);
- gen_helper_subu_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_subu_qb(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_SUBU_S_QB:
check_dsp(ctx);
- gen_helper_subu_s_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_subu_s_qb(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_SUBU_PH:
check_dsp_r2(ctx);
- gen_helper_subu_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_subu_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_SUBU_S_PH:
check_dsp_r2(ctx);
- gen_helper_subu_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_subu_s_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_ADDSC:
check_dsp(ctx);
- gen_helper_addsc(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_addsc(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_ADDWC:
check_dsp(ctx);
- gen_helper_addwc(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_addwc(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_MODSUB:
check_dsp(ctx);
break;
case OPC_PRECRQ_RS_PH_W:
check_dsp(ctx);
- gen_helper_precrq_rs_ph_w(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_precrq_rs_ph_w(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_PRECRQU_S_QB_PH:
check_dsp(ctx);
- gen_helper_precrqu_s_qb_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_precrqu_s_qb_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
}
break;
break;
case OPC_ABSQ_S_OB:
check_dsp_r2(ctx);
- gen_helper_absq_s_ob(cpu_gpr[ret], v2_t, cpu_env);
+ gen_helper_absq_s_ob(cpu_gpr[ret], v2_t, tcg_env);
break;
case OPC_ABSQ_S_PW:
check_dsp(ctx);
- gen_helper_absq_s_pw(cpu_gpr[ret], v2_t, cpu_env);
+ gen_helper_absq_s_pw(cpu_gpr[ret], v2_t, tcg_env);
break;
case OPC_ABSQ_S_QH:
check_dsp(ctx);
- gen_helper_absq_s_qh(cpu_gpr[ret], v2_t, cpu_env);
+ gen_helper_absq_s_qh(cpu_gpr[ret], v2_t, tcg_env);
break;
}
break;
break;
case OPC_SUBQ_PW:
check_dsp(ctx);
- gen_helper_subq_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_subq_pw(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_SUBQ_S_PW:
check_dsp(ctx);
- gen_helper_subq_s_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_subq_s_pw(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_SUBQ_QH:
check_dsp(ctx);
- gen_helper_subq_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_subq_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_SUBQ_S_QH:
check_dsp(ctx);
- gen_helper_subq_s_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_subq_s_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_SUBU_OB:
check_dsp(ctx);
- gen_helper_subu_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_subu_ob(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_SUBU_S_OB:
check_dsp(ctx);
- gen_helper_subu_s_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_subu_s_ob(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_SUBU_QH:
check_dsp_r2(ctx);
- gen_helper_subu_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_subu_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_SUBU_S_QH:
check_dsp_r2(ctx);
- gen_helper_subu_s_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_subu_s_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_SUBUH_OB:
check_dsp_r2(ctx);
break;
case OPC_ADDQ_PW:
check_dsp(ctx);
- gen_helper_addq_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_addq_pw(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_ADDQ_S_PW:
check_dsp(ctx);
- gen_helper_addq_s_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_addq_s_pw(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_ADDQ_QH:
check_dsp(ctx);
- gen_helper_addq_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_addq_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_ADDQ_S_QH:
check_dsp(ctx);
- gen_helper_addq_s_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_addq_s_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_ADDU_OB:
check_dsp(ctx);
- gen_helper_addu_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_addu_ob(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_ADDU_S_OB:
check_dsp(ctx);
- gen_helper_addu_s_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_addu_s_ob(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_ADDU_QH:
check_dsp_r2(ctx);
- gen_helper_addu_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_addu_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_ADDU_S_QH:
check_dsp_r2(ctx);
- gen_helper_addu_s_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_addu_s_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_ADDUH_OB:
check_dsp_r2(ctx);
break;
case OPC_PRECRQ_RS_QH_PW:
check_dsp(ctx);
- gen_helper_precrq_rs_qh_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_precrq_rs_qh_pw(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_PRECRQU_S_OB_QH:
check_dsp(ctx);
- gen_helper_precrqu_s_ob_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_precrqu_s_ob_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
}
break;
switch (op2) {
case OPC_SHLL_QB:
check_dsp(ctx);
- gen_helper_shll_qb(cpu_gpr[ret], t0, v2_t, cpu_env);
+ gen_helper_shll_qb(cpu_gpr[ret], t0, v2_t, tcg_env);
break;
case OPC_SHLLV_QB:
check_dsp(ctx);
- gen_helper_shll_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_shll_qb(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_SHLL_PH:
check_dsp(ctx);
- gen_helper_shll_ph(cpu_gpr[ret], t0, v2_t, cpu_env);
+ gen_helper_shll_ph(cpu_gpr[ret], t0, v2_t, tcg_env);
break;
case OPC_SHLLV_PH:
check_dsp(ctx);
- gen_helper_shll_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_shll_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_SHLL_S_PH:
check_dsp(ctx);
- gen_helper_shll_s_ph(cpu_gpr[ret], t0, v2_t, cpu_env);
+ gen_helper_shll_s_ph(cpu_gpr[ret], t0, v2_t, tcg_env);
break;
case OPC_SHLLV_S_PH:
check_dsp(ctx);
- gen_helper_shll_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_shll_s_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_SHLL_S_W:
check_dsp(ctx);
- gen_helper_shll_s_w(cpu_gpr[ret], t0, v2_t, cpu_env);
+ gen_helper_shll_s_w(cpu_gpr[ret], t0, v2_t, tcg_env);
break;
case OPC_SHLLV_S_W:
check_dsp(ctx);
- gen_helper_shll_s_w(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_shll_s_w(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_SHRL_QB:
check_dsp(ctx);
switch (op2) {
case OPC_SHLL_PW:
check_dsp(ctx);
- gen_helper_shll_pw(cpu_gpr[ret], v2_t, t0, cpu_env);
+ gen_helper_shll_pw(cpu_gpr[ret], v2_t, t0, tcg_env);
break;
case OPC_SHLLV_PW:
check_dsp(ctx);
- gen_helper_shll_pw(cpu_gpr[ret], v2_t, v1_t, cpu_env);
+ gen_helper_shll_pw(cpu_gpr[ret], v2_t, v1_t, tcg_env);
break;
case OPC_SHLL_S_PW:
check_dsp(ctx);
- gen_helper_shll_s_pw(cpu_gpr[ret], v2_t, t0, cpu_env);
+ gen_helper_shll_s_pw(cpu_gpr[ret], v2_t, t0, tcg_env);
break;
case OPC_SHLLV_S_PW:
check_dsp(ctx);
- gen_helper_shll_s_pw(cpu_gpr[ret], v2_t, v1_t, cpu_env);
+ gen_helper_shll_s_pw(cpu_gpr[ret], v2_t, v1_t, tcg_env);
break;
case OPC_SHLL_OB:
check_dsp(ctx);
- gen_helper_shll_ob(cpu_gpr[ret], v2_t, t0, cpu_env);
+ gen_helper_shll_ob(cpu_gpr[ret], v2_t, t0, tcg_env);
break;
case OPC_SHLLV_OB:
check_dsp(ctx);
- gen_helper_shll_ob(cpu_gpr[ret], v2_t, v1_t, cpu_env);
+ gen_helper_shll_ob(cpu_gpr[ret], v2_t, v1_t, tcg_env);
break;
case OPC_SHLL_QH:
check_dsp(ctx);
- gen_helper_shll_qh(cpu_gpr[ret], v2_t, t0, cpu_env);
+ gen_helper_shll_qh(cpu_gpr[ret], v2_t, t0, tcg_env);
break;
case OPC_SHLLV_QH:
check_dsp(ctx);
- gen_helper_shll_qh(cpu_gpr[ret], v2_t, v1_t, cpu_env);
+ gen_helper_shll_qh(cpu_gpr[ret], v2_t, v1_t, tcg_env);
break;
case OPC_SHLL_S_QH:
check_dsp(ctx);
- gen_helper_shll_s_qh(cpu_gpr[ret], v2_t, t0, cpu_env);
+ gen_helper_shll_s_qh(cpu_gpr[ret], v2_t, t0, tcg_env);
break;
case OPC_SHLLV_S_QH:
check_dsp(ctx);
- gen_helper_shll_s_qh(cpu_gpr[ret], v2_t, v1_t, cpu_env);
+ gen_helper_shll_s_qh(cpu_gpr[ret], v2_t, v1_t, tcg_env);
break;
case OPC_SHRA_OB:
check_dsp_r2(ctx);
check_dsp_r2(ctx);
switch (op2) {
case OPC_MUL_PH:
- gen_helper_mul_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_mul_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_MUL_S_PH:
- gen_helper_mul_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_mul_s_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_MULQ_S_W:
- gen_helper_mulq_s_w(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_mulq_s_w(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_MULQ_RS_W:
- gen_helper_mulq_rs_w(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_mulq_rs_w(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
}
break;
switch (op2) {
case OPC_DPAU_H_QBL:
check_dsp(ctx);
- gen_helper_dpau_h_qbl(t0, v1_t, v2_t, cpu_env);
+ gen_helper_dpau_h_qbl(t0, v1_t, v2_t, tcg_env);
break;
case OPC_DPAU_H_QBR:
check_dsp(ctx);
- gen_helper_dpau_h_qbr(t0, v1_t, v2_t, cpu_env);
+ gen_helper_dpau_h_qbr(t0, v1_t, v2_t, tcg_env);
break;
case OPC_DPSU_H_QBL:
check_dsp(ctx);
- gen_helper_dpsu_h_qbl(t0, v1_t, v2_t, cpu_env);
+ gen_helper_dpsu_h_qbl(t0, v1_t, v2_t, tcg_env);
break;
case OPC_DPSU_H_QBR:
check_dsp(ctx);
- gen_helper_dpsu_h_qbr(t0, v1_t, v2_t, cpu_env);
+ gen_helper_dpsu_h_qbr(t0, v1_t, v2_t, tcg_env);
break;
case OPC_DPA_W_PH:
check_dsp_r2(ctx);
- gen_helper_dpa_w_ph(t0, v1_t, v2_t, cpu_env);
+ gen_helper_dpa_w_ph(t0, v1_t, v2_t, tcg_env);
break;
case OPC_DPAX_W_PH:
check_dsp_r2(ctx);
- gen_helper_dpax_w_ph(t0, v1_t, v2_t, cpu_env);
+ gen_helper_dpax_w_ph(t0, v1_t, v2_t, tcg_env);
break;
case OPC_DPAQ_S_W_PH:
check_dsp(ctx);
- gen_helper_dpaq_s_w_ph(t0, v1_t, v2_t, cpu_env);
+ gen_helper_dpaq_s_w_ph(t0, v1_t, v2_t, tcg_env);
break;
case OPC_DPAQX_S_W_PH:
check_dsp_r2(ctx);
- gen_helper_dpaqx_s_w_ph(t0, v1_t, v2_t, cpu_env);
+ gen_helper_dpaqx_s_w_ph(t0, v1_t, v2_t, tcg_env);
break;
case OPC_DPAQX_SA_W_PH:
check_dsp_r2(ctx);
- gen_helper_dpaqx_sa_w_ph(t0, v1_t, v2_t, cpu_env);
+ gen_helper_dpaqx_sa_w_ph(t0, v1_t, v2_t, tcg_env);
break;
case OPC_DPS_W_PH:
check_dsp_r2(ctx);
- gen_helper_dps_w_ph(t0, v1_t, v2_t, cpu_env);
+ gen_helper_dps_w_ph(t0, v1_t, v2_t, tcg_env);
break;
case OPC_DPSX_W_PH:
check_dsp_r2(ctx);
- gen_helper_dpsx_w_ph(t0, v1_t, v2_t, cpu_env);
+ gen_helper_dpsx_w_ph(t0, v1_t, v2_t, tcg_env);
break;
case OPC_DPSQ_S_W_PH:
check_dsp(ctx);
- gen_helper_dpsq_s_w_ph(t0, v1_t, v2_t, cpu_env);
+ gen_helper_dpsq_s_w_ph(t0, v1_t, v2_t, tcg_env);
break;
case OPC_DPSQX_S_W_PH:
check_dsp_r2(ctx);
- gen_helper_dpsqx_s_w_ph(t0, v1_t, v2_t, cpu_env);
+ gen_helper_dpsqx_s_w_ph(t0, v1_t, v2_t, tcg_env);
break;
case OPC_DPSQX_SA_W_PH:
check_dsp_r2(ctx);
- gen_helper_dpsqx_sa_w_ph(t0, v1_t, v2_t, cpu_env);
+ gen_helper_dpsqx_sa_w_ph(t0, v1_t, v2_t, tcg_env);
break;
case OPC_MULSAQ_S_W_PH:
check_dsp(ctx);
- gen_helper_mulsaq_s_w_ph(t0, v1_t, v2_t, cpu_env);
+ gen_helper_mulsaq_s_w_ph(t0, v1_t, v2_t, tcg_env);
break;
case OPC_DPAQ_SA_L_W:
check_dsp(ctx);
- gen_helper_dpaq_sa_l_w(t0, v1_t, v2_t, cpu_env);
+ gen_helper_dpaq_sa_l_w(t0, v1_t, v2_t, tcg_env);
break;
case OPC_DPSQ_SA_L_W:
check_dsp(ctx);
- gen_helper_dpsq_sa_l_w(t0, v1_t, v2_t, cpu_env);
+ gen_helper_dpsq_sa_l_w(t0, v1_t, v2_t, tcg_env);
break;
case OPC_MAQ_S_W_PHL:
check_dsp(ctx);
- gen_helper_maq_s_w_phl(t0, v1_t, v2_t, cpu_env);
+ gen_helper_maq_s_w_phl(t0, v1_t, v2_t, tcg_env);
break;
case OPC_MAQ_S_W_PHR:
check_dsp(ctx);
- gen_helper_maq_s_w_phr(t0, v1_t, v2_t, cpu_env);
+ gen_helper_maq_s_w_phr(t0, v1_t, v2_t, tcg_env);
break;
case OPC_MAQ_SA_W_PHL:
check_dsp(ctx);
- gen_helper_maq_sa_w_phl(t0, v1_t, v2_t, cpu_env);
+ gen_helper_maq_sa_w_phl(t0, v1_t, v2_t, tcg_env);
break;
case OPC_MAQ_SA_W_PHR:
check_dsp(ctx);
- gen_helper_maq_sa_w_phr(t0, v1_t, v2_t, cpu_env);
+ gen_helper_maq_sa_w_phr(t0, v1_t, v2_t, tcg_env);
break;
case OPC_MULSA_W_PH:
check_dsp_r2(ctx);
- gen_helper_mulsa_w_ph(t0, v1_t, v2_t, cpu_env);
+ gen_helper_mulsa_w_ph(t0, v1_t, v2_t, tcg_env);
break;
}
break;
switch (op2) {
case OPC_DMADD:
check_dsp(ctx);
- gen_helper_dmadd(v1_t, v2_t, t0, cpu_env);
+ gen_helper_dmadd(v1_t, v2_t, t0, tcg_env);
break;
case OPC_DMADDU:
check_dsp(ctx);
- gen_helper_dmaddu(v1_t, v2_t, t0, cpu_env);
+ gen_helper_dmaddu(v1_t, v2_t, t0, tcg_env);
break;
case OPC_DMSUB:
check_dsp(ctx);
- gen_helper_dmsub(v1_t, v2_t, t0, cpu_env);
+ gen_helper_dmsub(v1_t, v2_t, t0, tcg_env);
break;
case OPC_DMSUBU:
check_dsp(ctx);
- gen_helper_dmsubu(v1_t, v2_t, t0, cpu_env);
+ gen_helper_dmsubu(v1_t, v2_t, t0, tcg_env);
break;
case OPC_DPA_W_QH:
check_dsp_r2(ctx);
- gen_helper_dpa_w_qh(v1_t, v2_t, t0, cpu_env);
+ gen_helper_dpa_w_qh(v1_t, v2_t, t0, tcg_env);
break;
case OPC_DPAQ_S_W_QH:
check_dsp(ctx);
- gen_helper_dpaq_s_w_qh(v1_t, v2_t, t0, cpu_env);
+ gen_helper_dpaq_s_w_qh(v1_t, v2_t, t0, tcg_env);
break;
case OPC_DPAQ_SA_L_PW:
check_dsp(ctx);
- gen_helper_dpaq_sa_l_pw(v1_t, v2_t, t0, cpu_env);
+ gen_helper_dpaq_sa_l_pw(v1_t, v2_t, t0, tcg_env);
break;
case OPC_DPAU_H_OBL:
check_dsp(ctx);
- gen_helper_dpau_h_obl(v1_t, v2_t, t0, cpu_env);
+ gen_helper_dpau_h_obl(v1_t, v2_t, t0, tcg_env);
break;
case OPC_DPAU_H_OBR:
check_dsp(ctx);
- gen_helper_dpau_h_obr(v1_t, v2_t, t0, cpu_env);
+ gen_helper_dpau_h_obr(v1_t, v2_t, t0, tcg_env);
break;
case OPC_DPS_W_QH:
check_dsp_r2(ctx);
- gen_helper_dps_w_qh(v1_t, v2_t, t0, cpu_env);
+ gen_helper_dps_w_qh(v1_t, v2_t, t0, tcg_env);
break;
case OPC_DPSQ_S_W_QH:
check_dsp(ctx);
- gen_helper_dpsq_s_w_qh(v1_t, v2_t, t0, cpu_env);
+ gen_helper_dpsq_s_w_qh(v1_t, v2_t, t0, tcg_env);
break;
case OPC_DPSQ_SA_L_PW:
check_dsp(ctx);
- gen_helper_dpsq_sa_l_pw(v1_t, v2_t, t0, cpu_env);
+ gen_helper_dpsq_sa_l_pw(v1_t, v2_t, t0, tcg_env);
break;
case OPC_DPSU_H_OBL:
check_dsp(ctx);
- gen_helper_dpsu_h_obl(v1_t, v2_t, t0, cpu_env);
+ gen_helper_dpsu_h_obl(v1_t, v2_t, t0, tcg_env);
break;
case OPC_DPSU_H_OBR:
check_dsp(ctx);
- gen_helper_dpsu_h_obr(v1_t, v2_t, t0, cpu_env);
+ gen_helper_dpsu_h_obr(v1_t, v2_t, t0, tcg_env);
break;
case OPC_MAQ_S_L_PWL:
check_dsp(ctx);
- gen_helper_maq_s_l_pwl(v1_t, v2_t, t0, cpu_env);
+ gen_helper_maq_s_l_pwl(v1_t, v2_t, t0, tcg_env);
break;
case OPC_MAQ_S_L_PWR:
check_dsp(ctx);
- gen_helper_maq_s_l_pwr(v1_t, v2_t, t0, cpu_env);
+ gen_helper_maq_s_l_pwr(v1_t, v2_t, t0, tcg_env);
break;
case OPC_MAQ_S_W_QHLL:
check_dsp(ctx);
- gen_helper_maq_s_w_qhll(v1_t, v2_t, t0, cpu_env);
+ gen_helper_maq_s_w_qhll(v1_t, v2_t, t0, tcg_env);
break;
case OPC_MAQ_SA_W_QHLL:
check_dsp(ctx);
- gen_helper_maq_sa_w_qhll(v1_t, v2_t, t0, cpu_env);
+ gen_helper_maq_sa_w_qhll(v1_t, v2_t, t0, tcg_env);
break;
case OPC_MAQ_S_W_QHLR:
check_dsp(ctx);
- gen_helper_maq_s_w_qhlr(v1_t, v2_t, t0, cpu_env);
+ gen_helper_maq_s_w_qhlr(v1_t, v2_t, t0, tcg_env);
break;
case OPC_MAQ_SA_W_QHLR:
check_dsp(ctx);
- gen_helper_maq_sa_w_qhlr(v1_t, v2_t, t0, cpu_env);
+ gen_helper_maq_sa_w_qhlr(v1_t, v2_t, t0, tcg_env);
break;
case OPC_MAQ_S_W_QHRL:
check_dsp(ctx);
- gen_helper_maq_s_w_qhrl(v1_t, v2_t, t0, cpu_env);
+ gen_helper_maq_s_w_qhrl(v1_t, v2_t, t0, tcg_env);
break;
case OPC_MAQ_SA_W_QHRL:
check_dsp(ctx);
- gen_helper_maq_sa_w_qhrl(v1_t, v2_t, t0, cpu_env);
+ gen_helper_maq_sa_w_qhrl(v1_t, v2_t, t0, tcg_env);
break;
case OPC_MAQ_S_W_QHRR:
check_dsp(ctx);
- gen_helper_maq_s_w_qhrr(v1_t, v2_t, t0, cpu_env);
+ gen_helper_maq_s_w_qhrr(v1_t, v2_t, t0, tcg_env);
break;
case OPC_MAQ_SA_W_QHRR:
check_dsp(ctx);
- gen_helper_maq_sa_w_qhrr(v1_t, v2_t, t0, cpu_env);
+ gen_helper_maq_sa_w_qhrr(v1_t, v2_t, t0, tcg_env);
break;
case OPC_MULSAQ_S_L_PW:
check_dsp(ctx);
- gen_helper_mulsaq_s_l_pw(v1_t, v2_t, t0, cpu_env);
+ gen_helper_mulsaq_s_l_pw(v1_t, v2_t, t0, tcg_env);
break;
case OPC_MULSAQ_S_W_QH:
check_dsp(ctx);
- gen_helper_mulsaq_s_w_qh(v1_t, v2_t, t0, cpu_env);
+ gen_helper_mulsaq_s_w_qh(v1_t, v2_t, t0, tcg_env);
break;
}
}
switch (op2) {
case OPC_MULEU_S_PH_QBL:
check_dsp(ctx);
- gen_helper_muleu_s_ph_qbl(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_muleu_s_ph_qbl(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_MULEU_S_PH_QBR:
check_dsp(ctx);
- gen_helper_muleu_s_ph_qbr(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_muleu_s_ph_qbr(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_MULQ_RS_PH:
check_dsp(ctx);
- gen_helper_mulq_rs_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_mulq_rs_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_MULEQ_S_W_PHL:
check_dsp(ctx);
- gen_helper_muleq_s_w_phl(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_muleq_s_w_phl(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_MULEQ_S_W_PHR:
check_dsp(ctx);
- gen_helper_muleq_s_w_phr(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_muleq_s_w_phr(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_MULQ_S_PH:
check_dsp_r2(ctx);
- gen_helper_mulq_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_mulq_s_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
}
break;
switch (op2) {
case OPC_MULEQ_S_PW_QHL:
check_dsp(ctx);
- gen_helper_muleq_s_pw_qhl(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_muleq_s_pw_qhl(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_MULEQ_S_PW_QHR:
check_dsp(ctx);
- gen_helper_muleq_s_pw_qhr(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_muleq_s_pw_qhr(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_MULEU_S_QH_OBL:
check_dsp(ctx);
- gen_helper_muleu_s_qh_obl(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_muleu_s_qh_obl(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_MULEU_S_QH_OBR:
check_dsp(ctx);
- gen_helper_muleu_s_qh_obr(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_muleu_s_qh_obr(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_MULQ_RS_QH:
check_dsp(ctx);
- gen_helper_mulq_rs_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_mulq_rs_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
}
break;
switch (op2) {
case OPC_CMPU_EQ_QB:
check_dsp(ctx);
- gen_helper_cmpu_eq_qb(v1_t, v2_t, cpu_env);
+ gen_helper_cmpu_eq_qb(v1_t, v2_t, tcg_env);
break;
case OPC_CMPU_LT_QB:
check_dsp(ctx);
- gen_helper_cmpu_lt_qb(v1_t, v2_t, cpu_env);
+ gen_helper_cmpu_lt_qb(v1_t, v2_t, tcg_env);
break;
case OPC_CMPU_LE_QB:
check_dsp(ctx);
- gen_helper_cmpu_le_qb(v1_t, v2_t, cpu_env);
+ gen_helper_cmpu_le_qb(v1_t, v2_t, tcg_env);
break;
case OPC_CMPGU_EQ_QB:
check_dsp(ctx);
break;
case OPC_CMP_EQ_PH:
check_dsp(ctx);
- gen_helper_cmp_eq_ph(v1_t, v2_t, cpu_env);
+ gen_helper_cmp_eq_ph(v1_t, v2_t, tcg_env);
break;
case OPC_CMP_LT_PH:
check_dsp(ctx);
- gen_helper_cmp_lt_ph(v1_t, v2_t, cpu_env);
+ gen_helper_cmp_lt_ph(v1_t, v2_t, tcg_env);
break;
case OPC_CMP_LE_PH:
check_dsp(ctx);
- gen_helper_cmp_le_ph(v1_t, v2_t, cpu_env);
+ gen_helper_cmp_le_ph(v1_t, v2_t, tcg_env);
break;
case OPC_PICK_QB:
check_dsp(ctx);
- gen_helper_pick_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_pick_qb(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_PICK_PH:
check_dsp(ctx);
- gen_helper_pick_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_pick_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_PACKRL_PH:
check_dsp(ctx);
switch (op2) {
case OPC_CMP_EQ_PW:
check_dsp(ctx);
- gen_helper_cmp_eq_pw(v1_t, v2_t, cpu_env);
+ gen_helper_cmp_eq_pw(v1_t, v2_t, tcg_env);
break;
case OPC_CMP_LT_PW:
check_dsp(ctx);
- gen_helper_cmp_lt_pw(v1_t, v2_t, cpu_env);
+ gen_helper_cmp_lt_pw(v1_t, v2_t, tcg_env);
break;
case OPC_CMP_LE_PW:
check_dsp(ctx);
- gen_helper_cmp_le_pw(v1_t, v2_t, cpu_env);
+ gen_helper_cmp_le_pw(v1_t, v2_t, tcg_env);
break;
case OPC_CMP_EQ_QH:
check_dsp(ctx);
- gen_helper_cmp_eq_qh(v1_t, v2_t, cpu_env);
+ gen_helper_cmp_eq_qh(v1_t, v2_t, tcg_env);
break;
case OPC_CMP_LT_QH:
check_dsp(ctx);
- gen_helper_cmp_lt_qh(v1_t, v2_t, cpu_env);
+ gen_helper_cmp_lt_qh(v1_t, v2_t, tcg_env);
break;
case OPC_CMP_LE_QH:
check_dsp(ctx);
- gen_helper_cmp_le_qh(v1_t, v2_t, cpu_env);
+ gen_helper_cmp_le_qh(v1_t, v2_t, tcg_env);
break;
case OPC_CMPGDU_EQ_OB:
check_dsp_r2(ctx);
- gen_helper_cmpgdu_eq_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_cmpgdu_eq_ob(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_CMPGDU_LT_OB:
check_dsp_r2(ctx);
- gen_helper_cmpgdu_lt_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_cmpgdu_lt_ob(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_CMPGDU_LE_OB:
check_dsp_r2(ctx);
- gen_helper_cmpgdu_le_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_cmpgdu_le_ob(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_CMPGU_EQ_OB:
check_dsp(ctx);
break;
case OPC_CMPU_EQ_OB:
check_dsp(ctx);
- gen_helper_cmpu_eq_ob(v1_t, v2_t, cpu_env);
+ gen_helper_cmpu_eq_ob(v1_t, v2_t, tcg_env);
break;
case OPC_CMPU_LT_OB:
check_dsp(ctx);
- gen_helper_cmpu_lt_ob(v1_t, v2_t, cpu_env);
+ gen_helper_cmpu_lt_ob(v1_t, v2_t, tcg_env);
break;
case OPC_CMPU_LE_OB:
check_dsp(ctx);
- gen_helper_cmpu_le_ob(v1_t, v2_t, cpu_env);
+ gen_helper_cmpu_le_ob(v1_t, v2_t, tcg_env);
break;
case OPC_PACKRL_PW:
check_dsp(ctx);
break;
case OPC_PICK_OB:
check_dsp(ctx);
- gen_helper_pick_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_pick_ob(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_PICK_PW:
check_dsp(ctx);
- gen_helper_pick_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_pick_pw(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_PICK_QH:
check_dsp(ctx);
- gen_helper_pick_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_pick_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
}
break;
case OPC_EXTR_W:
tcg_gen_movi_tl(t0, v2);
tcg_gen_movi_tl(t1, v1);
- gen_helper_extr_w(cpu_gpr[ret], t0, t1, cpu_env);
+ gen_helper_extr_w(cpu_gpr[ret], t0, t1, tcg_env);
break;
case OPC_EXTR_R_W:
tcg_gen_movi_tl(t0, v2);
tcg_gen_movi_tl(t1, v1);
- gen_helper_extr_r_w(cpu_gpr[ret], t0, t1, cpu_env);
+ gen_helper_extr_r_w(cpu_gpr[ret], t0, t1, tcg_env);
break;
case OPC_EXTR_RS_W:
tcg_gen_movi_tl(t0, v2);
tcg_gen_movi_tl(t1, v1);
- gen_helper_extr_rs_w(cpu_gpr[ret], t0, t1, cpu_env);
+ gen_helper_extr_rs_w(cpu_gpr[ret], t0, t1, tcg_env);
break;
case OPC_EXTR_S_H:
tcg_gen_movi_tl(t0, v2);
tcg_gen_movi_tl(t1, v1);
- gen_helper_extr_s_h(cpu_gpr[ret], t0, t1, cpu_env);
+ gen_helper_extr_s_h(cpu_gpr[ret], t0, t1, tcg_env);
break;
case OPC_EXTRV_S_H:
tcg_gen_movi_tl(t0, v2);
- gen_helper_extr_s_h(cpu_gpr[ret], t0, v1_t, cpu_env);
+ gen_helper_extr_s_h(cpu_gpr[ret], t0, v1_t, tcg_env);
break;
case OPC_EXTRV_W:
tcg_gen_movi_tl(t0, v2);
- gen_helper_extr_w(cpu_gpr[ret], t0, v1_t, cpu_env);
+ gen_helper_extr_w(cpu_gpr[ret], t0, v1_t, tcg_env);
break;
case OPC_EXTRV_R_W:
tcg_gen_movi_tl(t0, v2);
- gen_helper_extr_r_w(cpu_gpr[ret], t0, v1_t, cpu_env);
+ gen_helper_extr_r_w(cpu_gpr[ret], t0, v1_t, tcg_env);
break;
case OPC_EXTRV_RS_W:
tcg_gen_movi_tl(t0, v2);
- gen_helper_extr_rs_w(cpu_gpr[ret], t0, v1_t, cpu_env);
+ gen_helper_extr_rs_w(cpu_gpr[ret], t0, v1_t, tcg_env);
break;
case OPC_EXTP:
tcg_gen_movi_tl(t0, v2);
tcg_gen_movi_tl(t1, v1);
- gen_helper_extp(cpu_gpr[ret], t0, t1, cpu_env);
+ gen_helper_extp(cpu_gpr[ret], t0, t1, tcg_env);
break;
case OPC_EXTPV:
tcg_gen_movi_tl(t0, v2);
- gen_helper_extp(cpu_gpr[ret], t0, v1_t, cpu_env);
+ gen_helper_extp(cpu_gpr[ret], t0, v1_t, tcg_env);
break;
case OPC_EXTPDP:
tcg_gen_movi_tl(t0, v2);
tcg_gen_movi_tl(t1, v1);
- gen_helper_extpdp(cpu_gpr[ret], t0, t1, cpu_env);
+ gen_helper_extpdp(cpu_gpr[ret], t0, t1, tcg_env);
break;
case OPC_EXTPDPV:
tcg_gen_movi_tl(t0, v2);
- gen_helper_extpdp(cpu_gpr[ret], t0, v1_t, cpu_env);
+ gen_helper_extpdp(cpu_gpr[ret], t0, v1_t, tcg_env);
break;
case OPC_SHILO:
imm = (ctx->opcode >> 20) & 0x3F;
tcg_gen_movi_tl(t0, ret);
tcg_gen_movi_tl(t1, imm);
- gen_helper_shilo(t0, t1, cpu_env);
+ gen_helper_shilo(t0, t1, tcg_env);
break;
case OPC_SHILOV:
tcg_gen_movi_tl(t0, ret);
- gen_helper_shilo(t0, v1_t, cpu_env);
+ gen_helper_shilo(t0, v1_t, tcg_env);
break;
case OPC_MTHLIP:
tcg_gen_movi_tl(t0, ret);
- gen_helper_mthlip(t0, v1_t, cpu_env);
+ gen_helper_mthlip(t0, v1_t, tcg_env);
break;
case OPC_WRDSP:
imm = (ctx->opcode >> 11) & 0x3FF;
tcg_gen_movi_tl(t0, imm);
- gen_helper_wrdsp(v1_t, t0, cpu_env);
+ gen_helper_wrdsp(v1_t, t0, tcg_env);
break;
case OPC_RDDSP:
imm = (ctx->opcode >> 16) & 0x03FF;
tcg_gen_movi_tl(t0, imm);
- gen_helper_rddsp(cpu_gpr[ret], t0, cpu_env);
+ gen_helper_rddsp(cpu_gpr[ret], t0, tcg_env);
break;
}
break;
switch (op2) {
case OPC_DMTHLIP:
tcg_gen_movi_tl(t0, ret);
- gen_helper_dmthlip(v1_t, t0, cpu_env);
+ gen_helper_dmthlip(v1_t, t0, tcg_env);
break;
case OPC_DSHILO:
{
int ac = (ctx->opcode >> 11) & 0x03;
tcg_gen_movi_tl(t0, shift);
tcg_gen_movi_tl(t1, ac);
- gen_helper_dshilo(t0, t1, cpu_env);
+ gen_helper_dshilo(t0, t1, tcg_env);
break;
}
case OPC_DSHILOV:
{
int ac = (ctx->opcode >> 11) & 0x03;
tcg_gen_movi_tl(t0, ac);
- gen_helper_dshilo(v1_t, t0, cpu_env);
+ gen_helper_dshilo(v1_t, t0, tcg_env);
break;
}
case OPC_DEXTP:
tcg_gen_movi_tl(t0, v2);
tcg_gen_movi_tl(t1, v1);
- gen_helper_dextp(cpu_gpr[ret], t0, t1, cpu_env);
+ gen_helper_dextp(cpu_gpr[ret], t0, t1, tcg_env);
break;
case OPC_DEXTPV:
tcg_gen_movi_tl(t0, v2);
- gen_helper_dextp(cpu_gpr[ret], t0, v1_t, cpu_env);
+ gen_helper_dextp(cpu_gpr[ret], t0, v1_t, tcg_env);
break;
case OPC_DEXTPDP:
tcg_gen_movi_tl(t0, v2);
tcg_gen_movi_tl(t1, v1);
- gen_helper_dextpdp(cpu_gpr[ret], t0, t1, cpu_env);
+ gen_helper_dextpdp(cpu_gpr[ret], t0, t1, tcg_env);
break;
case OPC_DEXTPDPV:
tcg_gen_movi_tl(t0, v2);
- gen_helper_dextpdp(cpu_gpr[ret], t0, v1_t, cpu_env);
+ gen_helper_dextpdp(cpu_gpr[ret], t0, v1_t, tcg_env);
break;
case OPC_DEXTR_L:
tcg_gen_movi_tl(t0, v2);
tcg_gen_movi_tl(t1, v1);
- gen_helper_dextr_l(cpu_gpr[ret], t0, t1, cpu_env);
+ gen_helper_dextr_l(cpu_gpr[ret], t0, t1, tcg_env);
break;
case OPC_DEXTR_R_L:
tcg_gen_movi_tl(t0, v2);
tcg_gen_movi_tl(t1, v1);
- gen_helper_dextr_r_l(cpu_gpr[ret], t0, t1, cpu_env);
+ gen_helper_dextr_r_l(cpu_gpr[ret], t0, t1, tcg_env);
break;
case OPC_DEXTR_RS_L:
tcg_gen_movi_tl(t0, v2);
tcg_gen_movi_tl(t1, v1);
- gen_helper_dextr_rs_l(cpu_gpr[ret], t0, t1, cpu_env);
+ gen_helper_dextr_rs_l(cpu_gpr[ret], t0, t1, tcg_env);
break;
case OPC_DEXTR_W:
tcg_gen_movi_tl(t0, v2);
tcg_gen_movi_tl(t1, v1);
- gen_helper_dextr_w(cpu_gpr[ret], t0, t1, cpu_env);
+ gen_helper_dextr_w(cpu_gpr[ret], t0, t1, tcg_env);
break;
case OPC_DEXTR_R_W:
tcg_gen_movi_tl(t0, v2);
tcg_gen_movi_tl(t1, v1);
- gen_helper_dextr_r_w(cpu_gpr[ret], t0, t1, cpu_env);
+ gen_helper_dextr_r_w(cpu_gpr[ret], t0, t1, tcg_env);
break;
case OPC_DEXTR_RS_W:
tcg_gen_movi_tl(t0, v2);
tcg_gen_movi_tl(t1, v1);
- gen_helper_dextr_rs_w(cpu_gpr[ret], t0, t1, cpu_env);
+ gen_helper_dextr_rs_w(cpu_gpr[ret], t0, t1, tcg_env);
break;
case OPC_DEXTR_S_H:
tcg_gen_movi_tl(t0, v2);
tcg_gen_movi_tl(t1, v1);
- gen_helper_dextr_s_h(cpu_gpr[ret], t0, t1, cpu_env);
+ gen_helper_dextr_s_h(cpu_gpr[ret], t0, t1, tcg_env);
break;
case OPC_DEXTRV_S_H:
tcg_gen_movi_tl(t0, v2);
- gen_helper_dextr_s_h(cpu_gpr[ret], t0, v1_t, cpu_env);
+ gen_helper_dextr_s_h(cpu_gpr[ret], t0, v1_t, tcg_env);
break;
case OPC_DEXTRV_L:
tcg_gen_movi_tl(t0, v2);
- gen_helper_dextr_l(cpu_gpr[ret], t0, v1_t, cpu_env);
+ gen_helper_dextr_l(cpu_gpr[ret], t0, v1_t, tcg_env);
break;
case OPC_DEXTRV_R_L:
tcg_gen_movi_tl(t0, v2);
- gen_helper_dextr_r_l(cpu_gpr[ret], t0, v1_t, cpu_env);
+ gen_helper_dextr_r_l(cpu_gpr[ret], t0, v1_t, tcg_env);
break;
case OPC_DEXTRV_RS_L:
tcg_gen_movi_tl(t0, v2);
- gen_helper_dextr_rs_l(cpu_gpr[ret], t0, v1_t, cpu_env);
+ gen_helper_dextr_rs_l(cpu_gpr[ret], t0, v1_t, tcg_env);
break;
case OPC_DEXTRV_W:
tcg_gen_movi_tl(t0, v2);
- gen_helper_dextr_w(cpu_gpr[ret], t0, v1_t, cpu_env);
+ gen_helper_dextr_w(cpu_gpr[ret], t0, v1_t, tcg_env);
break;
case OPC_DEXTRV_R_W:
tcg_gen_movi_tl(t0, v2);
- gen_helper_dextr_r_w(cpu_gpr[ret], t0, v1_t, cpu_env);
+ gen_helper_dextr_r_w(cpu_gpr[ret], t0, v1_t, tcg_env);
break;
case OPC_DEXTRV_RS_W:
tcg_gen_movi_tl(t0, v2);
- gen_helper_dextr_rs_w(cpu_gpr[ret], t0, v1_t, cpu_env);
+ gen_helper_dextr_rs_w(cpu_gpr[ret], t0, v1_t, tcg_env);
break;
}
break;
MIPS_INVAL("PMON / selsl");
gen_reserved_instruction(ctx);
#else
- gen_helper_pmon(cpu_env, tcg_constant_i32(sa));
+ gen_helper_pmon(tcg_env, tcg_constant_i32(sa));
#endif
break;
case OPC_SYSCALL:
gen_load_gpr(t0, rt);
gen_load_gpr(t1, rs);
- gen_helper_insv(cpu_gpr[rt], cpu_env, t1, t0);
+ gen_helper_insv(cpu_gpr[rt], tcg_env, t1, t0);
break;
}
default: /* Invalid */
gen_load_gpr(t0, rt);
gen_load_gpr(t1, rs);
- gen_helper_dinsv(cpu_gpr[rt], cpu_env, t1, t0);
+ gen_helper_dinsv(cpu_gpr[rt], tcg_env, t1, t0);
break;
}
default: /* Invalid */
TCGv t0 = tcg_temp_new();
gen_load_gpr(t0, rs);
- gen_helper_yield(t0, cpu_env, t0);
+ gen_helper_yield(t0, tcg_env, t0);
gen_store_gpr(t0, rd);
}
break;
break;
case OPC_DVPE:
check_cp0_mt(ctx);
- gen_helper_dvpe(t0, cpu_env);
+ gen_helper_dvpe(t0, tcg_env);
gen_store_gpr(t0, rt);
break;
case OPC_EVPE:
check_cp0_mt(ctx);
- gen_helper_evpe(t0, cpu_env);
+ gen_helper_evpe(t0, tcg_env);
gen_store_gpr(t0, rt);
break;
case OPC_DVP:
check_insn(ctx, ISA_MIPS_R6);
if (ctx->vp) {
- gen_helper_dvp(t0, cpu_env);
+ gen_helper_dvp(t0, tcg_env);
gen_store_gpr(t0, rt);
}
break;
case OPC_EVP:
check_insn(ctx, ISA_MIPS_R6);
if (ctx->vp) {
- gen_helper_evp(t0, cpu_env);
+ gen_helper_evp(t0, tcg_env);
gen_store_gpr(t0, rt);
}
break;
case OPC_DI:
check_insn(ctx, ISA_MIPS_R2);
save_cpu_state(ctx, 1);
- gen_helper_di(t0, cpu_env);
+ gen_helper_di(t0, tcg_env);
gen_store_gpr(t0, rt);
/*
* Stop translation as we may have switched
case OPC_EI:
check_insn(ctx, ISA_MIPS_R2);
save_cpu_state(ctx, 1);
- gen_helper_ei(t0, cpu_env);
+ gen_helper_ei(t0, tcg_env);
gen_store_gpr(t0, rt);
/*
* DISAS_STOP isn't sufficient, we need to ensure we break
{
cpu_gpr[0] = NULL;
for (unsigned i = 1; i < 32; i++)
- cpu_gpr[i] = tcg_global_mem_new(cpu_env,
+ cpu_gpr[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUMIPSState,
active_tc.gpr[i]),
regnames[i]);
for (unsigned i = 1; i < 32; i++) {
g_autofree char *rname = g_strdup_printf("%s[hi]", regnames[i]);
- cpu_gpr_hi[i] = tcg_global_mem_new_i64(cpu_env,
+ cpu_gpr_hi[i] = tcg_global_mem_new_i64(tcg_env,
offsetof(CPUMIPSState,
active_tc.gpr_hi[i]),
rname);
for (unsigned i = 0; i < 32; i++) {
int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]);
- fpu_f64[i] = tcg_global_mem_new_i64(cpu_env, off, fregnames[i]);
+ fpu_f64[i] = tcg_global_mem_new_i64(tcg_env, off, fregnames[i]);
}
msa_translate_init();
- cpu_PC = tcg_global_mem_new(cpu_env,
+ cpu_PC = tcg_global_mem_new(tcg_env,
offsetof(CPUMIPSState, active_tc.PC), "PC");
for (unsigned i = 0; i < MIPS_DSP_ACC; i++) {
- cpu_HI[i] = tcg_global_mem_new(cpu_env,
+ cpu_HI[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUMIPSState, active_tc.HI[i]),
regnames_HI[i]);
- cpu_LO[i] = tcg_global_mem_new(cpu_env,
+ cpu_LO[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUMIPSState, active_tc.LO[i]),
regnames_LO[i]);
}
- cpu_dspctrl = tcg_global_mem_new(cpu_env,
+ cpu_dspctrl = tcg_global_mem_new(tcg_env,
offsetof(CPUMIPSState,
active_tc.DSPControl),
"DSPControl");
- bcond = tcg_global_mem_new(cpu_env,
+ bcond = tcg_global_mem_new(tcg_env,
offsetof(CPUMIPSState, bcond), "bcond");
- btarget = tcg_global_mem_new(cpu_env,
+ btarget = tcg_global_mem_new(tcg_env,
offsetof(CPUMIPSState, btarget), "btarget");
- hflags = tcg_global_mem_new_i32(cpu_env,
+ hflags = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUMIPSState, hflags), "hflags");
- fpu_fcr0 = tcg_global_mem_new_i32(cpu_env,
+ fpu_fcr0 = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUMIPSState, active_fpu.fcr0),
"fcr0");
- fpu_fcr31 = tcg_global_mem_new_i32(cpu_env,
+ fpu_fcr31 = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUMIPSState, active_fpu.fcr31),
"fcr31");
- cpu_lladdr = tcg_global_mem_new(cpu_env, offsetof(CPUMIPSState, lladdr),
+ cpu_lladdr = tcg_global_mem_new(tcg_env, offsetof(CPUMIPSState, lladdr),
"lladdr");
- cpu_llval = tcg_global_mem_new(cpu_env, offsetof(CPUMIPSState, llval),
+ cpu_llval = tcg_global_mem_new(tcg_env, offsetof(CPUMIPSState, llval),
"llval");
if (TARGET_LONG_BITS == 32) {
};
#define gen_helper_0e1i(name, arg1, arg2) do { \
- gen_helper_##name(cpu_env, arg1, tcg_constant_i32(arg2)); \
+ gen_helper_##name(tcg_env, arg1, tcg_constant_i32(arg2)); \
} while (0)
#define gen_helper_1e0i(name, ret, arg1) do { \
- gen_helper_##name(ret, cpu_env, tcg_constant_i32(arg1)); \
+ gen_helper_##name(ret, tcg_env, tcg_constant_i32(arg1)); \
} while (0)
#define gen_helper_0e2i(name, arg1, arg2, arg3) do { \
- gen_helper_##name(cpu_env, arg1, arg2, tcg_constant_i32(arg3));\
+ gen_helper_##name(tcg_env, arg1, arg2, tcg_constant_i32(arg3));\
} while (0)
void generate_exception(DisasContext *ctx, int excp);
gen_load_gpr(t0, a->rs);
gen_load_gpr(t1, a->rt);
- gen_helper_mult_acc(t0, cpu_env, t0, t1);
+ gen_helper_mult_acc(t0, tcg_env, t0, t1);
gen_store_gpr(t0, a->rd);
return true;
{
/* Note that PC is advanced for all hardware exceptions. */
tcg_gen_movi_tl(cpu_pc, dc->base.pc_next);
- gen_helper_raise_exception(cpu_env, tcg_constant_i32(index));
+ gen_helper_raise_exception(tcg_env, tcg_constant_i32(index));
dc->base.is_jmp = DISAS_NORETURN;
}
tcg_gen_lookup_and_goto_ptr();
gen_set_label(l);
- tcg_gen_st_tl(dest, cpu_env, offsetof(CPUNios2State, ctrl[CR_BADADDR]));
+ tcg_gen_st_tl(dest, tcg_env, offsetof(CPUNios2State, ctrl[CR_BADADDR]));
t_gen_helper_raise_exception(dc, EXCP_UNALIGND);
dc->base.is_jmp = DISAS_NORETURN;
#else
I_TYPE(instr, code);
TCGv dest = dest_gpr(dc, instr.b);
- gen_helper_rdprs(dest, cpu_env, tcg_constant_i32(instr.a));
+ gen_helper_rdprs(dest, tcg_env, tcg_constant_i32(instr.a));
tcg_gen_addi_tl(dest, dest, instr.imm16.s);
#endif
}
#else
if (FIELD_EX32(dc->tb_flags, TBFLAGS, CRS0)) {
TCGv tmp = tcg_temp_new();
- tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, ctrl[CR_ESTATUS]));
- gen_helper_eret(cpu_env, tmp, load_gpr(dc, R_EA));
+ tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPUNios2State, ctrl[CR_ESTATUS]));
+ gen_helper_eret(tcg_env, tmp, load_gpr(dc, R_EA));
} else {
- gen_helper_eret(cpu_env, load_gpr(dc, R_SSTATUS), load_gpr(dc, R_EA));
+ gen_helper_eret(tcg_env, load_gpr(dc, R_SSTATUS), load_gpr(dc, R_EA));
}
dc->base.is_jmp = DISAS_NORETURN;
#endif
g_assert_not_reached();
#else
TCGv tmp = tcg_temp_new();
- tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, ctrl[CR_BSTATUS]));
- gen_helper_eret(cpu_env, tmp, load_gpr(dc, R_BA));
+ tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPUNios2State, ctrl[CR_BSTATUS]));
+ gen_helper_eret(tcg_env, tmp, load_gpr(dc, R_BA));
dc->base.is_jmp = DISAS_NORETURN;
#endif
*/
t1 = tcg_temp_new();
t2 = tcg_temp_new();
- tcg_gen_ld_tl(t1, cpu_env, offsetof(CPUNios2State, ctrl[CR_IPENDING]));
- tcg_gen_ld_tl(t2, cpu_env, offsetof(CPUNios2State, ctrl[CR_IENABLE]));
+ tcg_gen_ld_tl(t1, tcg_env, offsetof(CPUNios2State, ctrl[CR_IPENDING]));
+ tcg_gen_ld_tl(t2, tcg_env, offsetof(CPUNios2State, ctrl[CR_IENABLE]));
tcg_gen_and_tl(dest, t1, t2);
break;
default:
- tcg_gen_ld_tl(dest, cpu_env,
+ tcg_gen_ld_tl(dest, tcg_env,
offsetof(CPUNios2State, ctrl[instr.imm5]));
break;
}
switch (instr.imm5) {
case CR_PTEADDR:
- gen_helper_mmu_write_pteaddr(cpu_env, v);
+ gen_helper_mmu_write_pteaddr(tcg_env, v);
break;
case CR_TLBACC:
- gen_helper_mmu_write_tlbacc(cpu_env, v);
+ gen_helper_mmu_write_tlbacc(tcg_env, v);
break;
case CR_TLBMISC:
- gen_helper_mmu_write_tlbmisc(cpu_env, v);
+ gen_helper_mmu_write_tlbmisc(tcg_env, v);
break;
case CR_STATUS:
case CR_IENABLE:
default:
if (wr == -1) {
/* The register is entirely writable. */
- tcg_gen_st_tl(v, cpu_env, ofs);
+ tcg_gen_st_tl(v, tcg_env, ofs);
} else {
/*
* The register is partially read-only or reserved:
if (ro != 0) {
TCGv o = tcg_temp_new();
- tcg_gen_ld_tl(o, cpu_env, ofs);
+ tcg_gen_ld_tl(o, tcg_env, ofs);
tcg_gen_andi_tl(o, o, ro);
tcg_gen_or_tl(n, n, o);
}
- tcg_gen_st_tl(n, cpu_env, ofs);
+ tcg_gen_st_tl(n, tcg_env, ofs);
}
break;
}
g_assert_not_reached();
#else
R_TYPE(instr, code);
- gen_helper_wrprs(cpu_env, tcg_constant_i32(instr.c),
+ gen_helper_wrprs(tcg_env, tcg_constant_i32(instr.c),
load_gpr(dc, instr.a));
/*
* The expected write to PRS[r0] is 0, from CRS[r0].
static void divs(DisasContext *dc, uint32_t code, uint32_t flags)
{
R_TYPE(instr, (code));
- gen_helper_divs(dest_gpr(dc, instr.c), cpu_env,
+ gen_helper_divs(dest_gpr(dc, instr.c), tcg_env,
load_gpr(dc, instr.a), load_gpr(dc, instr.b));
}
static void divu(DisasContext *dc, uint32_t code, uint32_t flags)
{
R_TYPE(instr, (code));
- gen_helper_divu(dest_gpr(dc, instr.c), cpu_env,
+ gen_helper_divu(dest_gpr(dc, instr.c), tcg_env,
load_gpr(dc, instr.a), load_gpr(dc, instr.b));
}
* things easier for cpu_loop if we pop this into env->error_code.
*/
R_TYPE(instr, code);
- tcg_gen_st_i32(tcg_constant_i32(instr.imm5), cpu_env,
+ tcg_gen_st_i32(tcg_constant_i32(instr.imm5), tcg_env,
offsetof(CPUNios2State, error_code));
#endif
t_gen_helper_raise_exception(dc, EXCP_TRAP);
void nios2_tcg_init(void)
{
#ifndef CONFIG_USER_ONLY
- TCGv_ptr crs = tcg_global_mem_new_ptr(cpu_env,
+ TCGv_ptr crs = tcg_global_mem_new_ptr(tcg_env,
offsetof(CPUNios2State, regs), "crs");
for (int i = 0; i < NUM_GP_REGS; i++) {
#endif
for (int i = 0; i < NUM_GP_REGS; i++) {
- cpu_R[i] = tcg_global_mem_new(cpu_env, offsetof_regs0(i),
+ cpu_R[i] = tcg_global_mem_new(tcg_env, offsetof_regs0(i),
gr_regnames[i]);
}
#undef offsetof_regs0
- cpu_pc = tcg_global_mem_new(cpu_env,
+ cpu_pc = tcg_global_mem_new(tcg_env,
offsetof(CPUNios2State, pc), "pc");
}
};
int i;
- cpu_sr = tcg_global_mem_new(cpu_env,
+ cpu_sr = tcg_global_mem_new(tcg_env,
offsetof(CPUOpenRISCState, sr), "sr");
- cpu_dflag = tcg_global_mem_new_i32(cpu_env,
+ cpu_dflag = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUOpenRISCState, dflag),
"dflag");
- cpu_pc = tcg_global_mem_new(cpu_env,
+ cpu_pc = tcg_global_mem_new(tcg_env,
offsetof(CPUOpenRISCState, pc), "pc");
- cpu_ppc = tcg_global_mem_new(cpu_env,
+ cpu_ppc = tcg_global_mem_new(tcg_env,
offsetof(CPUOpenRISCState, ppc), "ppc");
- jmp_pc = tcg_global_mem_new(cpu_env,
+ jmp_pc = tcg_global_mem_new(tcg_env,
offsetof(CPUOpenRISCState, jmp_pc), "jmp_pc");
- cpu_sr_f = tcg_global_mem_new(cpu_env,
+ cpu_sr_f = tcg_global_mem_new(tcg_env,
offsetof(CPUOpenRISCState, sr_f), "sr_f");
- cpu_sr_cy = tcg_global_mem_new(cpu_env,
+ cpu_sr_cy = tcg_global_mem_new(tcg_env,
offsetof(CPUOpenRISCState, sr_cy), "sr_cy");
- cpu_sr_ov = tcg_global_mem_new(cpu_env,
+ cpu_sr_ov = tcg_global_mem_new(tcg_env,
offsetof(CPUOpenRISCState, sr_ov), "sr_ov");
- cpu_lock_addr = tcg_global_mem_new(cpu_env,
+ cpu_lock_addr = tcg_global_mem_new(tcg_env,
offsetof(CPUOpenRISCState, lock_addr),
"lock_addr");
- cpu_lock_value = tcg_global_mem_new(cpu_env,
+ cpu_lock_value = tcg_global_mem_new(tcg_env,
offsetof(CPUOpenRISCState, lock_value),
"lock_value");
- fpcsr = tcg_global_mem_new_i32(cpu_env,
+ fpcsr = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUOpenRISCState, fpcsr),
"fpcsr");
- cpu_mac = tcg_global_mem_new_i64(cpu_env,
+ cpu_mac = tcg_global_mem_new_i64(tcg_env,
offsetof(CPUOpenRISCState, mac),
"mac");
for (i = 0; i < 32; i++) {
- cpu_regs[i] = tcg_global_mem_new(cpu_env,
+ cpu_regs[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUOpenRISCState,
shadow_gpr[0][i]),
regnames[i]);
static void gen_exception(DisasContext *dc, unsigned int excp)
{
- gen_helper_exception(cpu_env, tcg_constant_i32(excp));
+ gen_helper_exception(tcg_env, tcg_constant_i32(excp));
}
static void gen_illegal_exception(DisasContext *dc)
static void gen_ove_cy(DisasContext *dc)
{
if (dc->tb_flags & SR_OVE) {
- gen_helper_ove_cy(cpu_env);
+ gen_helper_ove_cy(tcg_env);
}
}
static void gen_ove_ov(DisasContext *dc)
{
if (dc->tb_flags & SR_OVE) {
- gen_helper_ove_ov(cpu_env);
+ gen_helper_ove_ov(tcg_env);
}
}
static void gen_ove_cyov(DisasContext *dc)
{
if (dc->tb_flags & SR_OVE) {
- gen_helper_ove_cyov(cpu_env);
+ gen_helper_ove_cyov(tcg_env);
}
}
}
tcg_gen_ori_tl(spr, cpu_R(dc, a->a), a->k);
- gen_helper_mfspr(cpu_R(dc, a->d), cpu_env, cpu_R(dc, a->d), spr);
+ gen_helper_mfspr(cpu_R(dc, a->d), tcg_env, cpu_R(dc, a->d), spr);
return true;
}
dc->base.is_jmp = DISAS_EXIT;
tcg_gen_ori_tl(spr, cpu_R(dc, a->a), a->k);
- gen_helper_mtspr(cpu_env, spr, cpu_R(dc, a->b));
+ gen_helper_mtspr(tcg_env, spr, cpu_R(dc, a->b));
return true;
}
if (is_user(dc)) {
gen_illegal_exception(dc);
} else {
- gen_helper_rfe(cpu_env);
+ gen_helper_rfe(tcg_env);
dc->base.is_jmp = DISAS_EXIT;
}
return true;
return false;
}
check_r0_write(dc, a->d);
- fn(cpu_R(dc, a->d), cpu_env, cpu_R(dc, a->a));
- gen_helper_update_fpcsr(cpu_env);
+ fn(cpu_R(dc, a->d), tcg_env, cpu_R(dc, a->a));
+ gen_helper_update_fpcsr(tcg_env);
return true;
}
return false;
}
check_r0_write(dc, a->d);
- fn(cpu_R(dc, a->d), cpu_env, cpu_R(dc, a->a), cpu_R(dc, a->b));
- gen_helper_update_fpcsr(cpu_env);
+ fn(cpu_R(dc, a->d), tcg_env, cpu_R(dc, a->a), cpu_R(dc, a->b));
+ gen_helper_update_fpcsr(tcg_env);
return true;
}
return false;
}
if (swap) {
- fn(cpu_sr_f, cpu_env, cpu_R(dc, a->b), cpu_R(dc, a->a));
+ fn(cpu_sr_f, tcg_env, cpu_R(dc, a->b), cpu_R(dc, a->a));
} else {
- fn(cpu_sr_f, cpu_env, cpu_R(dc, a->a), cpu_R(dc, a->b));
+ fn(cpu_sr_f, tcg_env, cpu_R(dc, a->a), cpu_R(dc, a->b));
}
if (inv) {
tcg_gen_xori_tl(cpu_sr_f, cpu_sr_f, 1);
}
- gen_helper_update_fpcsr(cpu_env);
+ gen_helper_update_fpcsr(tcg_env);
return true;
}
return false;
}
check_r0_write(dc, a->d);
- gen_helper_float_madd_s(cpu_R(dc, a->d), cpu_env, cpu_R(dc, a->d),
+ gen_helper_float_madd_s(cpu_R(dc, a->d), tcg_env, cpu_R(dc, a->d),
cpu_R(dc, a->a), cpu_R(dc, a->b));
- gen_helper_update_fpcsr(cpu_env);
+ gen_helper_update_fpcsr(tcg_env);
return true;
}
t1 = tcg_temp_new_i64();
load_pair(dc, t0, a->a, a->ap);
load_pair(dc, t1, a->b, a->bp);
- fn(t0, cpu_env, t0, t1);
+ fn(t0, tcg_env, t0, t1);
save_pair(dc, t0, a->d, a->dp);
- gen_helper_update_fpcsr(cpu_env);
+ gen_helper_update_fpcsr(tcg_env);
return true;
}
t0 = tcg_temp_new_i64();
load_pair(dc, t0, a->a, a->ap);
- fn(t0, cpu_env, t0);
+ fn(t0, tcg_env, t0);
save_pair(dc, t0, a->d, a->dp);
- gen_helper_update_fpcsr(cpu_env);
+ gen_helper_update_fpcsr(tcg_env);
return true;
}
load_pair(dc, t0, a->a, a->ap);
load_pair(dc, t1, a->b, a->bp);
if (swap) {
- fn(cpu_sr_f, cpu_env, t1, t0);
+ fn(cpu_sr_f, tcg_env, t1, t0);
} else {
- fn(cpu_sr_f, cpu_env, t0, t1);
+ fn(cpu_sr_f, tcg_env, t0, t1);
}
if (inv) {
tcg_gen_xori_tl(cpu_sr_f, cpu_sr_f, 1);
}
- gen_helper_update_fpcsr(cpu_env);
+ gen_helper_update_fpcsr(tcg_env);
return true;
}
check_r0_write(dc, a->d);
t0 = tcg_temp_new_i64();
- gen_helper_stod(t0, cpu_env, cpu_R(dc, a->a));
+ gen_helper_stod(t0, tcg_env, cpu_R(dc, a->a));
save_pair(dc, t0, a->d, a->dp);
- gen_helper_update_fpcsr(cpu_env);
+ gen_helper_update_fpcsr(tcg_env);
return true;
}
t0 = tcg_temp_new_i64();
load_pair(dc, t0, a->a, a->ap);
- gen_helper_dtos(cpu_R(dc, a->d), cpu_env, t0);
+ gen_helper_dtos(cpu_R(dc, a->d), tcg_env, t0);
- gen_helper_update_fpcsr(cpu_env);
+ gen_helper_update_fpcsr(tcg_env);
return true;
}
load_pair(dc, t0, a->d, a->dp);
load_pair(dc, t1, a->a, a->ap);
load_pair(dc, t2, a->b, a->bp);
- gen_helper_float_madd_d(t0, cpu_env, t0, t1, t2);
+ gen_helper_float_madd_d(t0, tcg_env, t0, t1, t2);
save_pair(dc, t0, a->d, a->dp);
- gen_helper_update_fpcsr(cpu_env);
+ gen_helper_update_fpcsr(tcg_env);
return true;
}
* translator_io_start() beforehand.
*/
translator_io_start(&ctx->base);
- gen_helper_store_mmcr0(cpu_env, val);
+ gen_helper_store_mmcr0(tcg_env, val);
/*
* End the translation block because MMCR0 writes can change
TCGv_i32 t_sprn = tcg_constant_i32(sprn);
translator_io_start(&ctx->base);
- gen_helper_read_pmc(cpu_gpr[gprn], cpu_env, t_sprn);
+ gen_helper_read_pmc(cpu_gpr[gprn], tcg_env, t_sprn);
}
void spr_read_PMC14_ureg(DisasContext *ctx, int gprn, int sprn)
TCGv_i32 t_sprn = tcg_constant_i32(sprn);
translator_io_start(&ctx->base);
- gen_helper_store_pmc(cpu_env, t_sprn, cpu_gpr[gprn]);
+ gen_helper_store_pmc(tcg_env, t_sprn, cpu_gpr[gprn]);
}
void spr_write_PMC14_ureg(DisasContext *ctx, int sprn, int gprn)
void spr_write_MMCR1(DisasContext *ctx, int sprn, int gprn)
{
translator_io_start(&ctx->base);
- gen_helper_store_mmcr1(cpu_env, cpu_gpr[gprn]);
+ gen_helper_store_mmcr1(tcg_env, cpu_gpr[gprn]);
}
#else
void spr_read_MMCR0_ureg(DisasContext *ctx, int gprn, int sprn)
for (i = 0; i < 8; i++) {
snprintf(p, cpu_reg_names_size, "crf%d", i);
- cpu_crf[i] = tcg_global_mem_new_i32(cpu_env,
+ cpu_crf[i] = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUPPCState, crf[i]), p);
p += 5;
cpu_reg_names_size -= 5;
for (i = 0; i < 32; i++) {
snprintf(p, cpu_reg_names_size, "r%d", i);
- cpu_gpr[i] = tcg_global_mem_new(cpu_env,
+ cpu_gpr[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUPPCState, gpr[i]), p);
p += (i < 10) ? 3 : 4;
cpu_reg_names_size -= (i < 10) ? 3 : 4;
snprintf(p, cpu_reg_names_size, "r%dH", i);
- cpu_gprh[i] = tcg_global_mem_new(cpu_env,
+ cpu_gprh[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUPPCState, gprh[i]), p);
p += (i < 10) ? 4 : 5;
cpu_reg_names_size -= (i < 10) ? 4 : 5;
}
- cpu_nip = tcg_global_mem_new(cpu_env,
+ cpu_nip = tcg_global_mem_new(tcg_env,
offsetof(CPUPPCState, nip), "nip");
- cpu_msr = tcg_global_mem_new(cpu_env,
+ cpu_msr = tcg_global_mem_new(tcg_env,
offsetof(CPUPPCState, msr), "msr");
- cpu_ctr = tcg_global_mem_new(cpu_env,
+ cpu_ctr = tcg_global_mem_new(tcg_env,
offsetof(CPUPPCState, ctr), "ctr");
- cpu_lr = tcg_global_mem_new(cpu_env,
+ cpu_lr = tcg_global_mem_new(tcg_env,
offsetof(CPUPPCState, lr), "lr");
#if defined(TARGET_PPC64)
- cpu_cfar = tcg_global_mem_new(cpu_env,
+ cpu_cfar = tcg_global_mem_new(tcg_env,
offsetof(CPUPPCState, cfar), "cfar");
#endif
- cpu_xer = tcg_global_mem_new(cpu_env,
+ cpu_xer = tcg_global_mem_new(tcg_env,
offsetof(CPUPPCState, xer), "xer");
- cpu_so = tcg_global_mem_new(cpu_env,
+ cpu_so = tcg_global_mem_new(tcg_env,
offsetof(CPUPPCState, so), "SO");
- cpu_ov = tcg_global_mem_new(cpu_env,
+ cpu_ov = tcg_global_mem_new(tcg_env,
offsetof(CPUPPCState, ov), "OV");
- cpu_ca = tcg_global_mem_new(cpu_env,
+ cpu_ca = tcg_global_mem_new(tcg_env,
offsetof(CPUPPCState, ca), "CA");
- cpu_ov32 = tcg_global_mem_new(cpu_env,
+ cpu_ov32 = tcg_global_mem_new(tcg_env,
offsetof(CPUPPCState, ov32), "OV32");
- cpu_ca32 = tcg_global_mem_new(cpu_env,
+ cpu_ca32 = tcg_global_mem_new(tcg_env,
offsetof(CPUPPCState, ca32), "CA32");
- cpu_reserve = tcg_global_mem_new(cpu_env,
+ cpu_reserve = tcg_global_mem_new(tcg_env,
offsetof(CPUPPCState, reserve_addr),
"reserve_addr");
- cpu_reserve_length = tcg_global_mem_new(cpu_env,
+ cpu_reserve_length = tcg_global_mem_new(tcg_env,
offsetof(CPUPPCState,
reserve_length),
"reserve_length");
- cpu_reserve_val = tcg_global_mem_new(cpu_env,
+ cpu_reserve_val = tcg_global_mem_new(tcg_env,
offsetof(CPUPPCState, reserve_val),
"reserve_val");
#if defined(TARGET_PPC64)
- cpu_reserve_val2 = tcg_global_mem_new(cpu_env,
+ cpu_reserve_val2 = tcg_global_mem_new(tcg_env,
offsetof(CPUPPCState, reserve_val2),
"reserve_val2");
#endif
- cpu_fpscr = tcg_global_mem_new(cpu_env,
+ cpu_fpscr = tcg_global_mem_new(tcg_env,
offsetof(CPUPPCState, fpscr), "fpscr");
- cpu_access_type = tcg_global_mem_new_i32(cpu_env,
+ cpu_access_type = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUPPCState, access_type),
"access_type");
}
{
if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
/* Restart with exclusive lock. */
- gen_helper_exit_atomic(cpu_env);
+ gen_helper_exit_atomic(tcg_env);
ctx->base.is_jmp = DISAS_NORETURN;
return false;
}
/* SPR load/store helpers */
static inline void gen_load_spr(TCGv t, int reg)
{
- tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
+ tcg_gen_ld_tl(t, tcg_env, offsetof(CPUPPCState, spr[reg]));
}
static inline void gen_store_spr(int reg, TCGv t)
{
- tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
+ tcg_gen_st_tl(t, tcg_env, offsetof(CPUPPCState, spr[reg]));
}
static inline void gen_set_access_type(DisasContext *ctx, int access_type)
gen_update_nip(ctx, ctx->cia);
t0 = tcg_constant_i32(excp);
t1 = tcg_constant_i32(error);
- gen_helper_raise_exception_err(cpu_env, t0, t1);
+ gen_helper_raise_exception_err(tcg_env, t0, t1);
ctx->base.is_jmp = DISAS_NORETURN;
}
*/
gen_update_nip(ctx, ctx->cia);
t0 = tcg_constant_i32(excp);
- gen_helper_raise_exception(cpu_env, t0);
+ gen_helper_raise_exception(tcg_env, t0);
ctx->base.is_jmp = DISAS_NORETURN;
}
gen_update_nip(ctx, nip);
t0 = tcg_constant_i32(excp);
- gen_helper_raise_exception(cpu_env, t0);
+ gen_helper_raise_exception(tcg_env, t0);
ctx->base.is_jmp = DISAS_NORETURN;
}
static void gen_ppc_maybe_interrupt(DisasContext *ctx)
{
translator_io_start(&ctx->base);
- gen_helper_ppc_maybe_interrupt(cpu_env);
+ gen_helper_ppc_maybe_interrupt(tcg_env);
}
#endif
gen_load_spr(t0, SPR_BOOKE_DBSR);
tcg_gen_ori_tl(t0, t0, dbsr);
gen_store_spr(SPR_BOOKE_DBSR, t0);
- gen_helper_raise_exception(cpu_env,
+ gen_helper_raise_exception(tcg_env,
tcg_constant_i32(POWERPC_EXCP_DEBUG));
ctx->base.is_jmp = DISAS_NORETURN;
} else {
if (!rfi_type) { /* BookS does not single step rfi type instructions */
TCGv t0 = tcg_temp_new();
tcg_gen_movi_tl(t0, ctx->cia);
- gen_helper_book3s_trace(cpu_env, t0);
+ gen_helper_book3s_trace(tcg_env, t0);
ctx->base.is_jmp = DISAS_NORETURN;
}
}
{
#ifdef PPC_DUMP_SPR_ACCESSES
TCGv_i32 t0 = tcg_constant_i32(sprn);
- gen_helper_load_dump_spr(cpu_env, t0);
+ gen_helper_load_dump_spr(tcg_env, t0);
#endif
}
{
#ifdef PPC_DUMP_SPR_ACCESSES
TCGv_i32 t0 = tcg_constant_i32(sprn);
- gen_helper_store_dump_spr(cpu_env, t0);
+ gen_helper_store_dump_spr(tcg_env, t0);
#endif
}
return;
}
- gen_helper_spr_core_write_generic(cpu_env, tcg_constant_i32(sprn),
+ gen_helper_spr_core_write_generic(tcg_env, tcg_constant_i32(sprn),
cpu_gpr[gprn]);
spr_store_dump_spr(sprn);
}
return;
}
- gen_helper_spr_write_CTRL(cpu_env, tcg_constant_i32(sprn),
+ gen_helper_spr_write_CTRL(tcg_env, tcg_constant_i32(sprn),
cpu_gpr[gprn]);
out:
spr_store_dump_spr(sprn);
void spr_write_ciabr(DisasContext *ctx, int sprn, int gprn)
{
translator_io_start(&ctx->base);
- gen_helper_store_ciabr(cpu_env, cpu_gpr[gprn]);
+ gen_helper_store_ciabr(tcg_env, cpu_gpr[gprn]);
}
/* Watchpoint */
void spr_write_dawr0(DisasContext *ctx, int sprn, int gprn)
{
translator_io_start(&ctx->base);
- gen_helper_store_dawr0(cpu_env, cpu_gpr[gprn]);
+ gen_helper_store_dawr0(tcg_env, cpu_gpr[gprn]);
}
void spr_write_dawrx0(DisasContext *ctx, int sprn, int gprn)
{
translator_io_start(&ctx->base);
- gen_helper_store_dawrx0(cpu_env, cpu_gpr[gprn]);
+ gen_helper_store_dawrx0(tcg_env, cpu_gpr[gprn]);
}
#endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
void spr_read_decr(DisasContext *ctx, int gprn, int sprn)
{
translator_io_start(&ctx->base);
- gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
+ gen_helper_load_decr(cpu_gpr[gprn], tcg_env);
}
void spr_write_decr(DisasContext *ctx, int sprn, int gprn)
{
translator_io_start(&ctx->base);
- gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
+ gen_helper_store_decr(tcg_env, cpu_gpr[gprn]);
}
#endif
void spr_read_tbl(DisasContext *ctx, int gprn, int sprn)
{
translator_io_start(&ctx->base);
- gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
+ gen_helper_load_tbl(cpu_gpr[gprn], tcg_env);
}
void spr_read_tbu(DisasContext *ctx, int gprn, int sprn)
{
translator_io_start(&ctx->base);
- gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
+ gen_helper_load_tbu(cpu_gpr[gprn], tcg_env);
}
void spr_read_atbl(DisasContext *ctx, int gprn, int sprn)
{
- gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
+ gen_helper_load_atbl(cpu_gpr[gprn], tcg_env);
}
void spr_read_atbu(DisasContext *ctx, int gprn, int sprn)
{
- gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
+ gen_helper_load_atbu(cpu_gpr[gprn], tcg_env);
}
#if !defined(CONFIG_USER_ONLY)
void spr_write_tbl(DisasContext *ctx, int sprn, int gprn)
{
translator_io_start(&ctx->base);
- gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
+ gen_helper_store_tbl(tcg_env, cpu_gpr[gprn]);
}
void spr_write_tbu(DisasContext *ctx, int sprn, int gprn)
{
translator_io_start(&ctx->base);
- gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
+ gen_helper_store_tbu(tcg_env, cpu_gpr[gprn]);
}
void spr_write_atbl(DisasContext *ctx, int sprn, int gprn)
{
- gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
+ gen_helper_store_atbl(tcg_env, cpu_gpr[gprn]);
}
void spr_write_atbu(DisasContext *ctx, int sprn, int gprn)
{
- gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
+ gen_helper_store_atbu(tcg_env, cpu_gpr[gprn]);
}
#if defined(TARGET_PPC64)
void spr_read_purr(DisasContext *ctx, int gprn, int sprn)
{
translator_io_start(&ctx->base);
- gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
+ gen_helper_load_purr(cpu_gpr[gprn], tcg_env);
}
void spr_write_purr(DisasContext *ctx, int sprn, int gprn)
{
translator_io_start(&ctx->base);
- gen_helper_store_purr(cpu_env, cpu_gpr[gprn]);
+ gen_helper_store_purr(tcg_env, cpu_gpr[gprn]);
}
/* HDECR */
void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn)
{
translator_io_start(&ctx->base);
- gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env);
+ gen_helper_load_hdecr(cpu_gpr[gprn], tcg_env);
}
void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn)
{
translator_io_start(&ctx->base);
- gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]);
+ gen_helper_store_hdecr(tcg_env, cpu_gpr[gprn]);
}
void spr_read_vtb(DisasContext *ctx, int gprn, int sprn)
{
translator_io_start(&ctx->base);
- gen_helper_load_vtb(cpu_gpr[gprn], cpu_env);
+ gen_helper_load_vtb(cpu_gpr[gprn], tcg_env);
}
void spr_write_vtb(DisasContext *ctx, int sprn, int gprn)
{
translator_io_start(&ctx->base);
- gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]);
+ gen_helper_store_vtb(tcg_env, cpu_gpr[gprn]);
}
void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn)
{
translator_io_start(&ctx->base);
- gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]);
+ gen_helper_store_tbu40(tcg_env, cpu_gpr[gprn]);
}
#endif
/* IBAT0L...IBAT7L */
void spr_read_ibat(DisasContext *ctx, int gprn, int sprn)
{
- tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
+ tcg_gen_ld_tl(cpu_gpr[gprn], tcg_env,
offsetof(CPUPPCState,
IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
}
void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn)
{
- tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
+ tcg_gen_ld_tl(cpu_gpr[gprn], tcg_env,
offsetof(CPUPPCState,
IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4]));
}
void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn)
{
TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0U) / 2);
- gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
+ gen_helper_store_ibatu(tcg_env, t0, cpu_gpr[gprn]);
}
void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn)
{
TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4U) / 2) + 4);
- gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
+ gen_helper_store_ibatu(tcg_env, t0, cpu_gpr[gprn]);
}
void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn)
{
TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0L) / 2);
- gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
+ gen_helper_store_ibatl(tcg_env, t0, cpu_gpr[gprn]);
}
void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn)
{
TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4L) / 2) + 4);
- gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
+ gen_helper_store_ibatl(tcg_env, t0, cpu_gpr[gprn]);
}
/* DBAT0U...DBAT7U */
/* DBAT0L...DBAT7L */
void spr_read_dbat(DisasContext *ctx, int gprn, int sprn)
{
- tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
+ tcg_gen_ld_tl(cpu_gpr[gprn], tcg_env,
offsetof(CPUPPCState,
DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
}
void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn)
{
- tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
+ tcg_gen_ld_tl(cpu_gpr[gprn], tcg_env,
offsetof(CPUPPCState,
DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
}
void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn)
{
TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0U) / 2);
- gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
+ gen_helper_store_dbatu(tcg_env, t0, cpu_gpr[gprn]);
}
void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn)
{
TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4U) / 2) + 4);
- gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
+ gen_helper_store_dbatu(tcg_env, t0, cpu_gpr[gprn]);
}
void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn)
{
TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0L) / 2);
- gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
+ gen_helper_store_dbatl(tcg_env, t0, cpu_gpr[gprn]);
}
void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn)
{
TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4L) / 2) + 4);
- gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
+ gen_helper_store_dbatl(tcg_env, t0, cpu_gpr[gprn]);
}
/* SDR1 */
void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn)
{
- gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
+ gen_helper_store_sdr1(tcg_env, cpu_gpr[gprn]);
}
#if defined(TARGET_PPC64)
/* PIDR */
void spr_write_pidr(DisasContext *ctx, int sprn, int gprn)
{
- gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]);
+ gen_helper_store_pidr(tcg_env, cpu_gpr[gprn]);
}
void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn)
{
- gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]);
+ gen_helper_store_lpidr(tcg_env, cpu_gpr[gprn]);
}
void spr_read_hior(DisasContext *ctx, int gprn, int sprn)
{
- tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
+ tcg_gen_ld_tl(cpu_gpr[gprn], tcg_env, offsetof(CPUPPCState, excp_prefix));
}
void spr_write_hior(DisasContext *ctx, int sprn, int gprn)
{
TCGv t0 = tcg_temp_new();
tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
- tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
+ tcg_gen_st_tl(t0, tcg_env, offsetof(CPUPPCState, excp_prefix));
}
void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn)
{
- gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]);
+ gen_helper_store_ptcr(tcg_env, cpu_gpr[gprn]);
}
void spr_write_pcr(DisasContext *ctx, int sprn, int gprn)
{
- gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]);
+ gen_helper_store_pcr(tcg_env, cpu_gpr[gprn]);
}
/* DPDES */
return;
}
- gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env);
+ gen_helper_load_dpdes(cpu_gpr[gprn], tcg_env);
}
void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn)
return;
}
- gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]);
+ gen_helper_store_dpdes(tcg_env, cpu_gpr[gprn]);
}
#endif
#endif
void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn)
{
translator_io_start(&ctx->base);
- gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
+ gen_helper_load_40x_pit(cpu_gpr[gprn], tcg_env);
}
void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn)
{
translator_io_start(&ctx->base);
- gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
+ gen_helper_store_40x_pit(tcg_env, cpu_gpr[gprn]);
}
void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn)
{
translator_io_start(&ctx->base);
gen_store_spr(sprn, cpu_gpr[gprn]);
- gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
+ gen_helper_store_40x_dbcr0(tcg_env, cpu_gpr[gprn]);
/* We must stop translation as we may have rebooted */
ctx->base.is_jmp = DISAS_EXIT_UPDATE;
}
void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn)
{
translator_io_start(&ctx->base);
- gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
+ gen_helper_store_40x_sler(tcg_env, cpu_gpr[gprn]);
}
void spr_write_40x_tcr(DisasContext *ctx, int sprn, int gprn)
{
translator_io_start(&ctx->base);
- gen_helper_store_40x_tcr(cpu_env, cpu_gpr[gprn]);
+ gen_helper_store_40x_tcr(tcg_env, cpu_gpr[gprn]);
}
void spr_write_40x_tsr(DisasContext *ctx, int sprn, int gprn)
{
translator_io_start(&ctx->base);
- gen_helper_store_40x_tsr(cpu_env, cpu_gpr[gprn]);
+ gen_helper_store_40x_tsr(tcg_env, cpu_gpr[gprn]);
}
void spr_write_40x_pid(DisasContext *ctx, int sprn, int gprn)
{
TCGv t0 = tcg_temp_new();
tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xFF);
- gen_helper_store_40x_pid(cpu_env, t0);
+ gen_helper_store_40x_pid(tcg_env, t0);
}
void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn)
{
translator_io_start(&ctx->base);
- gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
+ gen_helper_store_booke_tcr(tcg_env, cpu_gpr[gprn]);
}
void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn)
{
translator_io_start(&ctx->base);
- gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
+ gen_helper_store_booke_tsr(tcg_env, cpu_gpr[gprn]);
}
#endif
void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn)
{
TCGv_i32 t0 = tcg_temp_new_i32();
- tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
+ tcg_gen_ld_i32(t0, tcg_env, offsetof(CPUPPCState, spe_fscr));
tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
}
{
TCGv_i32 t0 = tcg_temp_new_i32();
tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
- tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
+ tcg_gen_st_i32(t0, tcg_env, offsetof(CPUPPCState, spe_fscr));
}
#if !defined(CONFIG_USER_ONLY)
void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn)
{
TCGv t0 = tcg_temp_new();
- tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
+ tcg_gen_ld_tl(t0, tcg_env, offsetof(CPUPPCState, ivpr_mask));
tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
- tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
+ tcg_gen_st_tl(t0, tcg_env, offsetof(CPUPPCState, excp_prefix));
gen_store_spr(sprn, t0);
}
}
TCGv t0 = tcg_temp_new();
- tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
+ tcg_gen_ld_tl(t0, tcg_env, offsetof(CPUPPCState, ivor_mask));
tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
- tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
+ tcg_gen_st_tl(t0, tcg_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
gen_store_spr(sprn, t0);
}
#endif
#ifndef CONFIG_USER_ONLY
void spr_read_thrm(DisasContext *ctx, int gprn, int sprn)
{
- gen_helper_fixup_thrm(cpu_env);
+ gen_helper_fixup_thrm(tcg_env);
gen_load_spr(cpu_gpr[gprn], sprn);
spr_load_dump_spr(sprn);
}
void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn)
{
- gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]);
+ gen_helper_booke206_tlbflush(tcg_env, cpu_gpr[gprn]);
}
void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn)
{
TCGv_i32 t0 = tcg_constant_i32(sprn);
- gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
+ gen_helper_booke_setpid(tcg_env, t0, cpu_gpr[gprn]);
}
void spr_write_eplc(DisasContext *ctx, int sprn, int gprn)
{
- gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]);
+ gen_helper_booke_set_eplc(tcg_env, cpu_gpr[gprn]);
}
void spr_write_epsc(DisasContext *ctx, int sprn, int gprn)
{
- gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]);
+ gen_helper_booke_set_epsc(tcg_env, cpu_gpr[gprn]);
}
#endif
TCGv_i32 t2 = tcg_constant_i32(sprn);
TCGv_i32 t3 = tcg_constant_i32(cause);
- gen_helper_fscr_facility_check(cpu_env, t1, t2, t3);
+ gen_helper_fscr_facility_check(tcg_env, t1, t2, t3);
}
static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn,
TCGv_i32 t2 = tcg_constant_i32(sprn);
TCGv_i32 t3 = tcg_constant_i32(cause);
- gen_helper_msr_facility_check(cpu_env, t1, t2, t3);
+ gen_helper_msr_facility_check(tcg_env, t1, t2, t3);
}
void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn)
void spr_read_tfmr(DisasContext *ctx, int gprn, int sprn)
{
- gen_helper_load_tfmr(cpu_gpr[gprn], cpu_env);
+ gen_helper_load_tfmr(cpu_gpr[gprn], tcg_env);
}
void spr_write_tfmr(DisasContext *ctx, int sprn, int gprn)
{
- gen_helper_store_tfmr(cpu_env, cpu_gpr[gprn]);
+ gen_helper_store_tfmr(tcg_env, cpu_gpr[gprn]);
}
void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn)
{
translator_io_start(&ctx->base);
- gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]);
+ gen_helper_store_lpcr(tcg_env, cpu_gpr[gprn]);
}
#endif /* !defined(CONFIG_USER_ONLY) */
static void gen_##name(DisasContext *ctx) \
{ \
TCGv_i32 t0 = tcg_constant_i32(compute_ov); \
- gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
+ gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], tcg_env, \
cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
if (unlikely(Rc(ctx->opcode) != 0)) { \
gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
static void gen_pause(DisasContext *ctx)
{
TCGv_i32 t0 = tcg_constant_i32(0);
- tcg_gen_st_i32(t0, cpu_env,
+ tcg_gen_st_i32(t0, tcg_env,
-offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
/* Stop translation, this gives other CPUs a chance to run */
/* sraw & sraw. */
static void gen_sraw(DisasContext *ctx)
{
- gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
+ gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], tcg_env,
cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
if (unlikely(Rc(ctx->opcode) != 0)) {
gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
/* srad & srad. */
static void gen_srad(DisasContext *ctx)
{
- gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
+ gen_helper_srad(cpu_gpr[rA(ctx->opcode)], tcg_env,
cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
if (unlikely(Rc(ctx->opcode) != 0)) {
gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
t0 = tcg_temp_new();
t1 = tcg_constant_i32(rD(ctx->opcode));
gen_addr_imm_index(ctx, t0, 0);
- gen_helper_lmw(cpu_env, t0, t1);
+ gen_helper_lmw(tcg_env, t0, t1);
}
/* stmw */
t0 = tcg_temp_new();
t1 = tcg_constant_i32(rS(ctx->opcode));
gen_addr_imm_index(ctx, t0, 0);
- gen_helper_stmw(cpu_env, t0, t1);
+ gen_helper_stmw(tcg_env, t0, t1);
}
/*** Integer load and store strings ***/
gen_addr_register(ctx, t0);
t1 = tcg_constant_i32(nb);
t2 = tcg_constant_i32(start);
- gen_helper_lsw(cpu_env, t0, t1, t2);
+ gen_helper_lsw(tcg_env, t0, t1, t2);
}
/* lswx */
t1 = tcg_constant_i32(rD(ctx->opcode));
t2 = tcg_constant_i32(rA(ctx->opcode));
t3 = tcg_constant_i32(rB(ctx->opcode));
- gen_helper_lswx(cpu_env, t0, t1, t2, t3);
+ gen_helper_lswx(tcg_env, t0, t1, t2, t3);
}
/* stswi */
}
t1 = tcg_constant_i32(nb);
t2 = tcg_constant_i32(rS(ctx->opcode));
- gen_helper_stsw(cpu_env, t0, t1, t2);
+ gen_helper_stsw(tcg_env, t0, t1, t2);
}
/* stswx */
tcg_gen_trunc_tl_i32(t1, cpu_xer);
tcg_gen_andi_i32(t1, t1, 0x7F);
t2 = tcg_constant_i32(rS(ctx->opcode));
- gen_helper_stsw(cpu_env, t0, t1, t2);
+ gen_helper_stsw(tcg_env, t0, t1, t2);
}
/*** Memory synchronisation ***/
}
l = gen_new_label();
t = tcg_temp_new_i32();
- tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
+ tcg_gen_ld_i32(t, tcg_env, offsetof(CPUPPCState, tlb_need_flush));
tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l);
if (global) {
- gen_helper_check_tlb_flush_global(cpu_env);
+ gen_helper_check_tlb_flush_global(tcg_env);
} else {
- gen_helper_check_tlb_flush_local(cpu_env);
+ gen_helper_check_tlb_flush_local(tcg_env);
}
gen_set_label(l);
}
if (need_serial) {
/* Restart with exclusive lock. */
- gen_helper_exit_atomic(cpu_env);
+ gen_helper_exit_atomic(tcg_env);
ctx->base.is_jmp = DISAS_NORETURN;
}
}
case 24: /* Store twin */
if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
/* Restart with exclusive lock. */
- gen_helper_exit_atomic(cpu_env);
+ gen_helper_exit_atomic(tcg_env);
ctx->base.is_jmp = DISAS_NORETURN;
} else {
TCGv t = tcg_temp_new();
tcg_gen_mov_tl(cpu_reserve, EA);
tcg_gen_movi_tl(cpu_reserve_length, 16);
- tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val));
- tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2));
+ tcg_gen_st_tl(hi, tcg_env, offsetof(CPUPPCState, reserve_val));
+ tcg_gen_st_tl(lo, tcg_env, offsetof(CPUPPCState, reserve_val2));
}
/* stqcx. */
*/
if (wc == 0) {
TCGv_i32 t0 = tcg_constant_i32(1);
- tcg_gen_st_i32(t0, cpu_env,
+ tcg_gen_st_i32(t0, tcg_env,
-offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
/* Stop translation, as the CPU is supposed to sleep from now */
gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
CHK_HV(ctx);
translator_io_start(&ctx->base);
t = tcg_constant_i32(PPC_PM_DOZE);
- gen_helper_pminsn(cpu_env, t);
+ gen_helper_pminsn(tcg_env, t);
/* Stop translation, as the CPU is supposed to sleep from now */
gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
#endif /* defined(CONFIG_USER_ONLY) */
CHK_HV(ctx);
translator_io_start(&ctx->base);
t = tcg_constant_i32(PPC_PM_NAP);
- gen_helper_pminsn(cpu_env, t);
+ gen_helper_pminsn(tcg_env, t);
/* Stop translation, as the CPU is supposed to sleep from now */
gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
#endif /* defined(CONFIG_USER_ONLY) */
CHK_HV(ctx);
translator_io_start(&ctx->base);
t = tcg_constant_i32(PPC_PM_STOP);
- gen_helper_pminsn(cpu_env, t);
+ gen_helper_pminsn(tcg_env, t);
/* Stop translation, as the CPU is supposed to sleep from now */
gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
#endif /* defined(CONFIG_USER_ONLY) */
CHK_HV(ctx);
translator_io_start(&ctx->base);
t = tcg_constant_i32(PPC_PM_SLEEP);
- gen_helper_pminsn(cpu_env, t);
+ gen_helper_pminsn(tcg_env, t);
/* Stop translation, as the CPU is supposed to sleep from now */
gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
#endif /* defined(CONFIG_USER_ONLY) */
CHK_HV(ctx);
translator_io_start(&ctx->base);
t = tcg_constant_i32(PPC_PM_RVWINKLE);
- gen_helper_pminsn(cpu_env, t);
+ gen_helper_pminsn(tcg_env, t);
/* Stop translation, as the CPU is supposed to sleep from now */
gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
#endif /* defined(CONFIG_USER_ONLY) */
/* Check for overflow, if it's enabled */
if (ctx->mmcr0_pmcjce) {
tcg_gen_brcondi_tl(TCG_COND_LT, t0, PMC_COUNTER_NEGATIVE_VAL, l);
- gen_helper_handle_pmc5_overflow(cpu_env);
+ gen_helper_handle_pmc5_overflow(tcg_env);
}
gen_set_label(l);
} else {
- gen_helper_insns_inc(cpu_env, tcg_constant_i32(ctx->base.num_insns));
+ gen_helper_insns_inc(tcg_env, tcg_constant_i32(ctx->base.num_insns));
}
#else
/*
CHK_SV(ctx);
translator_io_start(&ctx->base);
gen_update_cfar(ctx, ctx->cia);
- gen_helper_rfi(cpu_env);
+ gen_helper_rfi(tcg_env);
ctx->base.is_jmp = DISAS_EXIT;
#endif
}
CHK_SV(ctx);
translator_io_start(&ctx->base);
gen_update_cfar(ctx, ctx->cia);
- gen_helper_rfid(cpu_env);
+ gen_helper_rfid(tcg_env);
ctx->base.is_jmp = DISAS_EXIT;
#endif
}
CHK_SV(ctx);
translator_io_start(&ctx->base);
gen_update_cfar(ctx, ctx->cia);
- gen_helper_rfscv(cpu_env);
+ gen_helper_rfscv(tcg_env);
ctx->base.is_jmp = DISAS_EXIT;
#endif
}
/* Restore CPU state */
CHK_HV(ctx);
translator_io_start(&ctx->base);
- gen_helper_hrfid(cpu_env);
+ gen_helper_hrfid(tcg_env);
ctx->base.is_jmp = DISAS_EXIT;
#endif
}
/* Set the PC back to the faulting instruction. */
gen_update_nip(ctx, ctx->cia);
- gen_helper_scv(cpu_env, tcg_constant_i32(lev));
+ gen_helper_scv(tcg_env, tcg_constant_i32(lev));
ctx->base.is_jmp = DISAS_NORETURN;
}
return;
}
t0 = tcg_constant_i32(TO(ctx->opcode));
- gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
+ gen_helper_tw(tcg_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
t0);
}
}
t0 = tcg_constant_tl(SIMM(ctx->opcode));
t1 = tcg_constant_i32(TO(ctx->opcode));
- gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
+ gen_helper_tw(tcg_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
}
#if defined(TARGET_PPC64)
return;
}
t0 = tcg_constant_i32(TO(ctx->opcode));
- gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
+ gen_helper_td(tcg_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
t0);
}
}
t0 = tcg_constant_tl(SIMM(ctx->opcode));
t1 = tcg_constant_i32(TO(ctx->opcode));
- gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
+ gen_helper_td(tcg_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
}
#endif
tcg_gen_andi_tl(t1, cpu_msr, ~mask);
tcg_gen_or_tl(t0, t0, t1);
- gen_helper_store_msr(cpu_env, t0);
+ gen_helper_store_msr(tcg_env, t0);
/* Must stop the translation as machine state (may have) changed */
ctx->base.is_jmp = DISAS_EXIT_UPDATE;
tcg_gen_andi_tl(t1, cpu_msr, ~mask);
tcg_gen_or_tl(t0, t0, t1);
- gen_helper_store_msr(cpu_env, t0);
+ gen_helper_store_msr(tcg_env, t0);
/* Must stop the translation as machine state (may have) changed */
ctx->base.is_jmp = DISAS_EXIT_UPDATE;
tcgv_addr = tcg_temp_new();
tcgv_op = tcg_constant_i32(ctx->opcode & 0x03FF000);
gen_addr_reg_index(ctx, tcgv_addr);
- gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op);
+ gen_helper_dcbz(tcg_env, tcgv_addr, tcgv_op);
}
/* dcbzep */
tcgv_addr = tcg_temp_new();
tcgv_op = tcg_constant_i32(ctx->opcode & 0x03FF000);
gen_addr_reg_index(ctx, tcgv_addr);
- gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op);
+ gen_helper_dcbzep(tcg_env, tcgv_addr, tcgv_op);
}
/* dst / dstt */
gen_set_access_type(ctx, ACCESS_CACHE);
t0 = tcg_temp_new();
gen_addr_reg_index(ctx, t0);
- gen_helper_icbi(cpu_env, t0);
+ gen_helper_icbi(tcg_env, t0);
}
/* icbiep */
gen_set_access_type(ctx, ACCESS_CACHE);
t0 = tcg_temp_new();
gen_addr_reg_index(ctx, t0);
- gen_helper_icbiep(cpu_env, t0);
+ gen_helper_icbiep(tcg_env, t0);
}
/* Optional: */
CHK_SV(ctx);
t0 = tcg_constant_tl(SR(ctx->opcode));
- gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
+ gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], tcg_env, t0);
#endif /* defined(CONFIG_USER_ONLY) */
}
CHK_SV(ctx);
t0 = tcg_temp_new();
tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
- gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
+ gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], tcg_env, t0);
#endif /* defined(CONFIG_USER_ONLY) */
}
CHK_SV(ctx);
t0 = tcg_constant_tl(SR(ctx->opcode));
- gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
+ gen_helper_store_sr(tcg_env, t0, cpu_gpr[rS(ctx->opcode)]);
#endif /* defined(CONFIG_USER_ONLY) */
}
t0 = tcg_temp_new();
tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
- gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
+ gen_helper_store_sr(tcg_env, t0, cpu_gpr[rD(ctx->opcode)]);
#endif /* defined(CONFIG_USER_ONLY) */
}
CHK_SV(ctx);
t0 = tcg_constant_tl(SR(ctx->opcode));
- gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
+ gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], tcg_env, t0);
#endif /* defined(CONFIG_USER_ONLY) */
}
CHK_SV(ctx);
t0 = tcg_temp_new();
tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
- gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
+ gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], tcg_env, t0);
#endif /* defined(CONFIG_USER_ONLY) */
}
CHK_SV(ctx);
t0 = tcg_constant_tl(SR(ctx->opcode));
- gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
+ gen_helper_store_sr(tcg_env, t0, cpu_gpr[rS(ctx->opcode)]);
#endif /* defined(CONFIG_USER_ONLY) */
}
CHK_SV(ctx);
t0 = tcg_temp_new();
tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
- gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
+ gen_helper_store_sr(tcg_env, t0, cpu_gpr[rS(ctx->opcode)]);
#endif /* defined(CONFIG_USER_ONLY) */
}
#else
CHK_HV(ctx);
- gen_helper_tlbia(cpu_env);
+ gen_helper_tlbia(tcg_env);
#endif /* defined(CONFIG_USER_ONLY) */
}
GEN_PRIV(ctx);
#else
CHK_SV(ctx);
- gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
+ gen_helper_6xx_tlbd(tcg_env, cpu_gpr[rB(ctx->opcode)]);
#endif /* defined(CONFIG_USER_ONLY) */
}
GEN_PRIV(ctx);
#else
CHK_SV(ctx);
- gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
+ gen_helper_6xx_tlbi(tcg_env, cpu_gpr[rB(ctx->opcode)]);
#endif /* defined(CONFIG_USER_ONLY) */
}
CHK_SV(ctx);
t0 = tcg_temp_new();
gen_addr_reg_index(ctx, t0);
- gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
+ gen_helper_tlbiva(tcg_env, cpu_gpr[rB(ctx->opcode)]);
#endif /* defined(CONFIG_USER_ONLY) */
}
CHK_SV(ctx);
dcrn = tcg_constant_tl(SPR(ctx->opcode));
- gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
+ gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], tcg_env, dcrn);
#endif /* defined(CONFIG_USER_ONLY) */
}
CHK_SV(ctx);
dcrn = tcg_constant_tl(SPR(ctx->opcode));
- gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
+ gen_helper_store_dcr(tcg_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
#endif /* defined(CONFIG_USER_ONLY) */
}
GEN_PRIV(ctx);
#else
CHK_SV(ctx);
- gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
+ gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], tcg_env,
cpu_gpr[rA(ctx->opcode)]);
/* Note: Rc update flag set leads to undefined state of Rc0 */
#endif /* defined(CONFIG_USER_ONLY) */
GEN_PRIV(ctx);
#else
CHK_SV(ctx);
- gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
+ gen_helper_store_dcr(tcg_env, cpu_gpr[rA(ctx->opcode)],
cpu_gpr[rS(ctx->opcode)]);
/* Note: Rc update flag set leads to undefined state of Rc0 */
#endif /* defined(CONFIG_USER_ONLY) */
#else
CHK_SV(ctx);
/* Restore CPU state */
- gen_helper_40x_rfci(cpu_env);
+ gen_helper_40x_rfci(tcg_env);
ctx->base.is_jmp = DISAS_EXIT;
#endif /* defined(CONFIG_USER_ONLY) */
}
#else
CHK_SV(ctx);
/* Restore CPU state */
- gen_helper_rfci(cpu_env);
+ gen_helper_rfci(tcg_env);
ctx->base.is_jmp = DISAS_EXIT;
#endif /* defined(CONFIG_USER_ONLY) */
}
#else
CHK_SV(ctx);
/* Restore CPU state */
- gen_helper_rfdi(cpu_env);
+ gen_helper_rfdi(tcg_env);
ctx->base.is_jmp = DISAS_EXIT;
#endif /* defined(CONFIG_USER_ONLY) */
}
#else
CHK_SV(ctx);
/* Restore CPU state */
- gen_helper_rfmci(cpu_env);
+ gen_helper_rfmci(tcg_env);
ctx->base.is_jmp = DISAS_EXIT;
#endif /* defined(CONFIG_USER_ONLY) */
}
CHK_SV(ctx);
switch (rB(ctx->opcode)) {
case 0:
- gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
+ gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], tcg_env,
cpu_gpr[rA(ctx->opcode)]);
break;
case 1:
- gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
+ gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], tcg_env,
cpu_gpr[rA(ctx->opcode)]);
break;
default:
CHK_SV(ctx);
t0 = tcg_temp_new();
gen_addr_reg_index(ctx, t0);
- gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
+ gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], tcg_env, t0);
if (Rc(ctx->opcode)) {
TCGLabel *l1 = gen_new_label();
tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
switch (rB(ctx->opcode)) {
case 0:
- gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
+ gen_helper_4xx_tlbwe_hi(tcg_env, cpu_gpr[rA(ctx->opcode)],
cpu_gpr[rS(ctx->opcode)]);
break;
case 1:
- gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
+ gen_helper_4xx_tlbwe_lo(tcg_env, cpu_gpr[rA(ctx->opcode)],
cpu_gpr[rS(ctx->opcode)]);
break;
default:
case 2:
{
TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode));
- gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
+ gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], tcg_env,
t0, cpu_gpr[rA(ctx->opcode)]);
}
break;
CHK_SV(ctx);
t0 = tcg_temp_new();
gen_addr_reg_index(ctx, t0);
- gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
+ gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], tcg_env, t0);
if (Rc(ctx->opcode)) {
TCGLabel *l1 = gen_new_label();
tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
case 2:
{
TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode));
- gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
+ gen_helper_440_tlbwe(tcg_env, t0, cpu_gpr[rA(ctx->opcode)],
cpu_gpr[rS(ctx->opcode)]);
}
break;
GEN_PRIV(ctx);
#else
CHK_SV(ctx);
- gen_helper_booke206_tlbre(cpu_env);
+ gen_helper_booke206_tlbre(tcg_env);
#endif /* defined(CONFIG_USER_ONLY) */
}
} else {
t0 = cpu_gpr[rB(ctx->opcode)];
}
- gen_helper_booke206_tlbsx(cpu_env, t0);
+ gen_helper_booke206_tlbsx(tcg_env, t0);
#endif /* defined(CONFIG_USER_ONLY) */
}
GEN_PRIV(ctx);
#else
CHK_SV(ctx);
- gen_helper_booke206_tlbwe(cpu_env);
+ gen_helper_booke206_tlbwe(tcg_env);
#endif /* defined(CONFIG_USER_ONLY) */
}
CHK_SV(ctx);
t0 = tcg_temp_new();
gen_addr_reg_index(ctx, t0);
- gen_helper_booke206_tlbivax(cpu_env, t0);
+ gen_helper_booke206_tlbivax(tcg_env, t0);
#endif /* defined(CONFIG_USER_ONLY) */
}
switch ((ctx->opcode >> 21) & 0x3) {
case 0:
- gen_helper_booke206_tlbilx0(cpu_env, t0);
+ gen_helper_booke206_tlbilx0(tcg_env, t0);
break;
case 1:
- gen_helper_booke206_tlbilx1(cpu_env, t0);
+ gen_helper_booke206_tlbilx1(tcg_env, t0);
break;
case 3:
- gen_helper_booke206_tlbilx3(cpu_env, t0);
+ gen_helper_booke206_tlbilx3(tcg_env, t0);
break;
default:
gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
static void gen_dlmzb(DisasContext *ctx)
{
TCGv_i32 t0 = tcg_constant_i32(Rc(ctx->opcode));
- gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
+ gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], tcg_env,
cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
}
gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
return;
}
- gen_helper_tbegin(cpu_env);
+ gen_helper_tbegin(tcg_env);
}
#define GEN_TM_NOOP(name) \
static inline void get_fpr(TCGv_i64 dst, int regno)
{
- tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno));
+ tcg_gen_ld_i64(dst, tcg_env, fpr_offset(regno));
}
static inline void set_fpr(int regno, TCGv_i64 src)
{
- tcg_gen_st_i64(src, cpu_env, fpr_offset(regno));
+ tcg_gen_st_i64(src, tcg_env, fpr_offset(regno));
/*
* Before PowerISA v3.1 the result of doubleword 1 of the VSR
* corresponding to the target FPR was undefined. However,
* Starting at ISA v3.1, the result for doubleword 1 is now defined
* to be 0.
*/
- tcg_gen_st_i64(tcg_constant_i64(0), cpu_env, vsr64_offset(regno, false));
+ tcg_gen_st_i64(tcg_constant_i64(0), tcg_env, vsr64_offset(regno, false));
}
static inline void get_avr64(TCGv_i64 dst, int regno, bool high)
{
- tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high));
+ tcg_gen_ld_i64(dst, tcg_env, avr64_offset(regno, high));
}
static inline void set_avr64(int regno, TCGv_i64 src, bool high)
{
- tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high));
+ tcg_gen_st_i64(src, tcg_env, avr64_offset(regno, high));
}
/*
translator_io_start(&ctx->base);
gen_update_cfar(ctx, ctx->cia);
- gen_helper_rfebb(cpu_env, cpu_gpr[arg->s]);
+ gen_helper_rfebb(tcg_env, cpu_gpr[arg->s]);
ctx->base.is_jmp = DISAS_CHAIN;
static inline TCGv_ptr gen_fprp_ptr(int reg)
{
TCGv_ptr r = tcg_temp_new_ptr();
- tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, vsr[reg].u64[0]));
+ tcg_gen_addi_ptr(r, tcg_env, offsetof(CPUPPCState, vsr[reg].u64[0]));
return r;
}
rt = gen_fprp_ptr(a->rt); \
ra = gen_fprp_ptr(a->ra); \
rb = gen_fprp_ptr(a->rb); \
- gen_helper_##NAME(cpu_env, rt, ra, rb); \
+ gen_helper_##NAME(tcg_env, rt, ra, rb); \
if (unlikely(a->rc)) { \
gen_set_cr1_from_fpscr(ctx); \
} \
ra = gen_fprp_ptr(a->ra); \
rb = gen_fprp_ptr(a->rb); \
gen_helper_##NAME(cpu_crf[a->bf], \
- cpu_env, ra, rb); \
+ tcg_env, ra, rb); \
return true; \
}
REQUIRE_FPU(ctx); \
rb = gen_fprp_ptr(a->rb); \
gen_helper_##NAME(cpu_crf[a->bf], \
- cpu_env, tcg_constant_i32(a->uim), rb);\
+ tcg_env, tcg_constant_i32(a->uim), rb);\
return true; \
}
REQUIRE_FPU(ctx); \
ra = gen_fprp_ptr(a->fra); \
gen_helper_##NAME(cpu_crf[a->bf], \
- cpu_env, ra, tcg_constant_i32(a->dm)); \
+ tcg_env, ra, tcg_constant_i32(a->dm)); \
return true; \
}
REQUIRE_FPU(ctx); \
rt = gen_fprp_ptr(a->frt); \
rb = gen_fprp_ptr(a->frb); \
- gen_helper_##NAME(cpu_env, rt, rb, \
+ gen_helper_##NAME(tcg_env, rt, rb, \
tcg_constant_i32(a->U32F1), \
tcg_constant_i32(a->U32F2)); \
if (unlikely(a->rc)) { \
rt = gen_fprp_ptr(a->frt); \
ra = gen_fprp_ptr(a->fra); \
rb = gen_fprp_ptr(a->frb); \
- gen_helper_##NAME(cpu_env, rt, ra, rb, \
+ gen_helper_##NAME(tcg_env, rt, ra, rb, \
tcg_constant_i32(a->I32FLD)); \
if (unlikely(a->rc)) { \
gen_set_cr1_from_fpscr(ctx); \
REQUIRE_FPU(ctx); \
rt = gen_fprp_ptr(a->rt); \
rb = gen_fprp_ptr(a->rb); \
- gen_helper_##NAME(cpu_env, rt, rb); \
+ gen_helper_##NAME(tcg_env, rt, rb); \
if (unlikely(a->rc)) { \
gen_set_cr1_from_fpscr(ctx); \
} \
REQUIRE_FPU(ctx); \
rt = gen_fprp_ptr(a->rt); \
rx = gen_fprp_ptr(a->FPRFLD); \
- gen_helper_##NAME(cpu_env, rt, rx, \
+ gen_helper_##NAME(tcg_env, rt, rx, \
tcg_constant_i32(a->I32FLD)); \
if (unlikely(a->rc)) { \
gen_set_cr1_from_fpscr(ctx); \
rt = gen_fprp_ptr(a->frtp);
rb = gen_avr_ptr(a->vrb);
- gen_helper_DCFFIXQQ(cpu_env, rt, rb);
+ gen_helper_DCFFIXQQ(tcg_env, rt, rb);
return true;
}
rt = gen_avr_ptr(a->vrt);
rb = gen_fprp_ptr(a->frbp);
- gen_helper_DCTFIXQQ(cpu_env, rt, rb);
+ gen_helper_DCTFIXQQ(tcg_env, rt, rb);
return true;
}
}
ea = do_ea_calc(ctx, a->ra, tcg_constant_tl(a->rt));
- helper(cpu_env, ea, cpu_gpr[a->ra], cpu_gpr[a->rb]);
+ helper(tcg_env, ea, cpu_gpr[a->ra], cpu_gpr[a->rb]);
return true;
}
static inline void gen_reset_fpstatus(void)
{
- gen_helper_reset_fpstatus(cpu_env);
+ gen_helper_reset_fpstatus(tcg_env);
}
static inline void gen_compute_fprf_float64(TCGv_i64 arg)
{
- gen_helper_compute_fprf_float64(cpu_env, arg);
- gen_helper_float_check_status(cpu_env);
+ gen_helper_compute_fprf_float64(tcg_env, arg);
+ gen_helper_float_check_status(tcg_env);
}
#if defined(TARGET_PPC64)
get_fpr(t0, rA(ctx->opcode)); \
get_fpr(t1, rC(ctx->opcode)); \
get_fpr(t2, rB(ctx->opcode)); \
- gen_helper_f##name(t3, cpu_env, t0, t1, t2); \
+ gen_helper_f##name(t3, tcg_env, t0, t1, t2); \
set_fpr(rD(ctx->opcode), t3); \
if (set_fprf) { \
gen_compute_fprf_float64(t3); \
gen_reset_fpstatus(); \
get_fpr(t0, rA(ctx->opcode)); \
get_fpr(t1, rB(ctx->opcode)); \
- gen_helper_f##name(t2, cpu_env, t0, t1); \
+ gen_helper_f##name(t2, tcg_env, t0, t1); \
set_fpr(rD(ctx->opcode), t2); \
if (set_fprf) { \
gen_compute_fprf_float64(t2); \
gen_reset_fpstatus(); \
get_fpr(t0, rA(ctx->opcode)); \
get_fpr(t1, rC(ctx->opcode)); \
- gen_helper_f##name(t2, cpu_env, t0, t1); \
+ gen_helper_f##name(t2, tcg_env, t0, t1); \
set_fpr(rD(ctx->opcode), t2); \
if (set_fprf) { \
gen_compute_fprf_float64(t2); \
t1 = tcg_temp_new_i64(); \
gen_reset_fpstatus(); \
get_fpr(t0, rB(ctx->opcode)); \
- gen_helper_f##name(t1, cpu_env, t0); \
+ gen_helper_f##name(t1, tcg_env, t0); \
set_fpr(rD(ctx->opcode), t1); \
if (set_fprf) { \
- gen_helper_compute_fprf_float64(cpu_env, t1); \
+ gen_helper_compute_fprf_float64(tcg_env, t1); \
} \
- gen_helper_float_check_status(cpu_env); \
+ gen_helper_float_check_status(tcg_env); \
if (unlikely(Rc(ctx->opcode) != 0)) { \
gen_set_cr1_from_fpscr(ctx); \
} \
t1 = tcg_temp_new_i64(); \
gen_reset_fpstatus(); \
get_fpr(t0, rB(ctx->opcode)); \
- gen_helper_f##name(t1, cpu_env, t0); \
+ gen_helper_f##name(t1, tcg_env, t0); \
set_fpr(rD(ctx->opcode), t1); \
if (set_fprf) { \
gen_compute_fprf_float64(t1); \
t1 = tcg_temp_new_i64();
gen_reset_fpstatus();
get_fpr(t0, rB(ctx->opcode));
- gen_helper_frsqrtes(t1, cpu_env, t0);
+ gen_helper_frsqrtes(t1, tcg_env, t0);
set_fpr(rD(ctx->opcode), t1);
gen_compute_fprf_float64(t1);
if (unlikely(Rc(ctx->opcode) != 0)) {
gen_reset_fpstatus();
get_fpr(t0, a->frb);
- helper(t1, cpu_env, t0);
+ helper(t1, tcg_env, t0);
set_fpr(a->frt, t1);
gen_compute_fprf_float64(t1);
if (unlikely(a->rc != 0)) {
crf = tcg_constant_i32(crfD(ctx->opcode));
get_fpr(t0, rA(ctx->opcode));
get_fpr(t1, rB(ctx->opcode));
- gen_helper_fcmpo(cpu_env, t0, t1, crf);
- gen_helper_float_check_status(cpu_env);
+ gen_helper_fcmpo(tcg_env, t0, t1, crf);
+ gen_helper_float_check_status(tcg_env);
}
/* fcmpu */
crf = tcg_constant_i32(crfD(ctx->opcode));
get_fpr(t0, rA(ctx->opcode));
get_fpr(t1, rB(ctx->opcode));
- gen_helper_fcmpu(cpu_env, t0, t1, crf);
- gen_helper_float_check_status(cpu_env);
+ gen_helper_fcmpu(tcg_env, t0, t1, crf);
+ gen_helper_float_check_status(tcg_env);
}
/*** Floating-point move ***/
~((0xF << shift) & FP_EX_CLEAR_BITS));
/* FEX and VX need to be updated, so don't set fpscr directly */
tmask = tcg_constant_i32(1 << nibble);
- gen_helper_store_fpscr(cpu_env, tnew_fpscr, tmask);
+ gen_helper_store_fpscr(tcg_env, tnew_fpscr, tmask);
}
static TCGv_i64 place_from_fpscr(int rt, uint64_t mask)
tcg_gen_andi_i64(fpscr_masked, fpscr, ~clear_mask);
tcg_gen_or_i64(fpscr_masked, fpscr_masked, set_mask);
- gen_helper_store_fpscr(cpu_env, fpscr_masked, st_mask);
+ gen_helper_store_fpscr(tcg_env, fpscr_masked, st_mask);
}
static bool trans_MFFS_ISA207(DisasContext *ctx, arg_X_t_rc *a)
crb = 31 - crbD(ctx->opcode);
gen_reset_fpstatus();
if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
- gen_helper_fpscr_clrbit(cpu_env, tcg_constant_i32(crb));
+ gen_helper_fpscr_clrbit(tcg_env, tcg_constant_i32(crb));
}
if (unlikely(Rc(ctx->opcode) != 0)) {
tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
crb = 31 - crbD(ctx->opcode);
/* XXX: we pretend we can only do IEEE floating-point computations */
if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
- gen_helper_fpscr_setbit(cpu_env, tcg_constant_i32(crb));
+ gen_helper_fpscr_setbit(tcg_env, tcg_constant_i32(crb));
}
if (unlikely(Rc(ctx->opcode) != 0)) {
tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
}
/* We can raise a deferred exception */
- gen_helper_fpscr_check_status(cpu_env);
+ gen_helper_fpscr_check_status(tcg_env);
}
/* mtfsf */
}
t1 = tcg_temp_new_i64();
get_fpr(t1, rB(ctx->opcode));
- gen_helper_store_fpscr(cpu_env, t1, t0);
+ gen_helper_store_fpscr(tcg_env, t1, t0);
if (unlikely(Rc(ctx->opcode) != 0)) {
tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
}
/* We can raise a deferred exception */
- gen_helper_fpscr_check_status(cpu_env);
+ gen_helper_fpscr_check_status(tcg_env);
}
/* mtfsfi */
sh = (8 * w) + 7 - bf;
t0 = tcg_constant_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
t1 = tcg_constant_i32(1 << sh);
- gen_helper_store_fpscr(cpu_env, t0, t1);
+ gen_helper_store_fpscr(tcg_env, t0, t1);
if (unlikely(Rc(ctx->opcode) != 0)) {
tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
}
/* We can raise a deferred exception */
- gen_helper_fpscr_check_status(cpu_env);
+ gen_helper_fpscr_check_status(tcg_env);
}
static void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 dest, TCGv addr)
#if !defined(CONFIG_USER_ONLY)
if (is_book3s_arch2x(ctx)) {
- gen_helper_book3s_msgclr(cpu_env, cpu_gpr[a->rb]);
+ gen_helper_book3s_msgclr(tcg_env, cpu_gpr[a->rb]);
} else {
- gen_helper_msgclr(cpu_env, cpu_gpr[a->rb]);
+ gen_helper_msgclr(tcg_env, cpu_gpr[a->rb]);
}
#else
qemu_build_not_reached();
REQUIRE_INSNS_FLAGS2(ctx, ISA207S);
REQUIRE_SV(ctx);
#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
- gen_helper_book3s_msgclrp(cpu_env, cpu_gpr[a->rb]);
+ gen_helper_book3s_msgclrp(tcg_env, cpu_gpr[a->rb]);
#else
qemu_build_not_reached();
#endif
REQUIRE_INSNS_FLAGS2(ctx, ISA207S);
REQUIRE_SV(ctx);
#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
- gen_helper_book3s_msgsndp(cpu_env, cpu_gpr[a->rb]);
+ gen_helper_book3s_msgsndp(tcg_env, cpu_gpr[a->rb]);
#else
qemu_build_not_reached();
#endif
cpu_gprh[rA(ctx->opcode)]);
/* spe_acc := tmp */
- tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
+ tcg_gen_st_i64(tmp, tcg_env, offsetof(CPUPPCState, spe_acc));
/* rD := rA */
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
/* acc := rD */
gen_load_gpr64(tmp, rD(ctx->opcode));
- tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
+ tcg_gen_st_i64(tmp, tcg_env, offsetof(CPUPPCState, spe_acc));
}
static inline void gen_evmwumiaa(DisasContext *ctx)
gen_load_gpr64(tmp, rD(ctx->opcode));
/* Load acc */
- tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
+ tcg_gen_ld_i64(acc, tcg_env, offsetof(CPUPPCState, spe_acc));
/* acc := tmp + acc */
tcg_gen_add_i64(acc, acc, tmp);
/* Store acc */
- tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
+ tcg_gen_st_i64(acc, tcg_env, offsetof(CPUPPCState, spe_acc));
/* rD := acc */
gen_store_gpr64(rD(ctx->opcode), acc);
/* acc := rD */
gen_load_gpr64(tmp, rD(ctx->opcode));
- tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
+ tcg_gen_st_i64(tmp, tcg_env, offsetof(CPUPPCState, spe_acc));
}
static inline void gen_evmwsmiaa(DisasContext *ctx)
gen_load_gpr64(tmp, rD(ctx->opcode));
/* Load acc */
- tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
+ tcg_gen_ld_i64(acc, tcg_env, offsetof(CPUPPCState, spe_acc));
/* acc := tmp + acc */
tcg_gen_add_i64(acc, acc, tmp);
/* Store acc */
- tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
+ tcg_gen_st_i64(acc, tcg_env, offsetof(CPUPPCState, spe_acc));
/* rD := acc */
gen_store_gpr64(rD(ctx->opcode), acc);
{ \
TCGv_i32 t0 = tcg_temp_new_i32(); \
tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
- gen_helper_##name(t0, cpu_env, t0); \
+ gen_helper_##name(t0, tcg_env, t0); \
tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
}
#define GEN_SPEFPUOP_CONV_32_64(name) \
t0 = tcg_temp_new_i64(); \
t1 = tcg_temp_new_i32(); \
gen_load_gpr64(t0, rB(ctx->opcode)); \
- gen_helper_##name(t1, cpu_env, t0); \
+ gen_helper_##name(t1, tcg_env, t0); \
tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); \
}
#define GEN_SPEFPUOP_CONV_64_32(name) \
t0 = tcg_temp_new_i64(); \
t1 = tcg_temp_new_i32(); \
tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
- gen_helper_##name(t0, cpu_env, t1); \
+ gen_helper_##name(t0, tcg_env, t1); \
gen_store_gpr64(rD(ctx->opcode), t0); \
}
#define GEN_SPEFPUOP_CONV_64_64(name) \
} \
t0 = tcg_temp_new_i64(); \
gen_load_gpr64(t0, rB(ctx->opcode)); \
- gen_helper_##name(t0, cpu_env, t0); \
+ gen_helper_##name(t0, tcg_env, t0); \
gen_store_gpr64(rD(ctx->opcode), t0); \
}
#define GEN_SPEFPUOP_ARITH2_32_32(name) \
TCGv_i32 t1 = tcg_temp_new_i32(); \
tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
- gen_helper_##name(t0, cpu_env, t0, t1); \
+ gen_helper_##name(t0, tcg_env, t0, t1); \
tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
}
#define GEN_SPEFPUOP_ARITH2_64_64(name) \
t1 = tcg_temp_new_i64(); \
gen_load_gpr64(t0, rA(ctx->opcode)); \
gen_load_gpr64(t1, rB(ctx->opcode)); \
- gen_helper_##name(t0, cpu_env, t0, t1); \
+ gen_helper_##name(t0, tcg_env, t0, t1); \
gen_store_gpr64(rD(ctx->opcode), t0); \
}
#define GEN_SPEFPUOP_COMP_32(name) \
\
tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
- gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
+ gen_helper_##name(cpu_crf[crfD(ctx->opcode)], tcg_env, t0, t1); \
}
#define GEN_SPEFPUOP_COMP_64(name) \
static inline void gen_##name(DisasContext *ctx) \
t1 = tcg_temp_new_i64(); \
gen_load_gpr64(t0, rA(ctx->opcode)); \
gen_load_gpr64(t1, rB(ctx->opcode)); \
- gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
+ gen_helper_##name(cpu_crf[crfD(ctx->opcode)], tcg_env, t0, t1); \
}
/* Single precision floating-point vectors operations */
REQUIRE_SV(ctx);
#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
- gen_helper_SLBIE(cpu_env, cpu_gpr[a->rb]);
+ gen_helper_SLBIE(tcg_env, cpu_gpr[a->rb]);
#else
qemu_build_not_reached();
#endif
REQUIRE_SV(ctx);
#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
- gen_helper_SLBIEG(cpu_env, cpu_gpr[a->rb]);
+ gen_helper_SLBIEG(tcg_env, cpu_gpr[a->rb]);
#else
qemu_build_not_reached();
#endif
REQUIRE_SV(ctx);
#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
- gen_helper_SLBIA(cpu_env, tcg_constant_i32(a->ih));
+ gen_helper_SLBIA(tcg_env, tcg_constant_i32(a->ih));
#else
qemu_build_not_reached();
#endif
REQUIRE_SV(ctx);
#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
- gen_helper_SLBIAG(cpu_env, cpu_gpr[a->rs], tcg_constant_i32(a->l));
+ gen_helper_SLBIAG(tcg_env, cpu_gpr[a->rs], tcg_constant_i32(a->l));
#else
qemu_build_not_reached();
#endif
REQUIRE_SV(ctx);
#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
- gen_helper_SLBMTE(cpu_env, cpu_gpr[a->rb], cpu_gpr[a->rt]);
+ gen_helper_SLBMTE(tcg_env, cpu_gpr[a->rb], cpu_gpr[a->rt]);
#else
qemu_build_not_reached();
#endif
REQUIRE_SV(ctx);
#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
- gen_helper_SLBMFEV(cpu_gpr[a->rt], cpu_env, cpu_gpr[a->rb]);
+ gen_helper_SLBMFEV(cpu_gpr[a->rt], tcg_env, cpu_gpr[a->rb]);
#else
qemu_build_not_reached();
#endif
REQUIRE_SV(ctx);
#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
- gen_helper_SLBMFEE(cpu_gpr[a->rt], cpu_env, cpu_gpr[a->rb]);
+ gen_helper_SLBMFEE(cpu_gpr[a->rt], tcg_env, cpu_gpr[a->rb]);
#else
qemu_build_not_reached();
#endif
gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
return true;
}
- gen_helper_SLBFEE(cpu_gpr[a->rt], cpu_env,
+ gen_helper_SLBFEE(cpu_gpr[a->rt], tcg_env,
cpu_gpr[a->rb]);
l1 = gen_new_label();
l2 = gen_new_label();
if (!local && NARROW_MODE(ctx)) {
TCGv t0 = tcg_temp_new();
tcg_gen_ext32u_tl(t0, cpu_gpr[rb]);
- gen_helper_tlbie(cpu_env, t0);
+ gen_helper_tlbie(tcg_env, t0);
#if defined(TARGET_PPC64)
/*
* otherwise the results are undefined.
*/
} else if (a->r) {
- gen_helper_tlbie_isa300(cpu_env, cpu_gpr[rb], cpu_gpr[a->rs],
+ gen_helper_tlbie_isa300(tcg_env, cpu_gpr[rb], cpu_gpr[a->rs],
tcg_constant_i32(a->ric << TLBIE_F_RIC_SHIFT |
a->prs << TLBIE_F_PRS_SHIFT |
a->r << TLBIE_F_R_SHIFT |
#endif
} else {
- gen_helper_tlbie(cpu_env, cpu_gpr[rb]);
+ gen_helper_tlbie(tcg_env, cpu_gpr[rb]);
}
if (local) {
}
t1 = tcg_temp_new_i32();
- tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
+ tcg_gen_ld_i32(t1, tcg_env, offsetof(CPUPPCState, tlb_need_flush));
tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH);
- tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
+ tcg_gen_st_i32(t1, tcg_env, offsetof(CPUPPCState, tlb_need_flush));
return true;
#endif
static inline TCGv_ptr gen_avr_ptr(int reg)
{
TCGv_ptr r = tcg_temp_new_ptr();
- tcg_gen_addi_ptr(r, cpu_env, avr_full_offset(reg));
+ tcg_gen_addi_ptr(r, tcg_env, avr_full_offset(reg));
return r;
}
tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
} \
rs = gen_avr_ptr(rS(ctx->opcode)); \
- gen_helper_lve##name(cpu_env, rs, EA); \
+ gen_helper_lve##name(tcg_env, rs, EA); \
}
#define GEN_VR_STVE(name, opc2, opc3, size) \
tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
} \
rs = gen_avr_ptr(rS(ctx->opcode)); \
- gen_helper_stve##name(cpu_env, rs, EA); \
+ gen_helper_stve##name(tcg_env, rs, EA); \
}
GEN_VR_LDX(lvx, 0x07, 0x03);
tcg_gen_movi_i64(avr, 0);
set_avr64(rD(ctx->opcode), avr, true);
t = tcg_temp_new_i32();
- gen_helper_mfvscr(t, cpu_env);
+ gen_helper_mfvscr(t, tcg_env);
tcg_gen_extu_i32_i64(avr, t);
set_avr64(rD(ctx->opcode), avr, false);
}
bofs += 3 * 4;
#endif
- tcg_gen_ld_i32(val, cpu_env, bofs);
- gen_helper_mtvscr(cpu_env, val);
+ tcg_gen_ld_i32(val, tcg_env, bofs);
+ gen_helper_mtvscr(tcg_env, val);
}
static void gen_vx_vmul10(DisasContext *ctx, bool add_cin, bool ret_carry)
ra = gen_avr_ptr(rA(ctx->opcode)); \
rb = gen_avr_ptr(rB(ctx->opcode)); \
rd = gen_avr_ptr(rD(ctx->opcode)); \
- gen_helper_##name(cpu_env, rd, ra, rb); \
+ gen_helper_##name(tcg_env, rd, ra, rb); \
}
#define GEN_VXFORM3(name, opc2, opc3) \
/* Perform count for every word element using tcg_gen_clzi_i32. */
for (i = 0; i < 4; i++) {
- tcg_gen_ld_i32(tmp, cpu_env,
+ tcg_gen_ld_i32(tmp, tcg_env,
offsetof(CPUPPCState, vsr[32 + VB].u64[0]) + i * 4);
tcg_gen_clzi_i32(tmp, tmp, 32);
- tcg_gen_st_i32(tmp, cpu_env,
+ tcg_gen_st_i32(tmp, tcg_env,
offsetof(CPUPPCState, vsr[32 + VT].u64[0]) + i * 4);
}
}
ra = gen_avr_ptr(rA(ctx->opcode)); \
rb = gen_avr_ptr(rB(ctx->opcode)); \
rd = gen_avr_ptr(rD(ctx->opcode)); \
- gen_helper_##opname(cpu_env, rd, ra, rb); \
+ gen_helper_##opname(tcg_env, rd, ra, rb); \
}
#define GEN_VXRFORM(name, opc2, opc3) \
} \
rb = gen_avr_ptr(rB(ctx->opcode)); \
rd = gen_avr_ptr(rD(ctx->opcode)); \
- gen_helper_##name(cpu_env, rd, rb); \
+ gen_helper_##name(tcg_env, rd, rb); \
}
#define GEN_VXFORM_NOA_2(name, opc2, opc3, opc4) \
uimm = tcg_constant_i32(UIMM5(ctx->opcode)); \
rb = gen_avr_ptr(rB(ctx->opcode)); \
rd = gen_avr_ptr(rD(ctx->opcode)); \
- gen_helper_##name(cpu_env, rd, rb, uimm); \
+ gen_helper_##name(tcg_env, rd, rb, uimm); \
}
#define GEN_VXFORM_UIMM_SPLAT(name, opc2, opc3, splat_max) \
if (right) {
tcg_gen_subfi_tl(rc, 32 - size, rc);
}
- gen_helper(cpu_env, vrt, vra, vrb, rc);
+ gen_helper(tcg_env, vrt, vra, vrb, rc);
return true;
}
tcg_gen_subfi_tl(idx, 16 - size, idx);
}
- gen_helper(cpu_env, t, rb, idx);
+ gen_helper(tcg_env, t, rb, idx);
return true;
}
rc = gen_avr_ptr(rC(ctx->opcode)); \
rd = gen_avr_ptr(rD(ctx->opcode)); \
if (Rc(ctx->opcode)) { \
- gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
+ gen_helper_##name1(tcg_env, rd, ra, rb, rc); \
} else { \
- gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
+ gen_helper_##name0(tcg_env, rd, ra, rb, rc); \
} \
}
vra = gen_avr_ptr(a->vra);
vrb = gen_avr_ptr(a->vrb);
vrc = gen_avr_ptr(a->rc);
- gen_helper(cpu_env, vrt, vra, vrb, vrc);
+ gen_helper(tcg_env, vrt, vra, vrb, vrc);
return true;
}
static inline void get_cpu_vsr(TCGv_i64 dst, int n, bool high)
{
- tcg_gen_ld_i64(dst, cpu_env, vsr64_offset(n, high));
+ tcg_gen_ld_i64(dst, tcg_env, vsr64_offset(n, high));
}
static inline void set_cpu_vsr(int n, TCGv_i64 src, bool high)
{
- tcg_gen_st_i64(src, cpu_env, vsr64_offset(n, high));
+ tcg_gen_st_i64(src, tcg_env, vsr64_offset(n, high));
}
static inline TCGv_ptr gen_vsr_ptr(int reg)
{
TCGv_ptr r = tcg_temp_new_ptr();
- tcg_gen_addi_ptr(r, cpu_env, vsr_full_offset(reg));
+ tcg_gen_addi_ptr(r, tcg_env, vsr_full_offset(reg));
return r;
}
static inline TCGv_ptr gen_acc_ptr(int reg)
{
TCGv_ptr r = tcg_temp_new_ptr();
- tcg_gen_addi_ptr(r, cpu_env, acc_full_offset(reg));
+ tcg_gen_addi_ptr(r, tcg_env, acc_full_offset(reg));
return r;
}
xt = gen_vsr_ptr(xT(ctx->opcode)); \
gen_set_access_type(ctx, ACCESS_INT); \
gen_addr_register(ctx, EA); \
- gen_helper_##name(cpu_env, EA, xt, cpu_gpr[rB(ctx->opcode)]); \
+ gen_helper_##name(tcg_env, EA, xt, cpu_gpr[rB(ctx->opcode)]); \
}
VSX_VECTOR_LOAD_STORE_LENGTH(lxvl)
xa = gen_vsr_ptr(xA(ctx->opcode)); \
xb = gen_vsr_ptr(xB(ctx->opcode)); \
if ((ctx->opcode >> (31 - 21)) & 1) { \
- gen_helper_##name(cpu_crf[6], cpu_env, xt, xa, xb); \
+ gen_helper_##name(cpu_crf[6], tcg_env, xt, xa, xb); \
} else { \
ignored = tcg_temp_new_i32(); \
- gen_helper_##name(ignored, cpu_env, xt, xa, xb); \
+ gen_helper_##name(ignored, tcg_env, xt, xa, xb); \
} \
}
xt = gen_avr_ptr(a->rt);
xb = gen_avr_ptr(a->rb);
- gen_helper_XSCVQPDP(cpu_env, ro, xt, xb);
+ gen_helper_XSCVQPDP(tcg_env, ro, xt, xb);
return true;
}
xt = gen_avr_ptr(a->rt);
xb = gen_avr_ptr(a->rb);
- gen_helper(cpu_env, xt, xb);
+ gen_helper(tcg_env, xt, xb);
return true;
}
return; \
} \
opc = tcg_constant_i32(ctx->opcode); \
- gen_helper_##name(cpu_env, opc); \
+ gen_helper_##name(tcg_env, opc); \
}
#define GEN_VSX_HELPER_X3(name, op1, op2, inval, type) \
xt = gen_vsr_ptr(xT(ctx->opcode)); \
xa = gen_vsr_ptr(xA(ctx->opcode)); \
xb = gen_vsr_ptr(xB(ctx->opcode)); \
- gen_helper_##name(cpu_env, xt, xa, xb); \
+ gen_helper_##name(tcg_env, xt, xa, xb); \
}
#define GEN_VSX_HELPER_X2(name, op1, op2, inval, type) \
} \
xt = gen_vsr_ptr(xT(ctx->opcode)); \
xb = gen_vsr_ptr(xB(ctx->opcode)); \
- gen_helper_##name(cpu_env, xt, xb); \
+ gen_helper_##name(tcg_env, xt, xb); \
}
#define GEN_VSX_HELPER_X2_AB(name, op1, op2, inval, type) \
opc = tcg_constant_i32(ctx->opcode); \
xa = gen_vsr_ptr(xA(ctx->opcode)); \
xb = gen_vsr_ptr(xB(ctx->opcode)); \
- gen_helper_##name(cpu_env, opc, xa, xb); \
+ gen_helper_##name(tcg_env, opc, xa, xb); \
}
#define GEN_VSX_HELPER_X1(name, op1, op2, inval, type) \
} \
opc = tcg_constant_i32(ctx->opcode); \
xb = gen_vsr_ptr(xB(ctx->opcode)); \
- gen_helper_##name(cpu_env, opc, xb); \
+ gen_helper_##name(tcg_env, opc, xb); \
}
#define GEN_VSX_HELPER_R3(name, op1, op2, inval, type) \
xt = gen_vsr_ptr(rD(ctx->opcode) + 32); \
xa = gen_vsr_ptr(rA(ctx->opcode) + 32); \
xb = gen_vsr_ptr(rB(ctx->opcode) + 32); \
- gen_helper_##name(cpu_env, opc, xt, xa, xb); \
+ gen_helper_##name(tcg_env, opc, xt, xa, xb); \
}
#define GEN_VSX_HELPER_R2(name, op1, op2, inval, type) \
opc = tcg_constant_i32(ctx->opcode); \
xt = gen_vsr_ptr(rD(ctx->opcode) + 32); \
xb = gen_vsr_ptr(rB(ctx->opcode) + 32); \
- gen_helper_##name(cpu_env, opc, xt, xb); \
+ gen_helper_##name(tcg_env, opc, xt, xb); \
}
#define GEN_VSX_HELPER_R2_AB(name, op1, op2, inval, type) \
opc = tcg_constant_i32(ctx->opcode); \
xa = gen_vsr_ptr(rA(ctx->opcode) + 32); \
xb = gen_vsr_ptr(rB(ctx->opcode) + 32); \
- gen_helper_##name(cpu_env, opc, xa, xb); \
+ gen_helper_##name(tcg_env, opc, xa, xb); \
}
#define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \
t0 = tcg_temp_new_i64(); \
t1 = tcg_temp_new_i64(); \
get_cpu_vsr(t0, xB(ctx->opcode), true); \
- gen_helper_##name(t1, cpu_env, t0); \
+ gen_helper_##name(t1, tcg_env, t0); \
set_cpu_vsr(xT(ctx->opcode), t1, true); \
set_cpu_vsr(xT(ctx->opcode), tcg_constant_i64(0), false); \
}
REQUIRE_VSX(ctx);
xb = vsr ? gen_vsr_ptr(a->xb) : gen_avr_ptr(a->xb);
- gen_helper(cpu_env, tcg_constant_i32(a->bf), tcg_constant_i32(a->uim), xb);
+ gen_helper(tcg_env, tcg_constant_i32(a->bf), tcg_constant_i32(a->uim), xb);
return true;
}
s2 = gen_vsr_ptr(src2);
s3 = gen_vsr_ptr(src3);
- gen_helper(cpu_env, t, s1, s2, s3);
+ gen_helper(tcg_env, t, s1, s2, s3);
return true;
}
s2 = gen_vsr_ptr(xT(ctx->opcode)); \
s3 = gen_vsr_ptr(xB(ctx->opcode)); \
} \
- gen_helper_##name(cpu_env, xt, s1, s2, s3); \
+ gen_helper_##name(tcg_env, xt, s1, s2, s3); \
}
GEN_VSX_HELPER_VSX_MADD(xvmadddp, 0x04, 0x0C, 0x0D, 0, PPC2_VSX)
imm = tcg_constant_i32(a->si);
- tcg_gen_st_i32(imm, cpu_env,
+ tcg_gen_st_i32(imm, tcg_env,
offsetof(CPUPPCState, vsr[a->xt].VsrW(0 + a->ix)));
- tcg_gen_st_i32(imm, cpu_env,
+ tcg_gen_st_i32(imm, tcg_env,
offsetof(CPUPPCState, vsr[a->xt].VsrW(2 + a->ix)));
return true;
xa = gen_vsr_ptr(a->xa);
xb = gen_vsr_ptr(a->xb);
- helper(cpu_env, xt, xa, xb);
+ helper(tcg_env, xt, xa, xb);
return true;
}
ra = gen_avr_ptr(a->ra);
rb = gen_avr_ptr(a->rb);
- helper(cpu_env, rt, ra, rb);
+ helper(tcg_env, rt, ra, rb);
return true;
}
xt = gen_vsr_ptr(a->xt);
xb = gen_vsr_ptr(a->xb);
- gen_helper_XVCVSPBF16(cpu_env, xt, xb);
+ gen_helper_XVCVSPBF16(tcg_env, xt, xb);
return true;
}
xb = gen_vsr_ptr(a->xb);
mask = ger_pack_masks(a->pmsk, a->ymsk, a->xmsk);
- helper(cpu_env, xa, xb, xt, tcg_constant_i32(mask));
+ helper(tcg_env, xa, xb, xt, tcg_constant_i32(mask));
return true;
}
if (has_ext(ctx, RVS)) {
decode_save_opc(ctx);
translator_io_start(&ctx->base);
- gen_helper_sret(cpu_pc, cpu_env);
+ gen_helper_sret(cpu_pc, tcg_env);
exit_tb(ctx); /* no chaining */
ctx->base.is_jmp = DISAS_NORETURN;
} else {
#ifndef CONFIG_USER_ONLY
decode_save_opc(ctx);
translator_io_start(&ctx->base);
- gen_helper_mret(cpu_pc, cpu_env);
+ gen_helper_mret(cpu_pc, tcg_env);
exit_tb(ctx); /* no chaining */
ctx->base.is_jmp = DISAS_NORETURN;
return true;
#ifndef CONFIG_USER_ONLY
decode_save_opc(ctx);
gen_update_pc(ctx, ctx->cur_insn_len);
- gen_helper_wfi(cpu_env);
+ gen_helper_wfi(tcg_env);
return true;
#else
return false;
{
#ifndef CONFIG_USER_ONLY
decode_save_opc(ctx);
- gen_helper_tlb_flush(cpu_env);
+ gen_helper_tlb_flush(tcg_env);
return true;
#endif
return false;
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_bf16_s(dest, cpu_env, src1);
+ gen_helper_fcvt_bf16_s(dest, tcg_env, src1);
gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_s_bf16(dest, cpu_env, src1);
+ gen_helper_fcvt_s_bf16(dest, tcg_env, src1);
gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
data = FIELD_DP32(data, VDATA, VTA, ctx->vta);
data = FIELD_DP32(data, VDATA, VMA, ctx->vma);
tcg_gen_gvec_3_ptr(vreg_ofs(ctx, a->rd), vreg_ofs(ctx, 0),
- vreg_ofs(ctx, a->rs2), cpu_env,
+ vreg_ofs(ctx, a->rs2), tcg_env,
ctx->cfg_ptr->vlen / 8,
ctx->cfg_ptr->vlen / 8, data,
gen_helper_vfncvtbf16_f_f_w);
data = FIELD_DP32(data, VDATA, VTA, ctx->vta);
data = FIELD_DP32(data, VDATA, VMA, ctx->vma);
tcg_gen_gvec_3_ptr(vreg_ofs(ctx, a->rd), vreg_ofs(ctx, 0),
- vreg_ofs(ctx, a->rs2), cpu_env,
+ vreg_ofs(ctx, a->rs2), tcg_env,
ctx->cfg_ptr->vlen / 8,
ctx->cfg_ptr->vlen / 8, data,
gen_helper_vfwcvtbf16_f_f_v);
data = FIELD_DP32(data, VDATA, VMA, ctx->vma);
tcg_gen_gvec_4_ptr(vreg_ofs(ctx, a->rd), vreg_ofs(ctx, 0),
vreg_ofs(ctx, a->rs1),
- vreg_ofs(ctx, a->rs2), cpu_env,
+ vreg_ofs(ctx, a->rs2), tcg_env,
ctx->cfg_ptr->vlen / 8,
ctx->cfg_ptr->vlen / 8, data,
gen_helper_vfwmaccbf16_vv);
TCGv_i64 src3 = get_fpr_d(ctx, a->rs3);
gen_set_rm(ctx, a->rm);
- gen_helper_fmadd_d(dest, cpu_env, src1, src2, src3);
+ gen_helper_fmadd_d(dest, tcg_env, src1, src2, src3);
gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
TCGv_i64 src3 = get_fpr_d(ctx, a->rs3);
gen_set_rm(ctx, a->rm);
- gen_helper_fmsub_d(dest, cpu_env, src1, src2, src3);
+ gen_helper_fmsub_d(dest, tcg_env, src1, src2, src3);
gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
TCGv_i64 src3 = get_fpr_d(ctx, a->rs3);
gen_set_rm(ctx, a->rm);
- gen_helper_fnmsub_d(dest, cpu_env, src1, src2, src3);
+ gen_helper_fnmsub_d(dest, tcg_env, src1, src2, src3);
gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
TCGv_i64 src3 = get_fpr_d(ctx, a->rs3);
gen_set_rm(ctx, a->rm);
- gen_helper_fnmadd_d(dest, cpu_env, src1, src2, src3);
+ gen_helper_fnmadd_d(dest, tcg_env, src1, src2, src3);
gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
gen_set_rm(ctx, a->rm);
- gen_helper_fadd_d(dest, cpu_env, src1, src2);
+ gen_helper_fadd_d(dest, tcg_env, src1, src2);
gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
gen_set_rm(ctx, a->rm);
- gen_helper_fsub_d(dest, cpu_env, src1, src2);
+ gen_helper_fsub_d(dest, tcg_env, src1, src2);
gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
gen_set_rm(ctx, a->rm);
- gen_helper_fmul_d(dest, cpu_env, src1, src2);
+ gen_helper_fmul_d(dest, tcg_env, src1, src2);
gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
gen_set_rm(ctx, a->rm);
- gen_helper_fdiv_d(dest, cpu_env, src1, src2);
+ gen_helper_fdiv_d(dest, tcg_env, src1, src2);
gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
gen_set_rm(ctx, a->rm);
- gen_helper_fsqrt_d(dest, cpu_env, src1);
+ gen_helper_fsqrt_d(dest, tcg_env, src1);
gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
- gen_helper_fmin_d(dest, cpu_env, src1, src2);
+ gen_helper_fmin_d(dest, tcg_env, src1, src2);
gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
- gen_helper_fmax_d(dest, cpu_env, src1, src2);
+ gen_helper_fmax_d(dest, tcg_env, src1, src2);
gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_s_d(dest, cpu_env, src1);
+ gen_helper_fcvt_s_d(dest, tcg_env, src1);
gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_d_s(dest, cpu_env, src1);
+ gen_helper_fcvt_d_s(dest, tcg_env, src1);
gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
- gen_helper_feq_d(dest, cpu_env, src1, src2);
+ gen_helper_feq_d(dest, tcg_env, src1, src2);
gen_set_gpr(ctx, a->rd, dest);
return true;
}
TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
- gen_helper_flt_d(dest, cpu_env, src1, src2);
+ gen_helper_flt_d(dest, tcg_env, src1, src2);
gen_set_gpr(ctx, a->rd, dest);
return true;
}
TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
- gen_helper_fle_d(dest, cpu_env, src1, src2);
+ gen_helper_fle_d(dest, tcg_env, src1, src2);
gen_set_gpr(ctx, a->rd, dest);
return true;
}
TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_w_d(dest, cpu_env, src1);
+ gen_helper_fcvt_w_d(dest, tcg_env, src1);
gen_set_gpr(ctx, a->rd, dest);
return true;
}
TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_wu_d(dest, cpu_env, src1);
+ gen_helper_fcvt_wu_d(dest, tcg_env, src1);
gen_set_gpr(ctx, a->rd, dest);
return true;
}
TCGv src = get_gpr(ctx, a->rs1, EXT_SIGN);
gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_d_w(dest, cpu_env, src);
+ gen_helper_fcvt_d_w(dest, tcg_env, src);
gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx);
TCGv src = get_gpr(ctx, a->rs1, EXT_ZERO);
gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_d_wu(dest, cpu_env, src);
+ gen_helper_fcvt_d_wu(dest, tcg_env, src);
gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx);
TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_l_d(dest, cpu_env, src1);
+ gen_helper_fcvt_l_d(dest, tcg_env, src1);
gen_set_gpr(ctx, a->rd, dest);
return true;
}
TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_lu_d(dest, cpu_env, src1);
+ gen_helper_fcvt_lu_d(dest, tcg_env, src1);
gen_set_gpr(ctx, a->rd, dest);
return true;
}
TCGv src = get_gpr(ctx, a->rs1, EXT_SIGN);
gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_d_l(dest, cpu_env, src);
+ gen_helper_fcvt_d_l(dest, tcg_env, src);
gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx);
TCGv src = get_gpr(ctx, a->rs1, EXT_ZERO);
gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_d_lu(dest, cpu_env, src);
+ gen_helper_fcvt_d_lu(dest, tcg_env, src);
gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx);
TCGv_i64 src3 = get_fpr_hs(ctx, a->rs3);
gen_set_rm(ctx, a->rm);
- gen_helper_fmadd_s(dest, cpu_env, src1, src2, src3);
+ gen_helper_fmadd_s(dest, tcg_env, src1, src2, src3);
gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
TCGv_i64 src3 = get_fpr_hs(ctx, a->rs3);
gen_set_rm(ctx, a->rm);
- gen_helper_fmsub_s(dest, cpu_env, src1, src2, src3);
+ gen_helper_fmsub_s(dest, tcg_env, src1, src2, src3);
gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
TCGv_i64 src3 = get_fpr_hs(ctx, a->rs3);
gen_set_rm(ctx, a->rm);
- gen_helper_fnmsub_s(dest, cpu_env, src1, src2, src3);
+ gen_helper_fnmsub_s(dest, tcg_env, src1, src2, src3);
gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
TCGv_i64 src3 = get_fpr_hs(ctx, a->rs3);
gen_set_rm(ctx, a->rm);
- gen_helper_fnmadd_s(dest, cpu_env, src1, src2, src3);
+ gen_helper_fnmadd_s(dest, tcg_env, src1, src2, src3);
gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
gen_set_rm(ctx, a->rm);
- gen_helper_fadd_s(dest, cpu_env, src1, src2);
+ gen_helper_fadd_s(dest, tcg_env, src1, src2);
gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
gen_set_rm(ctx, a->rm);
- gen_helper_fsub_s(dest, cpu_env, src1, src2);
+ gen_helper_fsub_s(dest, tcg_env, src1, src2);
gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
gen_set_rm(ctx, a->rm);
- gen_helper_fmul_s(dest, cpu_env, src1, src2);
+ gen_helper_fmul_s(dest, tcg_env, src1, src2);
gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
gen_set_rm(ctx, a->rm);
- gen_helper_fdiv_s(dest, cpu_env, src1, src2);
+ gen_helper_fdiv_s(dest, tcg_env, src1, src2);
gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
gen_set_rm(ctx, a->rm);
- gen_helper_fsqrt_s(dest, cpu_env, src1);
+ gen_helper_fsqrt_s(dest, tcg_env, src1);
gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
- gen_helper_fmin_s(dest, cpu_env, src1, src2);
+ gen_helper_fmin_s(dest, tcg_env, src1, src2);
gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
- gen_helper_fmax_s(dest, cpu_env, src1, src2);
+ gen_helper_fmax_s(dest, tcg_env, src1, src2);
gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_w_s(dest, cpu_env, src1);
+ gen_helper_fcvt_w_s(dest, tcg_env, src1);
gen_set_gpr(ctx, a->rd, dest);
return true;
}
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_wu_s(dest, cpu_env, src1);
+ gen_helper_fcvt_wu_s(dest, tcg_env, src1);
gen_set_gpr(ctx, a->rd, dest);
return true;
}
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
- gen_helper_feq_s(dest, cpu_env, src1, src2);
+ gen_helper_feq_s(dest, tcg_env, src1, src2);
gen_set_gpr(ctx, a->rd, dest);
return true;
}
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
- gen_helper_flt_s(dest, cpu_env, src1, src2);
+ gen_helper_flt_s(dest, tcg_env, src1, src2);
gen_set_gpr(ctx, a->rd, dest);
return true;
}
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
- gen_helper_fle_s(dest, cpu_env, src1, src2);
+ gen_helper_fle_s(dest, tcg_env, src1, src2);
gen_set_gpr(ctx, a->rd, dest);
return true;
}
TCGv dest = dest_gpr(ctx, a->rd);
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
- gen_helper_fclass_s(dest, cpu_env, src1);
+ gen_helper_fclass_s(dest, tcg_env, src1);
gen_set_gpr(ctx, a->rd, dest);
return true;
}
TCGv src = get_gpr(ctx, a->rs1, EXT_SIGN);
gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_s_w(dest, cpu_env, src);
+ gen_helper_fcvt_s_w(dest, tcg_env, src);
gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
TCGv src = get_gpr(ctx, a->rs1, EXT_ZERO);
gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_s_wu(dest, cpu_env, src);
+ gen_helper_fcvt_s_wu(dest, tcg_env, src);
gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_l_s(dest, cpu_env, src1);
+ gen_helper_fcvt_l_s(dest, tcg_env, src1);
gen_set_gpr(ctx, a->rd, dest);
return true;
}
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_lu_s(dest, cpu_env, src1);
+ gen_helper_fcvt_lu_s(dest, tcg_env, src1);
gen_set_gpr(ctx, a->rd, dest);
return true;
}
TCGv src = get_gpr(ctx, a->rs1, EXT_SIGN);
gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_s_l(dest, cpu_env, src);
+ gen_helper_fcvt_s_l(dest, tcg_env, src);
gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
TCGv src = get_gpr(ctx, a->rs1, EXT_ZERO);
gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_s_lu(dest, cpu_env, src);
+ gen_helper_fcvt_s_lu(dest, tcg_env, src);
gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
decode_save_opc(ctx);
- func(dest, cpu_env, addr);
+ func(dest, tcg_env, addr);
gen_set_gpr(ctx, a->rd, dest);
return true;
}
TCGv data = get_gpr(ctx, a->rs2, EXT_NONE);
decode_save_opc(ctx);
- func(cpu_env, addr, data);
+ func(tcg_env, addr, data);
return true;
}
#endif /* CONFIG_USER_ONLY */
REQUIRE_EXT(ctx, RVH);
#ifndef CONFIG_USER_ONLY
decode_save_opc(ctx);
- gen_helper_hyp_gvma_tlb_flush(cpu_env);
+ gen_helper_hyp_gvma_tlb_flush(tcg_env);
return true;
#endif
return false;
REQUIRE_EXT(ctx, RVH);
#ifndef CONFIG_USER_ONLY
decode_save_opc(ctx);
- gen_helper_hyp_tlb_flush(cpu_env);
+ gen_helper_hyp_tlb_flush(tcg_env);
return true;
#endif
return false;
TCGv_i32 csr = tcg_constant_i32(rc);
translator_io_start(&ctx->base);
- gen_helper_csrr(dest, cpu_env, csr);
+ gen_helper_csrr(dest, tcg_env, csr);
gen_set_gpr(ctx, rd, dest);
return do_csr_post(ctx);
}
TCGv_i32 csr = tcg_constant_i32(rc);
translator_io_start(&ctx->base);
- gen_helper_csrw(cpu_env, csr, src);
+ gen_helper_csrw(tcg_env, csr, src);
return do_csr_post(ctx);
}
TCGv_i32 csr = tcg_constant_i32(rc);
translator_io_start(&ctx->base);
- gen_helper_csrrw(dest, cpu_env, csr, src, mask);
+ gen_helper_csrrw(dest, tcg_env, csr, src, mask);
gen_set_gpr(ctx, rd, dest);
return do_csr_post(ctx);
}
TCGv_i32 csr = tcg_constant_i32(rc);
translator_io_start(&ctx->base);
- gen_helper_csrr_i128(destl, cpu_env, csr);
- tcg_gen_ld_tl(desth, cpu_env, offsetof(CPURISCVState, retxh));
+ gen_helper_csrr_i128(destl, tcg_env, csr);
+ tcg_gen_ld_tl(desth, tcg_env, offsetof(CPURISCVState, retxh));
gen_set_gpr128(ctx, rd, destl, desth);
return do_csr_post(ctx);
}
TCGv_i32 csr = tcg_constant_i32(rc);
translator_io_start(&ctx->base);
- gen_helper_csrw_i128(cpu_env, csr, srcl, srch);
+ gen_helper_csrw_i128(tcg_env, csr, srcl, srch);
return do_csr_post(ctx);
}
TCGv_i32 csr = tcg_constant_i32(rc);
translator_io_start(&ctx->base);
- gen_helper_csrrw_i128(destl, cpu_env, csr, srcl, srch, maskl, maskh);
- tcg_gen_ld_tl(desth, cpu_env, offsetof(CPURISCVState, retxh));
+ gen_helper_csrrw_i128(destl, tcg_env, csr, srcl, srch, maskl, maskh);
+ tcg_gen_ld_tl(desth, tcg_env, offsetof(CPURISCVState, retxh));
gen_set_gpr128(ctx, rd, destl, desth);
return do_csr_post(ctx);
}
static void gen_div_i128(TCGv rdl, TCGv rdh,
TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
{
- gen_helper_divs_i128(rdl, cpu_env, rs1l, rs1h, rs2l, rs2h);
- tcg_gen_ld_tl(rdh, cpu_env, offsetof(CPURISCVState, retxh));
+ gen_helper_divs_i128(rdl, tcg_env, rs1l, rs1h, rs2l, rs2h);
+ tcg_gen_ld_tl(rdh, tcg_env, offsetof(CPURISCVState, retxh));
}
static void gen_div(TCGv ret, TCGv source1, TCGv source2)
static void gen_divu_i128(TCGv rdl, TCGv rdh,
TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
{
- gen_helper_divu_i128(rdl, cpu_env, rs1l, rs1h, rs2l, rs2h);
- tcg_gen_ld_tl(rdh, cpu_env, offsetof(CPURISCVState, retxh));
+ gen_helper_divu_i128(rdl, tcg_env, rs1l, rs1h, rs2l, rs2h);
+ tcg_gen_ld_tl(rdh, tcg_env, offsetof(CPURISCVState, retxh));
}
static void gen_divu(TCGv ret, TCGv source1, TCGv source2)
static void gen_rem_i128(TCGv rdl, TCGv rdh,
TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
{
- gen_helper_rems_i128(rdl, cpu_env, rs1l, rs1h, rs2l, rs2h);
- tcg_gen_ld_tl(rdh, cpu_env, offsetof(CPURISCVState, retxh));
+ gen_helper_rems_i128(rdl, tcg_env, rs1l, rs1h, rs2l, rs2h);
+ tcg_gen_ld_tl(rdh, tcg_env, offsetof(CPURISCVState, retxh));
}
static void gen_rem(TCGv ret, TCGv source1, TCGv source2)
static void gen_remu_i128(TCGv rdl, TCGv rdh,
TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
{
- gen_helper_remu_i128(rdl, cpu_env, rs1l, rs1h, rs2l, rs2h);
- tcg_gen_ld_tl(rdh, cpu_env, offsetof(CPURISCVState, retxh));
+ gen_helper_remu_i128(rdl, tcg_env, rs1l, rs1h, rs2l, rs2h);
+ tcg_gen_ld_tl(rdh, tcg_env, offsetof(CPURISCVState, retxh));
}
static void gen_remu(TCGv ret, TCGv source1, TCGv source2)
s1 = get_gpr(s, rs1, EXT_ZERO);
}
- gen_helper_vsetvl(dst, cpu_env, s1, s2);
+ gen_helper_vsetvl(dst, tcg_env, s1, s2);
gen_set_gpr(s, rd, dst);
mark_vs_dirty(s);
dst = dest_gpr(s, rd);
- gen_helper_vsetvl(dst, cpu_env, s1, s2);
+ gen_helper_vsetvl(dst, tcg_env, s1, s2);
gen_set_gpr(s, rd, dst);
mark_vs_dirty(s);
gen_update_pc(s, s->cur_insn_len);
desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
s->cfg_ptr->vlen / 8, data));
- tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
- tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
+ tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
+ tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));
- fn(dest, mask, base, cpu_env, desc);
+ fn(dest, mask, base, tcg_env, desc);
if (!is_store) {
mark_vs_dirty(s);
desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
s->cfg_ptr->vlen / 8, data));
- tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
- tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
+ tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
+ tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));
- fn(dest, mask, base, stride, cpu_env, desc);
+ fn(dest, mask, base, stride, tcg_env, desc);
if (!is_store) {
mark_vs_dirty(s);
desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
s->cfg_ptr->vlen / 8, data));
- tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
- tcg_gen_addi_ptr(index, cpu_env, vreg_ofs(s, vs2));
- tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
+ tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
+ tcg_gen_addi_ptr(index, tcg_env, vreg_ofs(s, vs2));
+ tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));
- fn(dest, mask, base, index, cpu_env, desc);
+ fn(dest, mask, base, index, tcg_env, desc);
if (!is_store) {
mark_vs_dirty(s);
desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
s->cfg_ptr->vlen / 8, data));
- tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
- tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
+ tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
+ tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));
- fn(dest, mask, base, cpu_env, desc);
+ fn(dest, mask, base, tcg_env, desc);
mark_vs_dirty(s);
gen_set_label(over);
s->cfg_ptr->vlen / 8, data));
base = get_gpr(s, rs1, EXT_NONE);
- tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
+ tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
- fn(dest, base, cpu_env, desc);
+ fn(dest, base, tcg_env, desc);
if (!is_store) {
mark_vs_dirty(s);
data = FIELD_DP32(data, VDATA, VMA, s->vma);
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
- cpu_env, s->cfg_ptr->vlen / 8,
+ tcg_env, s->cfg_ptr->vlen / 8,
s->cfg_ptr->vlen / 8, data, fn);
}
mark_vs_dirty(s);
desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
s->cfg_ptr->vlen / 8, data));
- tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
- tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2));
- tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
+ tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
+ tcg_gen_addi_ptr(src2, tcg_env, vreg_ofs(s, vs2));
+ tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));
- fn(dest, mask, src1, src2, cpu_env, desc);
+ fn(dest, mask, src1, src2, tcg_env, desc);
mark_vs_dirty(s);
gen_set_label(over);
desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
s->cfg_ptr->vlen / 8, data));
- tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
- tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2));
- tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
+ tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
+ tcg_gen_addi_ptr(src2, tcg_env, vreg_ofs(s, vs2));
+ tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));
- fn(dest, mask, src1, src2, cpu_env, desc);
+ fn(dest, mask, src1, src2, tcg_env, desc);
mark_vs_dirty(s);
gen_set_label(over);
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
vreg_ofs(s, a->rs1),
vreg_ofs(s, a->rs2),
- cpu_env, s->cfg_ptr->vlen / 8,
+ tcg_env, s->cfg_ptr->vlen / 8,
s->cfg_ptr->vlen / 8,
data, fn);
mark_vs_dirty(s);
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
vreg_ofs(s, a->rs1),
vreg_ofs(s, a->rs2),
- cpu_env, s->cfg_ptr->vlen / 8,
+ tcg_env, s->cfg_ptr->vlen / 8,
s->cfg_ptr->vlen / 8, data, fn);
mark_vs_dirty(s);
gen_set_label(over);
data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);
data = FIELD_DP32(data, VDATA, VMA, s->vma);
tcg_gen_gvec_4_ptr(vreg_ofs(s, vd), vreg_ofs(s, 0), vreg_ofs(s, vs1),
- vreg_ofs(s, vs2), cpu_env, s->cfg_ptr->vlen / 8,
+ vreg_ofs(s, vs2), tcg_env, s->cfg_ptr->vlen / 8,
s->cfg_ptr->vlen / 8, data, fn);
mark_vs_dirty(s);
gen_set_label(over);
data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1), \
- vreg_ofs(s, a->rs2), cpu_env, \
+ vreg_ofs(s, a->rs2), tcg_env, \
s->cfg_ptr->vlen / 8, \
s->cfg_ptr->vlen / 8, data, \
fns[s->sew]); \
tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
- cpu_env, s->cfg_ptr->vlen / 8,
+ tcg_env, s->cfg_ptr->vlen / 8,
s->cfg_ptr->vlen / 8, data,
fns[s->sew]);
gen_set_label(over);
tcg_gen_ext_tl_i64(s1_i64, s1);
desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
s->cfg_ptr->vlen / 8, data));
- tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
- fns[s->sew](dest, s1_i64, cpu_env, desc);
+ tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, a->rd));
+ fns[s->sew](dest, s1_i64, tcg_env, desc);
}
mark_vs_dirty(s);
dest = tcg_temp_new_ptr();
desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
s->cfg_ptr->vlen / 8, data));
- tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
- fns[s->sew](dest, s1, cpu_env, desc);
+ tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, a->rd));
+ fns[s->sew](dest, s1, tcg_env, desc);
mark_vs_dirty(s);
gen_set_label(over);
data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1), \
- vreg_ofs(s, a->rs2), cpu_env, \
+ vreg_ofs(s, a->rs2), tcg_env, \
s->cfg_ptr->vlen / 8, \
s->cfg_ptr->vlen / 8, data, \
fns[s->sew - 1]); \
desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
s->cfg_ptr->vlen / 8, data));
- tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
- tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2));
- tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
+ tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
+ tcg_gen_addi_ptr(src2, tcg_env, vreg_ofs(s, vs2));
+ tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));
/* NaN-box f[rs1] */
t1 = tcg_temp_new_i64();
do_nanbox(s, t1, cpu_fpr[rs1]);
- fn(dest, mask, t1, src2, cpu_env, desc);
+ fn(dest, mask, t1, src2, tcg_env, desc);
mark_vs_dirty(s);
gen_set_label(over);
data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1), \
- vreg_ofs(s, a->rs2), cpu_env, \
+ vreg_ofs(s, a->rs2), tcg_env, \
s->cfg_ptr->vlen / 8, \
s->cfg_ptr->vlen / 8, data, \
fns[s->sew - 1]); \
data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1), \
- vreg_ofs(s, a->rs2), cpu_env, \
+ vreg_ofs(s, a->rs2), tcg_env, \
s->cfg_ptr->vlen / 8, \
s->cfg_ptr->vlen / 8, data, \
fns[s->sew - 1]); \
data = FIELD_DP32(data, VDATA, VTA, s->vta);
data = FIELD_DP32(data, VDATA, VMA, s->vma);
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
- vreg_ofs(s, a->rs2), cpu_env,
+ vreg_ofs(s, a->rs2), tcg_env,
s->cfg_ptr->vlen / 8,
s->cfg_ptr->vlen / 8, data, fn);
mark_vs_dirty(s);
dest = tcg_temp_new_ptr();
desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
s->cfg_ptr->vlen / 8, data));
- tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
+ tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, a->rd));
- fns[s->sew - 1](dest, t1, cpu_env, desc);
+ fns[s->sew - 1](dest, t1, tcg_env, desc);
mark_vs_dirty(s);
gen_set_label(over);
data = FIELD_DP32(data, VDATA, VTA, s->vta); \
data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
- vreg_ofs(s, a->rs2), cpu_env, \
+ vreg_ofs(s, a->rs2), tcg_env, \
s->cfg_ptr->vlen / 8, \
s->cfg_ptr->vlen / 8, data, \
fns[s->sew - 1]); \
data = FIELD_DP32(data, VDATA, VTA, s->vta); \
data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
- vreg_ofs(s, a->rs2), cpu_env, \
+ vreg_ofs(s, a->rs2), tcg_env, \
s->cfg_ptr->vlen / 8, \
s->cfg_ptr->vlen / 8, data, \
fns[s->sew]); \
data = FIELD_DP32(data, VDATA, VTA, s->vta); \
data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
- vreg_ofs(s, a->rs2), cpu_env, \
+ vreg_ofs(s, a->rs2), tcg_env, \
s->cfg_ptr->vlen / 8, \
s->cfg_ptr->vlen / 8, data, \
fns[s->sew - 1]); \
data = FIELD_DP32(data, VDATA, VTA, s->vta); \
data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
- vreg_ofs(s, a->rs2), cpu_env, \
+ vreg_ofs(s, a->rs2), tcg_env, \
s->cfg_ptr->vlen / 8, \
s->cfg_ptr->vlen / 8, data, \
fns[s->sew]); \
FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);\
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1), \
- vreg_ofs(s, a->rs2), cpu_env, \
+ vreg_ofs(s, a->rs2), tcg_env, \
s->cfg_ptr->vlen / 8, \
s->cfg_ptr->vlen / 8, data, fn); \
mark_vs_dirty(s); \
desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
s->cfg_ptr->vlen / 8, data));
- tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2));
- tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
+ tcg_gen_addi_ptr(src2, tcg_env, vreg_ofs(s, a->rs2));
+ tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));
- gen_helper_vcpop_m(dst, mask, src2, cpu_env, desc);
+ gen_helper_vcpop_m(dst, mask, src2, tcg_env, desc);
gen_set_gpr(s, a->rd, dst);
return true;
}
desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
s->cfg_ptr->vlen / 8, data));
- tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2));
- tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
+ tcg_gen_addi_ptr(src2, tcg_env, vreg_ofs(s, a->rs2));
+ tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));
- gen_helper_vfirst_m(dst, mask, src2, cpu_env, desc);
+ gen_helper_vfirst_m(dst, mask, src2, tcg_env, desc);
gen_set_gpr(s, a->rd, dst);
return true;
}
data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), \
vreg_ofs(s, 0), vreg_ofs(s, a->rs2), \
- cpu_env, s->cfg_ptr->vlen / 8, \
+ tcg_env, s->cfg_ptr->vlen / 8, \
s->cfg_ptr->vlen / 8, \
data, fn); \
mark_vs_dirty(s); \
gen_helper_viota_m_w, gen_helper_viota_m_d,
};
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
- vreg_ofs(s, a->rs2), cpu_env,
+ vreg_ofs(s, a->rs2), tcg_env,
s->cfg_ptr->vlen / 8,
s->cfg_ptr->vlen / 8, data, fns[s->sew]);
mark_vs_dirty(s);
gen_helper_vid_v_w, gen_helper_vid_v_d,
};
tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
- cpu_env, s->cfg_ptr->vlen / 8,
+ tcg_env, s->cfg_ptr->vlen / 8,
s->cfg_ptr->vlen / 8,
data, fns[s->sew]);
mark_vs_dirty(s);
/* Convert the index to a pointer. */
tcg_gen_ext_i32_ptr(base, ofs);
- tcg_gen_add_ptr(base, base, cpu_env);
+ tcg_gen_add_ptr(base, base, tcg_env);
/* Perform the load. */
load_element(dest, base,
static void vec_element_loadi(DisasContext *s, TCGv_i64 dest,
int vreg, int idx, bool sign)
{
- load_element(dest, cpu_env, endian_ofs(s, vreg, idx), s->sew, sign);
+ load_element(dest, tcg_env, endian_ofs(s, vreg, idx), s->sew, sign);
}
/* Integer Scalar Move Instruction */
static void vec_element_storei(DisasContext *s, int vreg,
int idx, TCGv_i64 val)
{
- store_element(val, cpu_env, endian_ofs(s, vreg, idx), s->sew);
+ store_element(val, tcg_env, endian_ofs(s, vreg, idx), s->sew);
}
/* vmv.x.s rd, vs2 # x[rd] = vs2[0] */
data = FIELD_DP32(data, VDATA, VTA, s->vta);
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
- cpu_env, s->cfg_ptr->vlen / 8,
+ tcg_env, s->cfg_ptr->vlen / 8,
s->cfg_ptr->vlen / 8, data,
fns[s->sew]);
mark_vs_dirty(s);
TCGLabel *over = gen_new_label(); \
tcg_gen_brcondi_tl(TCG_COND_GEU, cpu_vstart, maxsz, over); \
tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), \
- cpu_env, maxsz, maxsz, 0, gen_helper_vmvr_v); \
+ tcg_env, maxsz, maxsz, 0, gen_helper_vmvr_v); \
mark_vs_dirty(s); \
gen_set_label(over); \
} \
data = FIELD_DP32(data, VDATA, VMA, s->vma);
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
- vreg_ofs(s, a->rs2), cpu_env,
+ vreg_ofs(s, a->rs2), tcg_env,
s->cfg_ptr->vlen / 8,
s->cfg_ptr->vlen / 8, data, fn);
data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s); \
data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
- vreg_ofs(s, a->rs2), cpu_env, \
+ vreg_ofs(s, a->rs2), tcg_env, \
s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, \
data, fns[s->sew]); \
mark_vs_dirty(s); \
/* save opcode for unwinding in case we throw an exception */ \
decode_save_opc(s); \
egs = tcg_constant_i32(EGS); \
- gen_helper_egs_check(egs, cpu_env); \
+ gen_helper_egs_check(egs, tcg_env); \
tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
} \
\
rs2_v = tcg_temp_new_ptr(); \
desc = tcg_constant_i32( \
simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data)); \
- tcg_gen_addi_ptr(rd_v, cpu_env, vreg_ofs(s, a->rd)); \
- tcg_gen_addi_ptr(rs2_v, cpu_env, vreg_ofs(s, a->rs2)); \
- gen_helper_##NAME(rd_v, rs2_v, cpu_env, desc); \
+ tcg_gen_addi_ptr(rd_v, tcg_env, vreg_ofs(s, a->rd)); \
+ tcg_gen_addi_ptr(rs2_v, tcg_env, vreg_ofs(s, a->rs2)); \
+ gen_helper_##NAME(rd_v, rs2_v, tcg_env, desc); \
mark_vs_dirty(s); \
gen_set_label(over); \
return true; \
/* save opcode for unwinding in case we throw an exception */ \
decode_save_opc(s); \
egs = tcg_constant_i32(EGS); \
- gen_helper_egs_check(egs, cpu_env); \
+ gen_helper_egs_check(egs, tcg_env); \
tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
} \
\
uimm_v = tcg_constant_i32(a->rs1); \
desc = tcg_constant_i32( \
simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data)); \
- tcg_gen_addi_ptr(rd_v, cpu_env, vreg_ofs(s, a->rd)); \
- tcg_gen_addi_ptr(rs2_v, cpu_env, vreg_ofs(s, a->rs2)); \
- gen_helper_##NAME(rd_v, rs2_v, uimm_v, cpu_env, desc); \
+ tcg_gen_addi_ptr(rd_v, tcg_env, vreg_ofs(s, a->rd)); \
+ tcg_gen_addi_ptr(rs2_v, tcg_env, vreg_ofs(s, a->rs2)); \
+ gen_helper_##NAME(rd_v, rs2_v, uimm_v, tcg_env, desc); \
mark_vs_dirty(s); \
gen_set_label(over); \
return true; \
/* save opcode for unwinding in case we throw an exception */ \
decode_save_opc(s); \
egs = tcg_constant_i32(EGS); \
- gen_helper_egs_check(egs, cpu_env); \
+ gen_helper_egs_check(egs, tcg_env); \
tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
} \
\
data = FIELD_DP32(data, VDATA, VMA, s->vma); \
\
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1), \
- vreg_ofs(s, a->rs2), cpu_env, \
+ vreg_ofs(s, a->rs2), tcg_env, \
s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, \
data, gen_helper_##NAME); \
\
/* save opcode for unwinding in case we throw an exception */
decode_save_opc(s);
egs = tcg_constant_i32(ZVKNH_EGS);
- gen_helper_egs_check(egs, cpu_env);
+ gen_helper_egs_check(egs, tcg_env);
tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
}
data = FIELD_DP32(data, VDATA, VMA, s->vma);
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
- vreg_ofs(s, a->rs2), cpu_env, s->cfg_ptr->vlen / 8,
+ vreg_ofs(s, a->rs2), tcg_env, s->cfg_ptr->vlen / 8,
s->cfg_ptr->vlen / 8, data,
s->sew == MO_32 ?
gen_helper_vsha2cl32_vv : gen_helper_vsha2cl64_vv);
/* save opcode for unwinding in case we throw an exception */
decode_save_opc(s);
egs = tcg_constant_i32(ZVKNH_EGS);
- gen_helper_egs_check(egs, cpu_env);
+ gen_helper_egs_check(egs, tcg_env);
tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
}
data = FIELD_DP32(data, VDATA, VMA, s->vma);
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
- vreg_ofs(s, a->rs2), cpu_env, s->cfg_ptr->vlen / 8,
+ vreg_ofs(s, a->rs2), tcg_env, s->cfg_ptr->vlen / 8,
s->cfg_ptr->vlen / 8, data,
s->sew == MO_32 ?
gen_helper_vsha2ch32_vv : gen_helper_vsha2ch64_vv);
* that might come from cpu_ld*_code() in the helper.
*/
gen_update_pc(ctx, 0);
- gen_helper_cm_jalt(cpu_pc, cpu_env, tcg_constant_i32(a->index));
+ gen_helper_cm_jalt(cpu_pc, tcg_env, tcg_constant_i32(a->index));
/* c.jt vs c.jalt depends on the index. */
if (a->index >= 32) {
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
- gen_helper_fminm_s(dest, cpu_env, src1, src2);
+ gen_helper_fminm_s(dest, tcg_env, src1, src2);
gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx);
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
- gen_helper_fmaxm_s(dest, cpu_env, src1, src2);
+ gen_helper_fmaxm_s(dest, tcg_env, src1, src2);
gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx);
TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
- gen_helper_fminm_d(dest, cpu_env, src1, src2);
+ gen_helper_fminm_d(dest, tcg_env, src1, src2);
gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx);
TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
- gen_helper_fmaxm_d(dest, cpu_env, src1, src2);
+ gen_helper_fmaxm_d(dest, tcg_env, src1, src2);
gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx);
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
- gen_helper_fminm_h(dest, cpu_env, src1, src2);
+ gen_helper_fminm_h(dest, tcg_env, src1, src2);
gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx);
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
- gen_helper_fmaxm_h(dest, cpu_env, src1, src2);
+ gen_helper_fmaxm_h(dest, tcg_env, src1, src2);
gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx);
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
gen_set_rm(ctx, a->rm);
- gen_helper_fround_s(dest, cpu_env, src1);
+ gen_helper_fround_s(dest, tcg_env, src1);
gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx);
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
gen_set_rm(ctx, a->rm);
- gen_helper_froundnx_s(dest, cpu_env, src1);
+ gen_helper_froundnx_s(dest, tcg_env, src1);
gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx);
TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
gen_set_rm(ctx, a->rm);
- gen_helper_fround_d(dest, cpu_env, src1);
+ gen_helper_fround_d(dest, tcg_env, src1);
gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx);
TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
gen_set_rm(ctx, a->rm);
- gen_helper_froundnx_d(dest, cpu_env, src1);
+ gen_helper_froundnx_d(dest, tcg_env, src1);
gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx);
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
gen_set_rm(ctx, a->rm);
- gen_helper_fround_h(dest, cpu_env, src1);
+ gen_helper_fround_h(dest, tcg_env, src1);
gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx);
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
gen_set_rm(ctx, a->rm);
- gen_helper_froundnx_h(dest, cpu_env, src1);
+ gen_helper_froundnx_h(dest, tcg_env, src1);
gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx);
/* Rounding mode is RTZ. */
gen_set_rm(ctx, RISCV_FRM_RTZ);
- gen_helper_fcvtmod_w_d(t1, cpu_env, src1);
+ gen_helper_fcvtmod_w_d(t1, tcg_env, src1);
tcg_gen_trunc_i64_tl(dst, t1);
gen_set_gpr(ctx, a->rd, dst);
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
- gen_helper_fleq_s(dest, cpu_env, src1, src2);
+ gen_helper_fleq_s(dest, tcg_env, src1, src2);
gen_set_gpr(ctx, a->rd, dest);
return true;
}
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
- gen_helper_fltq_s(dest, cpu_env, src1, src2);
+ gen_helper_fltq_s(dest, tcg_env, src1, src2);
gen_set_gpr(ctx, a->rd, dest);
return true;
}
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
- gen_helper_fleq_d(dest, cpu_env, src1, src2);
+ gen_helper_fleq_d(dest, tcg_env, src1, src2);
gen_set_gpr(ctx, a->rd, dest);
return true;
}
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
- gen_helper_fltq_d(dest, cpu_env, src1, src2);
+ gen_helper_fltq_d(dest, tcg_env, src1, src2);
gen_set_gpr(ctx, a->rd, dest);
return true;
}
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
- gen_helper_fleq_h(dest, cpu_env, src1, src2);
+ gen_helper_fleq_h(dest, tcg_env, src1, src2);
gen_set_gpr(ctx, a->rd, dest);
return true;
}
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
- gen_helper_fltq_h(dest, cpu_env, src1, src2);
+ gen_helper_fltq_h(dest, tcg_env, src1, src2);
gen_set_gpr(ctx, a->rd, dest);
return true;
}
TCGv_i64 src3 = get_fpr_hs(ctx, a->rs3);
gen_set_rm(ctx, a->rm);
- gen_helper_fmadd_h(dest, cpu_env, src1, src2, src3);
+ gen_helper_fmadd_h(dest, tcg_env, src1, src2, src3);
gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
TCGv_i64 src3 = get_fpr_hs(ctx, a->rs3);
gen_set_rm(ctx, a->rm);
- gen_helper_fmsub_h(dest, cpu_env, src1, src2, src3);
+ gen_helper_fmsub_h(dest, tcg_env, src1, src2, src3);
gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
TCGv_i64 src3 = get_fpr_hs(ctx, a->rs3);
gen_set_rm(ctx, a->rm);
- gen_helper_fnmsub_h(dest, cpu_env, src1, src2, src3);
+ gen_helper_fnmsub_h(dest, tcg_env, src1, src2, src3);
gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
TCGv_i64 src3 = get_fpr_hs(ctx, a->rs3);
gen_set_rm(ctx, a->rm);
- gen_helper_fnmadd_h(dest, cpu_env, src1, src2, src3);
+ gen_helper_fnmadd_h(dest, tcg_env, src1, src2, src3);
gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
gen_set_rm(ctx, a->rm);
- gen_helper_fadd_h(dest, cpu_env, src1, src2);
+ gen_helper_fadd_h(dest, tcg_env, src1, src2);
gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
gen_set_rm(ctx, a->rm);
- gen_helper_fsub_h(dest, cpu_env, src1, src2);
+ gen_helper_fsub_h(dest, tcg_env, src1, src2);
gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
gen_set_rm(ctx, a->rm);
- gen_helper_fmul_h(dest, cpu_env, src1, src2);
+ gen_helper_fmul_h(dest, tcg_env, src1, src2);
gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
gen_set_rm(ctx, a->rm);
- gen_helper_fdiv_h(dest, cpu_env, src1, src2);
+ gen_helper_fdiv_h(dest, tcg_env, src1, src2);
gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
gen_set_rm(ctx, a->rm);
- gen_helper_fsqrt_h(dest, cpu_env, src1);
+ gen_helper_fsqrt_h(dest, tcg_env, src1);
gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
- gen_helper_fmin_h(dest, cpu_env, src1, src2);
+ gen_helper_fmin_h(dest, tcg_env, src1, src2);
gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
- gen_helper_fmax_h(dest, cpu_env, src1, src2);
+ gen_helper_fmax_h(dest, tcg_env, src1, src2);
gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_s_h(dest, cpu_env, src1);
+ gen_helper_fcvt_s_h(dest, tcg_env, src1);
gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx);
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_d_h(dest, cpu_env, src1);
+ gen_helper_fcvt_d_h(dest, tcg_env, src1);
gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx);
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_h_s(dest, cpu_env, src1);
+ gen_helper_fcvt_h_s(dest, tcg_env, src1);
gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx);
TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_h_d(dest, cpu_env, src1);
+ gen_helper_fcvt_h_d(dest, tcg_env, src1);
gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx);
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
- gen_helper_feq_h(dest, cpu_env, src1, src2);
+ gen_helper_feq_h(dest, tcg_env, src1, src2);
gen_set_gpr(ctx, a->rd, dest);
return true;
}
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
- gen_helper_flt_h(dest, cpu_env, src1, src2);
+ gen_helper_flt_h(dest, tcg_env, src1, src2);
gen_set_gpr(ctx, a->rd, dest);
return true;
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
- gen_helper_fle_h(dest, cpu_env, src1, src2);
+ gen_helper_fle_h(dest, tcg_env, src1, src2);
gen_set_gpr(ctx, a->rd, dest);
return true;
}
TCGv dest = dest_gpr(ctx, a->rd);
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
- gen_helper_fclass_h(dest, cpu_env, src1);
+ gen_helper_fclass_h(dest, tcg_env, src1);
gen_set_gpr(ctx, a->rd, dest);
return true;
}
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_w_h(dest, cpu_env, src1);
+ gen_helper_fcvt_w_h(dest, tcg_env, src1);
gen_set_gpr(ctx, a->rd, dest);
return true;
}
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_wu_h(dest, cpu_env, src1);
+ gen_helper_fcvt_wu_h(dest, tcg_env, src1);
gen_set_gpr(ctx, a->rd, dest);
return true;
}
TCGv t0 = get_gpr(ctx, a->rs1, EXT_SIGN);
gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_h_w(dest, cpu_env, t0);
+ gen_helper_fcvt_h_w(dest, tcg_env, t0);
gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx);
TCGv t0 = get_gpr(ctx, a->rs1, EXT_SIGN);
gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_h_wu(dest, cpu_env, t0);
+ gen_helper_fcvt_h_wu(dest, tcg_env, t0);
gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx);
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_l_h(dest, cpu_env, src1);
+ gen_helper_fcvt_l_h(dest, tcg_env, src1);
gen_set_gpr(ctx, a->rd, dest);
return true;
}
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_lu_h(dest, cpu_env, src1);
+ gen_helper_fcvt_lu_h(dest, tcg_env, src1);
gen_set_gpr(ctx, a->rd, dest);
return true;
}
TCGv t0 = get_gpr(ctx, a->rs1, EXT_SIGN);
gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_h_l(dest, cpu_env, t0);
+ gen_helper_fcvt_h_l(dest, tcg_env, t0);
gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx);
TCGv t0 = get_gpr(ctx, a->rs1, EXT_SIGN);
gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_h_lu(dest, cpu_env, t0);
+ gen_helper_fcvt_h_lu(dest, tcg_env, t0);
gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx);
static bool trans_cbo_clean(DisasContext *ctx, arg_cbo_clean *a)
{
REQUIRE_ZICBOM(ctx);
- gen_helper_cbo_clean_flush(cpu_env, cpu_gpr[a->rs1]);
+ gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
return true;
}
static bool trans_cbo_flush(DisasContext *ctx, arg_cbo_flush *a)
{
REQUIRE_ZICBOM(ctx);
- gen_helper_cbo_clean_flush(cpu_env, cpu_gpr[a->rs1]);
+ gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
return true;
}
static bool trans_cbo_inval(DisasContext *ctx, arg_cbo_inval *a)
{
REQUIRE_ZICBOM(ctx);
- gen_helper_cbo_inval(cpu_env, cpu_gpr[a->rs1]);
+ gen_helper_cbo_inval(tcg_env, cpu_gpr[a->rs1]);
return true;
}
static bool trans_cbo_zero(DisasContext *ctx, arg_cbo_zero *a)
{
REQUIRE_ZICBOZ(ctx);
- gen_helper_cbo_zero(cpu_env, cpu_gpr[a->rs1]);
+ gen_helper_cbo_zero(tcg_env, cpu_gpr[a->rs1]);
return true;
}
REQUIRE_EXT(ctx, RVS);
#ifndef CONFIG_USER_ONLY
decode_save_opc(ctx);
- gen_helper_tlb_flush(cpu_env);
+ gen_helper_tlb_flush(tcg_env);
return true;
#endif
return false;
REQUIRE_EXT(ctx, RVH);
#ifndef CONFIG_USER_ONLY
decode_save_opc(ctx);
- gen_helper_hyp_tlb_flush(cpu_env);
+ gen_helper_hyp_tlb_flush(tcg_env);
return true;
#endif
return false;
REQUIRE_EXT(ctx, RVH);
#ifndef CONFIG_USER_ONLY
decode_save_opc(ctx);
- gen_helper_hyp_gvma_tlb_flush(cpu_env);
+ gen_helper_hyp_gvma_tlb_flush(tcg_env);
return true;
#endif
return false;
#ifndef CONFIG_USER_ONLY
REQUIRE_PRIV_MS(ctx);
- gen_helper_tlb_flush_all(cpu_env);
+ gen_helper_tlb_flush_all(tcg_env);
return true;
#else
return false;
static void generate_exception(DisasContext *ctx, int excp)
{
gen_update_pc(ctx, 0);
- gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
+ gen_helper_raise_exception(tcg_env, tcg_constant_i32(excp));
ctx->base.is_jmp = DISAS_NORETURN;
}
static void gen_exception_illegal(DisasContext *ctx)
{
- tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env,
+ tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), tcg_env,
offsetof(CPURISCVState, bins));
if (ctx->virt_inst_excp) {
generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT);
static void gen_exception_inst_addr_mis(DisasContext *ctx, TCGv target)
{
- tcg_gen_st_tl(target, cpu_env, offsetof(CPURISCVState, badaddr));
+ tcg_gen_st_tl(target, tcg_env, offsetof(CPURISCVState, badaddr));
generate_exception(ctx, RISCV_EXCP_INST_ADDR_MIS);
}
{
#ifndef CONFIG_USER_ONLY
if (ctx->itrigger) {
- gen_helper_itrigger_match(cpu_env);
+ gen_helper_itrigger_match(tcg_env);
}
#endif
tcg_gen_lookup_and_goto_ptr();
{
#ifndef CONFIG_USER_ONLY
if (ctx->itrigger) {
- gen_helper_itrigger_match(cpu_env);
+ gen_helper_itrigger_match(tcg_env);
}
#endif
tcg_gen_exit_tb(NULL, 0);
ctx->mstatus_fs = EXT_STATUS_DIRTY;
tmp = tcg_temp_new();
- tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
+ tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus));
tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS);
- tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
+ tcg_gen_st_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus));
if (ctx->virt_enabled) {
- tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
+ tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus_hs));
tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS);
- tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
+ tcg_gen_st_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus_hs));
}
}
}
ctx->mstatus_vs = EXT_STATUS_DIRTY;
tmp = tcg_temp_new();
- tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
+ tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus));
tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS);
- tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
+ tcg_gen_st_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus));
if (ctx->virt_enabled) {
- tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
+ tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus_hs));
tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS);
- tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
+ tcg_gen_st_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus_hs));
}
}
}
/* The helper may raise ILLEGAL_INSN -- record binv for unwind. */
decode_save_opc(ctx);
- gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm));
+ gen_helper_set_rounding_mode(tcg_env, tcg_constant_i32(rm));
}
static void gen_set_rm_chkfrm(DisasContext *ctx, int rm)
/* The helper may raise ILLEGAL_INSN -- record binv for unwind. */
decode_save_opc(ctx);
- gen_helper_set_rounding_mode_chkfrm(cpu_env, tcg_constant_i32(rm));
+ gen_helper_set_rounding_mode_chkfrm(tcg_env, tcg_constant_i32(rm));
}
static int ex_plus_1(DisasContext *ctx, int nf)
cpu_gprh[0] = NULL;
for (i = 1; i < 32; i++) {
- cpu_gpr[i] = tcg_global_mem_new(cpu_env,
+ cpu_gpr[i] = tcg_global_mem_new(tcg_env,
offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]);
- cpu_gprh[i] = tcg_global_mem_new(cpu_env,
+ cpu_gprh[i] = tcg_global_mem_new(tcg_env,
offsetof(CPURISCVState, gprh[i]), riscv_int_regnamesh[i]);
}
for (i = 0; i < 32; i++) {
- cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
+ cpu_fpr[i] = tcg_global_mem_new_i64(tcg_env,
offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]);
}
- cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc");
- cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl");
- cpu_vstart = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vstart),
+ cpu_pc = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, pc), "pc");
+ cpu_vl = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, vl), "vl");
+ cpu_vstart = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, vstart),
"vstart");
- load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res),
+ load_res = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_res),
"load_res");
- load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val),
+ load_val = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_val),
"load_val");
/* Assign PM CSRs to tcg globals */
- pm_mask = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmmask),
+ pm_mask = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, cur_pmmask),
"pmmask");
- pm_base = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmbase),
+ pm_base = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, cur_pmbase),
"pmbase");
}
{
if (FIELD_EX32(ctx->tb_flags, PSW, PM)) {
if (is_exception) {
- gen_helper_raise_privilege_violation(cpu_env);
+ gen_helper_raise_privilege_violation(tcg_env);
}
return 0;
} else {
{
switch (cr) {
case 0: /* PSW */
- gen_helper_pack_psw(ret, cpu_env);
+ gen_helper_pack_psw(ret, tcg_env);
break;
case 1: /* PC */
tcg_gen_movi_i32(ret, pc);
}
switch (cr) {
case 0: /* PSW */
- gen_helper_set_psw(cpu_env, val);
+ gen_helper_set_psw(tcg_env, val);
if (is_privileged(ctx, 0)) {
/* PSW.{I,U} may be updated here. exit TB. */
ctx->base.is_jmp = DISAS_UPDATE;
}
break;
case 3: /* FPSW */
- gen_helper_set_fpsw(cpu_env, val);
+ gen_helper_set_fpsw(tcg_env, val);
break;
case 8: /* BPSW */
tcg_gen_mov_i32(cpu_bpsw, val);
static void rx_div(TCGv ret, TCGv arg1, TCGv arg2)
{
- gen_helper_div(ret, cpu_env, arg1, arg2);
+ gen_helper_div(ret, tcg_env, arg1, arg2);
}
static void rx_divu(TCGv ret, TCGv arg1, TCGv arg2)
{
- gen_helper_divu(ret, cpu_env, arg1, arg2);
+ gen_helper_divu(ret, tcg_env, arg1, arg2);
}
/* div #imm, rd */
/* scmpu */
static bool trans_SCMPU(DisasContext *ctx, arg_SCMPU *a)
{
- gen_helper_scmpu(cpu_env);
+ gen_helper_scmpu(tcg_env);
return true;
}
/* smovu */
static bool trans_SMOVU(DisasContext *ctx, arg_SMOVU *a)
{
- gen_helper_smovu(cpu_env);
+ gen_helper_smovu(tcg_env);
return true;
}
/* smovf */
static bool trans_SMOVF(DisasContext *ctx, arg_SMOVF *a)
{
- gen_helper_smovf(cpu_env);
+ gen_helper_smovf(tcg_env);
return true;
}
/* smovb */
static bool trans_SMOVB(DisasContext *ctx, arg_SMOVB *a)
{
- gen_helper_smovb(cpu_env);
+ gen_helper_smovb(tcg_env);
return true;
}
#define STRING(op) \
do { \
TCGv size = tcg_constant_i32(a->sz); \
- gen_helper_##op(cpu_env, size); \
+ gen_helper_##op(tcg_env, size); \
} while (0)
/* suntile.<bwl> */
static bool trans_RACW(DisasContext *ctx, arg_RACW *a)
{
TCGv imm = tcg_constant_i32(a->imm + 1);
- gen_helper_racw(cpu_env, imm);
+ gen_helper_racw(tcg_env, imm);
return true;
}
/* satr */
static bool trans_SATR(DisasContext *ctx, arg_SATR *a)
{
- gen_helper_satr(cpu_env);
+ gen_helper_satr(tcg_env);
return true;
}
cat3(arg_, name, _ir) * a) \
{ \
TCGv imm = tcg_constant_i32(li(ctx, 0)); \
- gen_helper_##op(cpu_regs[a->rd], cpu_env, \
+ gen_helper_##op(cpu_regs[a->rd], tcg_env, \
cpu_regs[a->rd], imm); \
return true; \
} \
TCGv val, mem; \
mem = tcg_temp_new(); \
val = rx_load_source(ctx, mem, a->ld, MO_32, a->rs); \
- gen_helper_##op(cpu_regs[a->rd], cpu_env, \
+ gen_helper_##op(cpu_regs[a->rd], tcg_env, \
cpu_regs[a->rd], val); \
return true; \
}
TCGv val, mem; \
mem = tcg_temp_new(); \
val = rx_load_source(ctx, mem, a->ld, MO_32, a->rs); \
- gen_helper_##op(cpu_regs[a->rd], cpu_env, val); \
+ gen_helper_##op(cpu_regs[a->rd], tcg_env, val); \
return true; \
}
static bool trans_FCMP_ir(DisasContext *ctx, arg_FCMP_ir * a)
{
TCGv imm = tcg_constant_i32(li(ctx, 0));
- gen_helper_fcmp(cpu_env, cpu_regs[a->rd], imm);
+ gen_helper_fcmp(tcg_env, cpu_regs[a->rd], imm);
return true;
}
TCGv val, mem;
mem = tcg_temp_new();
val = rx_load_source(ctx, mem, a->ld, MO_32, a->rs);
- gen_helper_fcmp(cpu_env, cpu_regs[a->rd], val);
+ gen_helper_fcmp(tcg_env, cpu_regs[a->rd], val);
return true;
}
TCGv val, mem;
mem = tcg_temp_new();
val = rx_load_source(ctx, mem, a->ld, a->mi, a->rs);
- gen_helper_itof(cpu_regs[a->rd], cpu_env, val);
+ gen_helper_itof(cpu_regs[a->rd], tcg_env, val);
return true;
}
psw = tcg_temp_new();
tcg_gen_mov_i32(cpu_pc, cpu_bpc);
tcg_gen_mov_i32(psw, cpu_bpsw);
- gen_helper_set_psw_rte(cpu_env, psw);
+ gen_helper_set_psw_rte(tcg_env, psw);
ctx->base.is_jmp = DISAS_EXIT;
}
return true;
psw = tcg_temp_new();
pop(cpu_pc);
pop(psw);
- gen_helper_set_psw_rte(cpu_env, psw);
+ gen_helper_set_psw_rte(tcg_env, psw);
ctx->base.is_jmp = DISAS_EXIT;
}
return true;
static bool trans_BRK(DisasContext *ctx, arg_BRK *a)
{
tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next);
- gen_helper_rxbrk(cpu_env);
+ gen_helper_rxbrk(tcg_env);
ctx->base.is_jmp = DISAS_NORETURN;
return true;
}
tcg_debug_assert(a->imm < 0x100);
vec = tcg_constant_i32(a->imm);
tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next);
- gen_helper_rxint(cpu_env, vec);
+ gen_helper_rxint(tcg_env, vec);
ctx->base.is_jmp = DISAS_NORETURN;
return true;
}
{
if (is_privileged(ctx, 1)) {
tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next);
- gen_helper_wait(cpu_env);
+ gen_helper_wait(tcg_env);
}
return true;
}
ctx->pc = ctx->base.pc_next;
insn = decode_load(ctx);
if (!decode(ctx, insn)) {
- gen_helper_raise_illegal_instruction(cpu_env);
+ gen_helper_raise_illegal_instruction(tcg_env);
}
}
}
#define ALLOC_REGISTER(sym, name) \
- cpu_##sym = tcg_global_mem_new_i32(cpu_env, \
+ cpu_##sym = tcg_global_mem_new_i32(tcg_env, \
offsetof(CPURXState, sym), name)
void rx_translate_init(void)
int i;
for (i = 0; i < NUM_REGS; i++) {
- cpu_regs[i] = tcg_global_mem_new_i32(cpu_env,
+ cpu_regs[i] = tcg_global_mem_new_i32(tcg_env,
offsetof(CPURXState, regs[i]),
regnames[i]);
}
ALLOC_REGISTER(isp, "ISP");
ALLOC_REGISTER(fintv, "FINTV");
ALLOC_REGISTER(intb, "INTB");
- cpu_acc = tcg_global_mem_new_i64(cpu_env,
+ cpu_acc = tcg_global_mem_new_i64(tcg_env,
offsetof(CPURXState, acc), "ACC");
}
{
int i;
- psw_addr = tcg_global_mem_new_i64(cpu_env,
+ psw_addr = tcg_global_mem_new_i64(tcg_env,
offsetof(CPUS390XState, psw.addr),
"psw_addr");
- psw_mask = tcg_global_mem_new_i64(cpu_env,
+ psw_mask = tcg_global_mem_new_i64(tcg_env,
offsetof(CPUS390XState, psw.mask),
"psw_mask");
- gbea = tcg_global_mem_new_i64(cpu_env,
+ gbea = tcg_global_mem_new_i64(tcg_env,
offsetof(CPUS390XState, gbea),
"gbea");
- cc_op = tcg_global_mem_new_i32(cpu_env, offsetof(CPUS390XState, cc_op),
+ cc_op = tcg_global_mem_new_i32(tcg_env, offsetof(CPUS390XState, cc_op),
"cc_op");
- cc_src = tcg_global_mem_new_i64(cpu_env, offsetof(CPUS390XState, cc_src),
+ cc_src = tcg_global_mem_new_i64(tcg_env, offsetof(CPUS390XState, cc_src),
"cc_src");
- cc_dst = tcg_global_mem_new_i64(cpu_env, offsetof(CPUS390XState, cc_dst),
+ cc_dst = tcg_global_mem_new_i64(tcg_env, offsetof(CPUS390XState, cc_dst),
"cc_dst");
- cc_vr = tcg_global_mem_new_i64(cpu_env, offsetof(CPUS390XState, cc_vr),
+ cc_vr = tcg_global_mem_new_i64(tcg_env, offsetof(CPUS390XState, cc_vr),
"cc_vr");
for (i = 0; i < 16; i++) {
snprintf(cpu_reg_names[i], sizeof(cpu_reg_names[0]), "r%d", i);
- regs[i] = tcg_global_mem_new(cpu_env,
+ regs[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUS390XState, regs[i]),
cpu_reg_names[i]);
}
{
TCGv_i64 r = tcg_temp_new_i64();
- tcg_gen_ld_i64(r, cpu_env, freg64_offset(reg));
+ tcg_gen_ld_i64(r, tcg_env, freg64_offset(reg));
return r;
}
{
TCGv_i64 r = tcg_temp_new_i64();
- tcg_gen_ld32u_i64(r, cpu_env, freg32_offset(reg));
+ tcg_gen_ld32u_i64(r, tcg_env, freg32_offset(reg));
return r;
}
static void store_freg(int reg, TCGv_i64 v)
{
- tcg_gen_st_i64(v, cpu_env, freg64_offset(reg));
+ tcg_gen_st_i64(v, tcg_env, freg64_offset(reg));
}
static void store_reg32_i64(int reg, TCGv_i64 v)
static void store_freg32_i64(int reg, TCGv_i64 v)
{
- tcg_gen_st32_i64(v, cpu_env, freg32_offset(reg));
+ tcg_gen_st32_i64(v, tcg_env, freg32_offset(reg));
}
static void update_psw_addr(DisasContext *s)
if (s->base.tb->flags & FLAG_MASK_PER) {
TCGv_i64 next_pc = to_next ? tcg_constant_i64(s->pc_tmp) : psw_addr;
- gen_helper_per_branch(cpu_env, gbea, next_pc);
+ gen_helper_per_branch(tcg_env, gbea, next_pc);
}
#endif
}
tcg_gen_brcond_i64(tcg_invert_cond(cond), arg1, arg2, lab);
tcg_gen_movi_i64(gbea, s->base.pc_next);
- gen_helper_per_branch(cpu_env, gbea, psw_addr);
+ gen_helper_per_branch(tcg_env, gbea, psw_addr);
gen_set_label(lab);
} else {
static void gen_exception(int excp)
{
- gen_helper_exception(cpu_env, tcg_constant_i32(excp));
+ gen_helper_exception(tcg_env, tcg_constant_i32(excp));
}
static void gen_program_exception(DisasContext *s, int code)
{
/* Remember what pgm exception this was. */
- tcg_gen_st_i32(tcg_constant_i32(code), cpu_env,
+ tcg_gen_st_i32(tcg_constant_i32(code), tcg_env,
offsetof(CPUS390XState, int_pgm_code));
- tcg_gen_st_i32(tcg_constant_i32(s->ilen), cpu_env,
+ tcg_gen_st_i32(tcg_constant_i32(s->ilen), tcg_env,
offsetof(CPUS390XState, int_pgm_ilen));
/* update the psw */
static inline void gen_data_exception(uint8_t dxc)
{
- gen_helper_data_exception(cpu_env, tcg_constant_i32(dxc));
+ gen_helper_data_exception(tcg_env, tcg_constant_i32(dxc));
}
static inline void gen_trap(DisasContext *s)
case CC_OP_LCBB:
case CC_OP_MULS_32:
/* 1 argument */
- gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, dummy, cc_dst, dummy);
+ gen_helper_calc_cc(cc_op, tcg_env, local_cc_op, dummy, cc_dst, dummy);
break;
case CC_OP_ADDU:
case CC_OP_ICM:
case CC_OP_VC:
case CC_OP_MULS_64:
/* 2 arguments */
- gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, cc_src, cc_dst, dummy);
+ gen_helper_calc_cc(cc_op, tcg_env, local_cc_op, cc_src, cc_dst, dummy);
break;
case CC_OP_ADD_64:
case CC_OP_SUB_64:
case CC_OP_ADD_32:
case CC_OP_SUB_32:
/* 3 arguments */
- gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, cc_src, cc_dst, cc_vr);
+ gen_helper_calc_cc(cc_op, tcg_env, local_cc_op, cc_src, cc_dst, cc_vr);
break;
case CC_OP_DYNAMIC:
/* unknown operation - assume 3 arguments and cc_op in env */
- gen_helper_calc_cc(cc_op, cpu_env, cc_op, cc_src, cc_dst, cc_vr);
+ gen_helper_calc_cc(cc_op, tcg_env, cc_op, cc_src, cc_dst, cc_vr);
break;
default:
g_assert_not_reached();
static DisasJumpType op_aeb(DisasContext *s, DisasOps *o)
{
- gen_helper_aeb(o->out, cpu_env, o->in1, o->in2);
+ gen_helper_aeb(o->out, tcg_env, o->in1, o->in2);
return DISAS_NEXT;
}
static DisasJumpType op_adb(DisasContext *s, DisasOps *o)
{
- gen_helper_adb(o->out, cpu_env, o->in1, o->in2);
+ gen_helper_adb(o->out, tcg_env, o->in1, o->in2);
return DISAS_NEXT;
}
static DisasJumpType op_axb(DisasContext *s, DisasOps *o)
{
- gen_helper_axb(o->out_128, cpu_env, o->in1_128, o->in2_128);
+ gen_helper_axb(o->out_128, tcg_env, o->in1_128, o->in2_128);
return DISAS_NEXT;
}
if (have_field(s, ri)) { \
if (unlikely(s->ex_value)) { \
cdest = tcg_temp_new_i64(); \
- tcg_gen_ld_i64(cdest, cpu_env, offsetof(CPUS390XState, ex_target));\
+ tcg_gen_ld_i64(cdest, tcg_env, offsetof(CPUS390XState, ex_target));\
tcg_gen_addi_i64(cdest, cdest, (int64_t)get_field(s, ri) * 2); \
is_imm = false; \
} else { \
static DisasJumpType op_ceb(DisasContext *s, DisasOps *o)
{
- gen_helper_ceb(cc_op, cpu_env, o->in1, o->in2);
+ gen_helper_ceb(cc_op, tcg_env, o->in1, o->in2);
set_cc_static(s);
return DISAS_NEXT;
}
static DisasJumpType op_cdb(DisasContext *s, DisasOps *o)
{
- gen_helper_cdb(cc_op, cpu_env, o->in1, o->in2);
+ gen_helper_cdb(cc_op, tcg_env, o->in1, o->in2);
set_cc_static(s);
return DISAS_NEXT;
}
static DisasJumpType op_cxb(DisasContext *s, DisasOps *o)
{
- gen_helper_cxb(cc_op, cpu_env, o->in1_128, o->in2_128);
+ gen_helper_cxb(cc_op, tcg_env, o->in1_128, o->in2_128);
set_cc_static(s);
return DISAS_NEXT;
}
if (!m34) {
return DISAS_NORETURN;
}
- gen_helper_cfeb(o->out, cpu_env, o->in2, m34);
+ gen_helper_cfeb(o->out, tcg_env, o->in2, m34);
set_cc_static(s);
return DISAS_NEXT;
}
if (!m34) {
return DISAS_NORETURN;
}
- gen_helper_cfdb(o->out, cpu_env, o->in2, m34);
+ gen_helper_cfdb(o->out, tcg_env, o->in2, m34);
set_cc_static(s);
return DISAS_NEXT;
}
if (!m34) {
return DISAS_NORETURN;
}
- gen_helper_cfxb(o->out, cpu_env, o->in2_128, m34);
+ gen_helper_cfxb(o->out, tcg_env, o->in2_128, m34);
set_cc_static(s);
return DISAS_NEXT;
}
if (!m34) {
return DISAS_NORETURN;
}
- gen_helper_cgeb(o->out, cpu_env, o->in2, m34);
+ gen_helper_cgeb(o->out, tcg_env, o->in2, m34);
set_cc_static(s);
return DISAS_NEXT;
}
if (!m34) {
return DISAS_NORETURN;
}
- gen_helper_cgdb(o->out, cpu_env, o->in2, m34);
+ gen_helper_cgdb(o->out, tcg_env, o->in2, m34);
set_cc_static(s);
return DISAS_NEXT;
}
if (!m34) {
return DISAS_NORETURN;
}
- gen_helper_cgxb(o->out, cpu_env, o->in2_128, m34);
+ gen_helper_cgxb(o->out, tcg_env, o->in2_128, m34);
set_cc_static(s);
return DISAS_NEXT;
}
if (!m34) {
return DISAS_NORETURN;
}
- gen_helper_clfeb(o->out, cpu_env, o->in2, m34);
+ gen_helper_clfeb(o->out, tcg_env, o->in2, m34);
set_cc_static(s);
return DISAS_NEXT;
}
if (!m34) {
return DISAS_NORETURN;
}
- gen_helper_clfdb(o->out, cpu_env, o->in2, m34);
+ gen_helper_clfdb(o->out, tcg_env, o->in2, m34);
set_cc_static(s);
return DISAS_NEXT;
}
if (!m34) {
return DISAS_NORETURN;
}
- gen_helper_clfxb(o->out, cpu_env, o->in2_128, m34);
+ gen_helper_clfxb(o->out, tcg_env, o->in2_128, m34);
set_cc_static(s);
return DISAS_NEXT;
}
if (!m34) {
return DISAS_NORETURN;
}
- gen_helper_clgeb(o->out, cpu_env, o->in2, m34);
+ gen_helper_clgeb(o->out, tcg_env, o->in2, m34);
set_cc_static(s);
return DISAS_NEXT;
}
if (!m34) {
return DISAS_NORETURN;
}
- gen_helper_clgdb(o->out, cpu_env, o->in2, m34);
+ gen_helper_clgdb(o->out, tcg_env, o->in2, m34);
set_cc_static(s);
return DISAS_NEXT;
}
if (!m34) {
return DISAS_NORETURN;
}
- gen_helper_clgxb(o->out, cpu_env, o->in2_128, m34);
+ gen_helper_clgxb(o->out, tcg_env, o->in2_128, m34);
set_cc_static(s);
return DISAS_NEXT;
}
if (!m34) {
return DISAS_NORETURN;
}
- gen_helper_cegb(o->out, cpu_env, o->in2, m34);
+ gen_helper_cegb(o->out, tcg_env, o->in2, m34);
return DISAS_NEXT;
}
if (!m34) {
return DISAS_NORETURN;
}
- gen_helper_cdgb(o->out, cpu_env, o->in2, m34);
+ gen_helper_cdgb(o->out, tcg_env, o->in2, m34);
return DISAS_NEXT;
}
if (!m34) {
return DISAS_NORETURN;
}
- gen_helper_cxgb(o->out_128, cpu_env, o->in2, m34);
+ gen_helper_cxgb(o->out_128, tcg_env, o->in2, m34);
return DISAS_NEXT;
}
if (!m34) {
return DISAS_NORETURN;
}
- gen_helper_celgb(o->out, cpu_env, o->in2, m34);
+ gen_helper_celgb(o->out, tcg_env, o->in2, m34);
return DISAS_NEXT;
}
if (!m34) {
return DISAS_NORETURN;
}
- gen_helper_cdlgb(o->out, cpu_env, o->in2, m34);
+ gen_helper_cdlgb(o->out, tcg_env, o->in2, m34);
return DISAS_NEXT;
}
if (!m34) {
return DISAS_NORETURN;
}
- gen_helper_cxlgb(o->out_128, cpu_env, o->in2, m34);
+ gen_helper_cxlgb(o->out_128, tcg_env, o->in2, m34);
return DISAS_NEXT;
}
TCGv_i128 pair = tcg_temp_new_i128();
TCGv_i64 len = tcg_temp_new_i64();
- gen_helper_cksm(pair, cpu_env, o->in1, o->in2, regs[r2 + 1]);
+ gen_helper_cksm(pair, tcg_env, o->in1, o->in2, regs[r2 + 1]);
set_cc_static(s);
tcg_gen_extr_i128_i64(o->out, len, pair);
return DISAS_NEXT;
default:
vl = tcg_constant_i32(l);
- gen_helper_clc(cc_op, cpu_env, vl, o->addr1, o->in2);
+ gen_helper_clc(cc_op, tcg_env, vl, o->addr1, o->in2);
set_cc_static(s);
return DISAS_NEXT;
}
t1 = tcg_constant_i32(r1);
t2 = tcg_constant_i32(r2);
- gen_helper_clcl(cc_op, cpu_env, t1, t2);
+ gen_helper_clcl(cc_op, tcg_env, t1, t2);
set_cc_static(s);
return DISAS_NEXT;
}
t1 = tcg_constant_i32(r1);
t3 = tcg_constant_i32(r3);
- gen_helper_clcle(cc_op, cpu_env, t1, o->in2, t3);
+ gen_helper_clcle(cc_op, tcg_env, t1, o->in2, t3);
set_cc_static(s);
return DISAS_NEXT;
}
t1 = tcg_constant_i32(r1);
t3 = tcg_constant_i32(r3);
- gen_helper_clclu(cc_op, cpu_env, t1, o->in2, t3);
+ gen_helper_clclu(cc_op, tcg_env, t1, o->in2, t3);
set_cc_static(s);
return DISAS_NEXT;
}
TCGv_i32 t1 = tcg_temp_new_i32();
tcg_gen_extrl_i64_i32(t1, o->in1);
- gen_helper_clm(cc_op, cpu_env, t1, m3, o->in2);
+ gen_helper_clm(cc_op, tcg_env, t1, m3, o->in2);
set_cc_static(s);
return DISAS_NEXT;
}
{
TCGv_i128 pair = tcg_temp_new_i128();
- gen_helper_clst(pair, cpu_env, regs[0], o->in1, o->in2);
+ gen_helper_clst(pair, tcg_env, regs[0], o->in1, o->in2);
tcg_gen_extr_i128_i64(o->in2, o->in1, pair);
set_cc_static(s);
TCGv_i32 t_r3 = tcg_constant_i32(r3);
if (tb_cflags(s->base.tb) & CF_PARALLEL) {
- gen_helper_csst_parallel(cc_op, cpu_env, t_r3, o->addr1, o->in2);
+ gen_helper_csst_parallel(cc_op, tcg_env, t_r3, o->addr1, o->in2);
} else {
- gen_helper_csst(cc_op, cpu_env, t_r3, o->addr1, o->in2);
+ gen_helper_csst(cc_op, tcg_env, t_r3, o->addr1, o->in2);
}
set_cc_static(s);
tcg_gen_and_i64(cc, cc, o->in2);
tcg_gen_brcondi_i64(TCG_COND_EQ, cc, 0, lab);
- gen_helper_purge(cpu_env);
+ gen_helper_purge(tcg_env);
gen_set_label(lab);
return DISAS_NEXT;
switch (s->insn->data) {
case 12:
- gen_helper_cu12(cc_op, cpu_env, tr1, tr2, chk);
+ gen_helper_cu12(cc_op, tcg_env, tr1, tr2, chk);
break;
case 14:
- gen_helper_cu14(cc_op, cpu_env, tr1, tr2, chk);
+ gen_helper_cu14(cc_op, tcg_env, tr1, tr2, chk);
break;
case 21:
- gen_helper_cu21(cc_op, cpu_env, tr1, tr2, chk);
+ gen_helper_cu21(cc_op, tcg_env, tr1, tr2, chk);
break;
case 24:
- gen_helper_cu24(cc_op, cpu_env, tr1, tr2, chk);
+ gen_helper_cu24(cc_op, tcg_env, tr1, tr2, chk);
break;
case 41:
- gen_helper_cu41(cc_op, cpu_env, tr1, tr2, chk);
+ gen_helper_cu41(cc_op, tcg_env, tr1, tr2, chk);
break;
case 42:
- gen_helper_cu42(cc_op, cpu_env, tr1, tr2, chk);
+ gen_helper_cu42(cc_op, tcg_env, tr1, tr2, chk);
break;
default:
g_assert_not_reached();
TCGv_i32 r3 = tcg_constant_i32(get_field(s, r3));
TCGv_i32 func_code = tcg_constant_i32(get_field(s, i2));
- gen_helper_diag(cpu_env, r1, r3, func_code);
+ gen_helper_diag(tcg_env, r1, r3, func_code);
return DISAS_NEXT;
}
#endif
static DisasJumpType op_divs32(DisasContext *s, DisasOps *o)
{
- gen_helper_divs32(o->out, cpu_env, o->in1, o->in2);
+ gen_helper_divs32(o->out, tcg_env, o->in1, o->in2);
tcg_gen_extr32_i64(o->out2, o->out, o->out);
return DISAS_NEXT;
}
static DisasJumpType op_divu32(DisasContext *s, DisasOps *o)
{
- gen_helper_divu32(o->out, cpu_env, o->in1, o->in2);
+ gen_helper_divu32(o->out, tcg_env, o->in1, o->in2);
tcg_gen_extr32_i64(o->out2, o->out, o->out);
return DISAS_NEXT;
}
{
TCGv_i128 t = tcg_temp_new_i128();
- gen_helper_divs64(t, cpu_env, o->in1, o->in2);
+ gen_helper_divs64(t, tcg_env, o->in1, o->in2);
tcg_gen_extr_i128_i64(o->out2, o->out, t);
return DISAS_NEXT;
}
{
TCGv_i128 t = tcg_temp_new_i128();
- gen_helper_divu64(t, cpu_env, o->out, o->out2, o->in2);
+ gen_helper_divu64(t, tcg_env, o->out, o->out2, o->in2);
tcg_gen_extr_i128_i64(o->out2, o->out, t);
return DISAS_NEXT;
}
static DisasJumpType op_deb(DisasContext *s, DisasOps *o)
{
- gen_helper_deb(o->out, cpu_env, o->in1, o->in2);
+ gen_helper_deb(o->out, tcg_env, o->in1, o->in2);
return DISAS_NEXT;
}
static DisasJumpType op_ddb(DisasContext *s, DisasOps *o)
{
- gen_helper_ddb(o->out, cpu_env, o->in1, o->in2);
+ gen_helper_ddb(o->out, tcg_env, o->in1, o->in2);
return DISAS_NEXT;
}
static DisasJumpType op_dxb(DisasContext *s, DisasOps *o)
{
- gen_helper_dxb(o->out_128, cpu_env, o->in1_128, o->in2_128);
+ gen_helper_dxb(o->out_128, tcg_env, o->in1_128, o->in2_128);
return DISAS_NEXT;
}
static DisasJumpType op_ear(DisasContext *s, DisasOps *o)
{
int r2 = get_field(s, r2);
- tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, aregs[r2]));
+ tcg_gen_ld32u_i64(o->out, tcg_env, offsetof(CPUS390XState, aregs[r2]));
return DISAS_NEXT;
}
static DisasJumpType op_efpc(DisasContext *s, DisasOps *o)
{
- tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, fpc));
+ tcg_gen_ld32u_i64(o->out, tcg_env, offsetof(CPUS390XState, fpc));
return DISAS_NEXT;
}
}
ilen = tcg_constant_i32(s->ilen);
- gen_helper_ex(cpu_env, ilen, v1, o->in2);
+ gen_helper_ex(tcg_env, ilen, v1, o->in2);
return DISAS_PC_CC_UPDATED;
}
if (!m34) {
return DISAS_NORETURN;
}
- gen_helper_fieb(o->out, cpu_env, o->in2, m34);
+ gen_helper_fieb(o->out, tcg_env, o->in2, m34);
return DISAS_NEXT;
}
if (!m34) {
return DISAS_NORETURN;
}
- gen_helper_fidb(o->out, cpu_env, o->in2, m34);
+ gen_helper_fidb(o->out, tcg_env, o->in2, m34);
return DISAS_NEXT;
}
if (!m34) {
return DISAS_NORETURN;
}
- gen_helper_fixb(o->out_128, cpu_env, o->in2_128, m34);
+ gen_helper_fixb(o->out_128, tcg_env, o->in2_128, m34);
return DISAS_NEXT;
}
} else {
m4 = tcg_constant_i32(0);
}
- gen_helper_idte(cpu_env, o->in1, o->in2, m4);
+ gen_helper_idte(tcg_env, o->in1, o->in2, m4);
return DISAS_NEXT;
}
} else {
m4 = tcg_constant_i32(0);
}
- gen_helper_ipte(cpu_env, o->in1, o->in2, m4);
+ gen_helper_ipte(tcg_env, o->in1, o->in2, m4);
return DISAS_NEXT;
}
static DisasJumpType op_iske(DisasContext *s, DisasOps *o)
{
- gen_helper_iske(o->out, cpu_env, o->in2);
+ gen_helper_iske(o->out, tcg_env, o->in2);
return DISAS_NEXT;
}
#endif
t_r2 = tcg_constant_i32(r2);
t_r3 = tcg_constant_i32(r3);
type = tcg_constant_i32(s->insn->data);
- gen_helper_msa(cc_op, cpu_env, t_r1, t_r2, t_r3, type);
+ gen_helper_msa(cc_op, tcg_env, t_r1, t_r2, t_r3, type);
set_cc_static(s);
return DISAS_NEXT;
}
static DisasJumpType op_keb(DisasContext *s, DisasOps *o)
{
- gen_helper_keb(cc_op, cpu_env, o->in1, o->in2);
+ gen_helper_keb(cc_op, tcg_env, o->in1, o->in2);
set_cc_static(s);
return DISAS_NEXT;
}
static DisasJumpType op_kdb(DisasContext *s, DisasOps *o)
{
- gen_helper_kdb(cc_op, cpu_env, o->in1, o->in2);
+ gen_helper_kdb(cc_op, tcg_env, o->in1, o->in2);
set_cc_static(s);
return DISAS_NEXT;
}
static DisasJumpType op_kxb(DisasContext *s, DisasOps *o)
{
- gen_helper_kxb(cc_op, cpu_env, o->in1_128, o->in2_128);
+ gen_helper_kxb(cc_op, tcg_env, o->in1_128, o->in2_128);
set_cc_static(s);
return DISAS_NEXT;
}
static DisasJumpType op_ldeb(DisasContext *s, DisasOps *o)
{
- gen_helper_ldeb(o->out, cpu_env, o->in2);
+ gen_helper_ldeb(o->out, tcg_env, o->in2);
return DISAS_NEXT;
}
if (!m34) {
return DISAS_NORETURN;
}
- gen_helper_ledb(o->out, cpu_env, o->in2, m34);
+ gen_helper_ledb(o->out, tcg_env, o->in2, m34);
return DISAS_NEXT;
}
if (!m34) {
return DISAS_NORETURN;
}
- gen_helper_ldxb(o->out, cpu_env, o->in2_128, m34);
+ gen_helper_ldxb(o->out, tcg_env, o->in2_128, m34);
return DISAS_NEXT;
}
if (!m34) {
return DISAS_NORETURN;
}
- gen_helper_lexb(o->out, cpu_env, o->in2_128, m34);
+ gen_helper_lexb(o->out, tcg_env, o->in2_128, m34);
return DISAS_NEXT;
}
static DisasJumpType op_lxdb(DisasContext *s, DisasOps *o)
{
- gen_helper_lxdb(o->out_128, cpu_env, o->in2);
+ gen_helper_lxdb(o->out_128, tcg_env, o->in2);
return DISAS_NEXT;
}
static DisasJumpType op_lxeb(DisasContext *s, DisasOps *o)
{
- gen_helper_lxeb(o->out_128, cpu_env, o->in2);
+ gen_helper_lxeb(o->out_128, tcg_env, o->in2);
return DISAS_NEXT;
}
TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1));
TCGv_i32 r3 = tcg_constant_i32(get_field(s, r3));
- gen_helper_lctl(cpu_env, r1, o->in2, r3);
+ gen_helper_lctl(tcg_env, r1, o->in2, r3);
/* Exit to main loop to reevaluate s390_cpu_exec_interrupt. */
s->exit_to_mainloop = true;
return DISAS_TOO_MANY;
TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1));
TCGv_i32 r3 = tcg_constant_i32(get_field(s, r3));
- gen_helper_lctlg(cpu_env, r1, o->in2, r3);
+ gen_helper_lctlg(tcg_env, r1, o->in2, r3);
/* Exit to main loop to reevaluate s390_cpu_exec_interrupt. */
s->exit_to_mainloop = true;
return DISAS_TOO_MANY;
static DisasJumpType op_lra(DisasContext *s, DisasOps *o)
{
- gen_helper_lra(o->out, cpu_env, o->out, o->in2);
+ gen_helper_lra(o->out, tcg_env, o->out, o->in2);
set_cc_static(s);
return DISAS_NEXT;
}
static DisasJumpType op_lpp(DisasContext *s, DisasOps *o)
{
- tcg_gen_st_i64(o->in2, cpu_env, offsetof(CPUS390XState, pp));
+ tcg_gen_st_i64(o->in2, tcg_env, offsetof(CPUS390XState, pp));
return DISAS_NEXT;
}
tcg_gen_andi_i64(addr, mask, PSW_MASK_SHORT_ADDR);
tcg_gen_andi_i64(mask, mask, PSW_MASK_SHORT_CTRL);
tcg_gen_xori_i64(mask, mask, PSW_MASK_SHORTPSW);
- gen_helper_load_psw(cpu_env, mask, addr);
+ gen_helper_load_psw(tcg_env, mask, addr);
return DISAS_NORETURN;
}
MO_TEUQ | MO_ALIGN_8);
tcg_gen_addi_i64(o->in2, o->in2, 8);
tcg_gen_qemu_ld_i64(t2, o->in2, get_mem_index(s), MO_TEUQ);
- gen_helper_load_psw(cpu_env, t1, t2);
+ gen_helper_load_psw(tcg_env, t1, t2);
return DISAS_NORETURN;
}
#endif
TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1));
TCGv_i32 r3 = tcg_constant_i32(get_field(s, r3));
- gen_helper_lam(cpu_env, r1, o->in2, r3);
+ gen_helper_lam(tcg_env, r1, o->in2, r3);
return DISAS_NEXT;
}
}
#if !defined(CONFIG_USER_ONLY)
- gen_helper_monitor_call(cpu_env, o->addr1,
+ gen_helper_monitor_call(tcg_env, o->addr1,
tcg_constant_i32(monitor_class));
#endif
/* Defaults to a NOP. */
break;
case PSW_ASC_SECONDARY >> FLAG_MASK_PSW_SHIFT:
if (b2) {
- tcg_gen_ld32u_i64(ar1, cpu_env, offsetof(CPUS390XState, aregs[b2]));
+ tcg_gen_ld32u_i64(ar1, tcg_env, offsetof(CPUS390XState, aregs[b2]));
} else {
tcg_gen_movi_i64(ar1, 0);
}
break;
}
- tcg_gen_st32_i64(ar1, cpu_env, offsetof(CPUS390XState, aregs[1]));
+ tcg_gen_st32_i64(ar1, tcg_env, offsetof(CPUS390XState, aregs[1]));
return DISAS_NEXT;
}
{
TCGv_i32 l = tcg_constant_i32(get_field(s, l1));
- gen_helper_mvc(cpu_env, l, o->addr1, o->in2);
+ gen_helper_mvc(tcg_env, l, o->addr1, o->in2);
return DISAS_NEXT;
}
static DisasJumpType op_mvcrl(DisasContext *s, DisasOps *o)
{
- gen_helper_mvcrl(cpu_env, regs[0], o->addr1, o->in2);
+ gen_helper_mvcrl(tcg_env, regs[0], o->addr1, o->in2);
return DISAS_NEXT;
}
{
TCGv_i32 l = tcg_constant_i32(get_field(s, l1));
- gen_helper_mvcin(cpu_env, l, o->addr1, o->in2);
+ gen_helper_mvcin(tcg_env, l, o->addr1, o->in2);
return DISAS_NEXT;
}
t1 = tcg_constant_i32(r1);
t2 = tcg_constant_i32(r2);
- gen_helper_mvcl(cc_op, cpu_env, t1, t2);
+ gen_helper_mvcl(cc_op, tcg_env, t1, t2);
set_cc_static(s);
return DISAS_NEXT;
}
t1 = tcg_constant_i32(r1);
t3 = tcg_constant_i32(r3);
- gen_helper_mvcle(cc_op, cpu_env, t1, o->in2, t3);
+ gen_helper_mvcle(cc_op, tcg_env, t1, o->in2, t3);
set_cc_static(s);
return DISAS_NEXT;
}
t1 = tcg_constant_i32(r1);
t3 = tcg_constant_i32(r3);
- gen_helper_mvclu(cc_op, cpu_env, t1, o->in2, t3);
+ gen_helper_mvclu(cc_op, tcg_env, t1, o->in2, t3);
set_cc_static(s);
return DISAS_NEXT;
}
static DisasJumpType op_mvcos(DisasContext *s, DisasOps *o)
{
int r3 = get_field(s, r3);
- gen_helper_mvcos(cc_op, cpu_env, o->addr1, o->in2, regs[r3]);
+ gen_helper_mvcos(cc_op, tcg_env, o->addr1, o->in2, regs[r3]);
set_cc_static(s);
return DISAS_NEXT;
}
{
int r1 = get_field(s, l1);
int r3 = get_field(s, r3);
- gen_helper_mvcp(cc_op, cpu_env, regs[r1], o->addr1, o->in2, regs[r3]);
+ gen_helper_mvcp(cc_op, tcg_env, regs[r1], o->addr1, o->in2, regs[r3]);
set_cc_static(s);
return DISAS_NEXT;
}
{
int r1 = get_field(s, l1);
int r3 = get_field(s, r3);
- gen_helper_mvcs(cc_op, cpu_env, regs[r1], o->addr1, o->in2, regs[r3]);
+ gen_helper_mvcs(cc_op, tcg_env, regs[r1], o->addr1, o->in2, regs[r3]);
set_cc_static(s);
return DISAS_NEXT;
}
{
TCGv_i32 l = tcg_constant_i32(get_field(s, l1));
- gen_helper_mvn(cpu_env, l, o->addr1, o->in2);
+ gen_helper_mvn(tcg_env, l, o->addr1, o->in2);
return DISAS_NEXT;
}
{
TCGv_i32 l = tcg_constant_i32(get_field(s, l1));
- gen_helper_mvo(cpu_env, l, o->addr1, o->in2);
+ gen_helper_mvo(tcg_env, l, o->addr1, o->in2);
return DISAS_NEXT;
}
TCGv_i32 t1 = tcg_constant_i32(get_field(s, r1));
TCGv_i32 t2 = tcg_constant_i32(get_field(s, r2));
- gen_helper_mvpg(cc_op, cpu_env, regs[0], t1, t2);
+ gen_helper_mvpg(cc_op, tcg_env, regs[0], t1, t2);
set_cc_static(s);
return DISAS_NEXT;
}
TCGv_i32 t1 = tcg_constant_i32(get_field(s, r1));
TCGv_i32 t2 = tcg_constant_i32(get_field(s, r2));
- gen_helper_mvst(cc_op, cpu_env, t1, t2);
+ gen_helper_mvst(cc_op, tcg_env, t1, t2);
set_cc_static(s);
return DISAS_NEXT;
}
{
TCGv_i32 l = tcg_constant_i32(get_field(s, l1));
- gen_helper_mvz(cpu_env, l, o->addr1, o->in2);
+ gen_helper_mvz(tcg_env, l, o->addr1, o->in2);
return DISAS_NEXT;
}
static DisasJumpType op_meeb(DisasContext *s, DisasOps *o)
{
- gen_helper_meeb(o->out, cpu_env, o->in1, o->in2);
+ gen_helper_meeb(o->out, tcg_env, o->in1, o->in2);
return DISAS_NEXT;
}
static DisasJumpType op_mdeb(DisasContext *s, DisasOps *o)
{
- gen_helper_mdeb(o->out, cpu_env, o->in1, o->in2);
+ gen_helper_mdeb(o->out, tcg_env, o->in1, o->in2);
return DISAS_NEXT;
}
static DisasJumpType op_mdb(DisasContext *s, DisasOps *o)
{
- gen_helper_mdb(o->out, cpu_env, o->in1, o->in2);
+ gen_helper_mdb(o->out, tcg_env, o->in1, o->in2);
return DISAS_NEXT;
}
static DisasJumpType op_mxb(DisasContext *s, DisasOps *o)
{
- gen_helper_mxb(o->out_128, cpu_env, o->in1_128, o->in2_128);
+ gen_helper_mxb(o->out_128, tcg_env, o->in1_128, o->in2_128);
return DISAS_NEXT;
}
static DisasJumpType op_mxdb(DisasContext *s, DisasOps *o)
{
- gen_helper_mxdb(o->out_128, cpu_env, o->in1, o->in2);
+ gen_helper_mxdb(o->out_128, tcg_env, o->in1, o->in2);
return DISAS_NEXT;
}
static DisasJumpType op_maeb(DisasContext *s, DisasOps *o)
{
TCGv_i64 r3 = load_freg32_i64(get_field(s, r3));
- gen_helper_maeb(o->out, cpu_env, o->in1, o->in2, r3);
+ gen_helper_maeb(o->out, tcg_env, o->in1, o->in2, r3);
return DISAS_NEXT;
}
static DisasJumpType op_madb(DisasContext *s, DisasOps *o)
{
TCGv_i64 r3 = load_freg(get_field(s, r3));
- gen_helper_madb(o->out, cpu_env, o->in1, o->in2, r3);
+ gen_helper_madb(o->out, tcg_env, o->in1, o->in2, r3);
return DISAS_NEXT;
}
static DisasJumpType op_mseb(DisasContext *s, DisasOps *o)
{
TCGv_i64 r3 = load_freg32_i64(get_field(s, r3));
- gen_helper_mseb(o->out, cpu_env, o->in1, o->in2, r3);
+ gen_helper_mseb(o->out, tcg_env, o->in1, o->in2, r3);
return DISAS_NEXT;
}
static DisasJumpType op_msdb(DisasContext *s, DisasOps *o)
{
TCGv_i64 r3 = load_freg(get_field(s, r3));
- gen_helper_msdb(o->out, cpu_env, o->in1, o->in2, r3);
+ gen_helper_msdb(o->out, tcg_env, o->in1, o->in2, r3);
return DISAS_NEXT;
}
{
TCGv_i32 l = tcg_constant_i32(get_field(s, l1));
- gen_helper_nc(cc_op, cpu_env, l, o->addr1, o->in2);
+ gen_helper_nc(cc_op, tcg_env, l, o->addr1, o->in2);
set_cc_static(s);
return DISAS_NEXT;
}
{
TCGv_i32 l = tcg_constant_i32(get_field(s, l1));
- gen_helper_oc(cc_op, cpu_env, l, o->addr1, o->in2);
+ gen_helper_oc(cc_op, tcg_env, l, o->addr1, o->in2);
set_cc_static(s);
return DISAS_NEXT;
}
{
TCGv_i32 l = tcg_constant_i32(get_field(s, l1));
- gen_helper_pack(cpu_env, l, o->addr1, o->in2);
+ gen_helper_pack(tcg_env, l, o->addr1, o->in2);
return DISAS_NEXT;
}
return DISAS_NORETURN;
}
l = tcg_constant_i32(l2);
- gen_helper_pka(cpu_env, o->addr1, o->in2, l);
+ gen_helper_pka(tcg_env, o->addr1, o->in2, l);
return DISAS_NEXT;
}
return DISAS_NORETURN;
}
l = tcg_constant_i32(l2);
- gen_helper_pku(cpu_env, o->addr1, o->in2, l);
+ gen_helper_pku(tcg_env, o->addr1, o->in2, l);
return DISAS_NEXT;
}
#ifndef CONFIG_USER_ONLY
static DisasJumpType op_ptlb(DisasContext *s, DisasOps *o)
{
- gen_helper_ptlb(cpu_env);
+ gen_helper_ptlb(tcg_env);
return DISAS_NEXT;
}
#endif
#ifndef CONFIG_USER_ONLY
static DisasJumpType op_rrbe(DisasContext *s, DisasOps *o)
{
- gen_helper_rrbe(cc_op, cpu_env, o->in2);
+ gen_helper_rrbe(cc_op, tcg_env, o->in2);
set_cc_static(s);
return DISAS_NEXT;
}
static DisasJumpType op_sacf(DisasContext *s, DisasOps *o)
{
- gen_helper_sacf(cpu_env, o->in2);
+ gen_helper_sacf(tcg_env, o->in2);
/* Addressing mode has changed, so end the block. */
return DISAS_TOO_MANY;
}
static DisasJumpType op_sar(DisasContext *s, DisasOps *o)
{
int r1 = get_field(s, r1);
- tcg_gen_st32_i64(o->in2, cpu_env, offsetof(CPUS390XState, aregs[r1]));
+ tcg_gen_st32_i64(o->in2, tcg_env, offsetof(CPUS390XState, aregs[r1]));
return DISAS_NEXT;
}
static DisasJumpType op_seb(DisasContext *s, DisasOps *o)
{
- gen_helper_seb(o->out, cpu_env, o->in1, o->in2);
+ gen_helper_seb(o->out, tcg_env, o->in1, o->in2);
return DISAS_NEXT;
}
static DisasJumpType op_sdb(DisasContext *s, DisasOps *o)
{
- gen_helper_sdb(o->out, cpu_env, o->in1, o->in2);
+ gen_helper_sdb(o->out, tcg_env, o->in1, o->in2);
return DISAS_NEXT;
}
static DisasJumpType op_sxb(DisasContext *s, DisasOps *o)
{
- gen_helper_sxb(o->out_128, cpu_env, o->in1_128, o->in2_128);
+ gen_helper_sxb(o->out_128, tcg_env, o->in1_128, o->in2_128);
return DISAS_NEXT;
}
static DisasJumpType op_sqeb(DisasContext *s, DisasOps *o)
{
- gen_helper_sqeb(o->out, cpu_env, o->in2);
+ gen_helper_sqeb(o->out, tcg_env, o->in2);
return DISAS_NEXT;
}
static DisasJumpType op_sqdb(DisasContext *s, DisasOps *o)
{
- gen_helper_sqdb(o->out, cpu_env, o->in2);
+ gen_helper_sqdb(o->out, tcg_env, o->in2);
return DISAS_NEXT;
}
static DisasJumpType op_sqxb(DisasContext *s, DisasOps *o)
{
- gen_helper_sqxb(o->out_128, cpu_env, o->in2_128);
+ gen_helper_sqxb(o->out_128, tcg_env, o->in2_128);
return DISAS_NEXT;
}
#ifndef CONFIG_USER_ONLY
static DisasJumpType op_servc(DisasContext *s, DisasOps *o)
{
- gen_helper_servc(cc_op, cpu_env, o->in2, o->in1);
+ gen_helper_servc(cc_op, tcg_env, o->in2, o->in1);
set_cc_static(s);
return DISAS_NEXT;
}
TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1));
TCGv_i32 r3 = tcg_constant_i32(get_field(s, r3));
- gen_helper_sigp(cc_op, cpu_env, o->in2, r1, r3);
+ gen_helper_sigp(cc_op, tcg_env, o->in2, r1, r3);
set_cc_static(s);
return DISAS_NEXT;
}
static DisasJumpType op_sfpc(DisasContext *s, DisasOps *o)
{
- gen_helper_sfpc(cpu_env, o->in2);
+ gen_helper_sfpc(tcg_env, o->in2);
return DISAS_NEXT;
}
static DisasJumpType op_sfas(DisasContext *s, DisasOps *o)
{
- gen_helper_sfas(cpu_env, o->in2);
+ gen_helper_sfas(tcg_env, o->in2);
return DISAS_NEXT;
}
{
/* Bits other than 62 and 63 are ignored. Bit 29 is set to zero. */
tcg_gen_andi_i64(o->addr1, o->addr1, 0x3ull);
- gen_helper_srnm(cpu_env, o->addr1);
+ gen_helper_srnm(tcg_env, o->addr1);
return DISAS_NEXT;
}
{
/* Bits 0-55 are are ignored. */
tcg_gen_andi_i64(o->addr1, o->addr1, 0xffull);
- gen_helper_srnm(cpu_env, o->addr1);
+ gen_helper_srnm(tcg_env, o->addr1);
return DISAS_NEXT;
}
tcg_gen_andi_i64(o->addr1, o->addr1, 0x7ull);
/* No need to call a helper, we don't implement dfp */
- tcg_gen_ld32u_i64(tmp, cpu_env, offsetof(CPUS390XState, fpc));
+ tcg_gen_ld32u_i64(tmp, tcg_env, offsetof(CPUS390XState, fpc));
tcg_gen_deposit_i64(tmp, tmp, o->addr1, 4, 3);
- tcg_gen_st32_i64(tmp, cpu_env, offsetof(CPUS390XState, fpc));
+ tcg_gen_st32_i64(tmp, tcg_env, offsetof(CPUS390XState, fpc));
return DISAS_NEXT;
}
tcg_gen_qemu_ld_i64(regs[r3], o->addr1, get_mem_index(s), MO_TEUQ);
/* subtract CPU timer from first operand and store in GR0 */
- gen_helper_stpt(tmp, cpu_env);
+ gen_helper_stpt(tmp, tcg_env);
tcg_gen_sub_i64(regs[0], o->in1, tmp);
/* store second operand in GR1 */
static DisasJumpType op_sske(DisasContext *s, DisasOps *o)
{
- gen_helper_sske(cpu_env, o->in1, o->in2);
+ gen_helper_sske(tcg_env, o->in1, o->in2);
return DISAS_NEXT;
}
static DisasJumpType op_stap(DisasContext *s, DisasOps *o)
{
- tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, core_id));
+ tcg_gen_ld32u_i64(o->out, tcg_env, offsetof(CPUS390XState, core_id));
return DISAS_NEXT;
}
#endif
static DisasJumpType op_stck(DisasContext *s, DisasOps *o)
{
- gen_helper_stck(o->out, cpu_env);
+ gen_helper_stck(o->out, tcg_env);
/* ??? We don't implement clock states. */
gen_op_movi_cc(s, 0);
return DISAS_NEXT;
TCGv_i64 c1 = tcg_temp_new_i64();
TCGv_i64 c2 = tcg_temp_new_i64();
TCGv_i64 todpr = tcg_temp_new_i64();
- gen_helper_stck(c1, cpu_env);
+ gen_helper_stck(c1, tcg_env);
/* 16 bit value store in an uint32_t (only valid bits set) */
- tcg_gen_ld32u_i64(todpr, cpu_env, offsetof(CPUS390XState, todpr));
+ tcg_gen_ld32u_i64(todpr, tcg_env, offsetof(CPUS390XState, todpr));
/* Shift the 64-bit value into its place as a zero-extended
104-bit value. Note that "bit positions 64-103 are always
non-zero so that they compare differently to STCK"; we set
#ifndef CONFIG_USER_ONLY
static DisasJumpType op_sck(DisasContext *s, DisasOps *o)
{
- gen_helper_sck(cc_op, cpu_env, o->in2);
+ gen_helper_sck(cc_op, tcg_env, o->in2);
set_cc_static(s);
return DISAS_NEXT;
}
static DisasJumpType op_sckc(DisasContext *s, DisasOps *o)
{
- gen_helper_sckc(cpu_env, o->in2);
+ gen_helper_sckc(tcg_env, o->in2);
return DISAS_NEXT;
}
static DisasJumpType op_sckpf(DisasContext *s, DisasOps *o)
{
- gen_helper_sckpf(cpu_env, regs[0]);
+ gen_helper_sckpf(tcg_env, regs[0]);
return DISAS_NEXT;
}
static DisasJumpType op_stckc(DisasContext *s, DisasOps *o)
{
- gen_helper_stckc(o->out, cpu_env);
+ gen_helper_stckc(o->out, tcg_env);
return DISAS_NEXT;
}
TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1));
TCGv_i32 r3 = tcg_constant_i32(get_field(s, r3));
- gen_helper_stctg(cpu_env, r1, o->in2, r3);
+ gen_helper_stctg(tcg_env, r1, o->in2, r3);
return DISAS_NEXT;
}
TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1));
TCGv_i32 r3 = tcg_constant_i32(get_field(s, r3));
- gen_helper_stctl(cpu_env, r1, o->in2, r3);
+ gen_helper_stctl(tcg_env, r1, o->in2, r3);
return DISAS_NEXT;
}
static DisasJumpType op_stidp(DisasContext *s, DisasOps *o)
{
- tcg_gen_ld_i64(o->out, cpu_env, offsetof(CPUS390XState, cpuid));
+ tcg_gen_ld_i64(o->out, tcg_env, offsetof(CPUS390XState, cpuid));
return DISAS_NEXT;
}
static DisasJumpType op_spt(DisasContext *s, DisasOps *o)
{
- gen_helper_spt(cpu_env, o->in2);
+ gen_helper_spt(tcg_env, o->in2);
return DISAS_NEXT;
}
static DisasJumpType op_stfl(DisasContext *s, DisasOps *o)
{
- gen_helper_stfl(cpu_env);
+ gen_helper_stfl(tcg_env);
return DISAS_NEXT;
}
static DisasJumpType op_stpt(DisasContext *s, DisasOps *o)
{
- gen_helper_stpt(o->out, cpu_env);
+ gen_helper_stpt(o->out, tcg_env);
return DISAS_NEXT;
}
static DisasJumpType op_stsi(DisasContext *s, DisasOps *o)
{
- gen_helper_stsi(cc_op, cpu_env, o->in2, regs[0], regs[1]);
+ gen_helper_stsi(cc_op, tcg_env, o->in2, regs[0], regs[1]);
set_cc_static(s);
return DISAS_NEXT;
}
static DisasJumpType op_spx(DisasContext *s, DisasOps *o)
{
- gen_helper_spx(cpu_env, o->in2);
+ gen_helper_spx(tcg_env, o->in2);
return DISAS_NEXT;
}
static DisasJumpType op_xsch(DisasContext *s, DisasOps *o)
{
- gen_helper_xsch(cpu_env, regs[1]);
+ gen_helper_xsch(tcg_env, regs[1]);
set_cc_static(s);
return DISAS_NEXT;
}
static DisasJumpType op_csch(DisasContext *s, DisasOps *o)
{
- gen_helper_csch(cpu_env, regs[1]);
+ gen_helper_csch(tcg_env, regs[1]);
set_cc_static(s);
return DISAS_NEXT;
}
static DisasJumpType op_hsch(DisasContext *s, DisasOps *o)
{
- gen_helper_hsch(cpu_env, regs[1]);
+ gen_helper_hsch(tcg_env, regs[1]);
set_cc_static(s);
return DISAS_NEXT;
}
static DisasJumpType op_msch(DisasContext *s, DisasOps *o)
{
- gen_helper_msch(cpu_env, regs[1], o->in2);
+ gen_helper_msch(tcg_env, regs[1], o->in2);
set_cc_static(s);
return DISAS_NEXT;
}
static DisasJumpType op_rchp(DisasContext *s, DisasOps *o)
{
- gen_helper_rchp(cpu_env, regs[1]);
+ gen_helper_rchp(tcg_env, regs[1]);
set_cc_static(s);
return DISAS_NEXT;
}
static DisasJumpType op_rsch(DisasContext *s, DisasOps *o)
{
- gen_helper_rsch(cpu_env, regs[1]);
+ gen_helper_rsch(tcg_env, regs[1]);
set_cc_static(s);
return DISAS_NEXT;
}
static DisasJumpType op_sal(DisasContext *s, DisasOps *o)
{
- gen_helper_sal(cpu_env, regs[1]);
+ gen_helper_sal(tcg_env, regs[1]);
return DISAS_NEXT;
}
static DisasJumpType op_schm(DisasContext *s, DisasOps *o)
{
- gen_helper_schm(cpu_env, regs[1], regs[2], o->in2);
+ gen_helper_schm(tcg_env, regs[1], regs[2], o->in2);
return DISAS_NEXT;
}
static DisasJumpType op_ssch(DisasContext *s, DisasOps *o)
{
- gen_helper_ssch(cpu_env, regs[1], o->in2);
+ gen_helper_ssch(tcg_env, regs[1], o->in2);
set_cc_static(s);
return DISAS_NEXT;
}
static DisasJumpType op_stsch(DisasContext *s, DisasOps *o)
{
- gen_helper_stsch(cpu_env, regs[1], o->in2);
+ gen_helper_stsch(tcg_env, regs[1], o->in2);
set_cc_static(s);
return DISAS_NEXT;
}
static DisasJumpType op_stcrw(DisasContext *s, DisasOps *o)
{
- gen_helper_stcrw(cpu_env, o->in2);
+ gen_helper_stcrw(tcg_env, o->in2);
set_cc_static(s);
return DISAS_NEXT;
}
static DisasJumpType op_tpi(DisasContext *s, DisasOps *o)
{
- gen_helper_tpi(cc_op, cpu_env, o->addr1);
+ gen_helper_tpi(cc_op, tcg_env, o->addr1);
set_cc_static(s);
return DISAS_NEXT;
}
static DisasJumpType op_tsch(DisasContext *s, DisasOps *o)
{
- gen_helper_tsch(cpu_env, regs[1], o->in2);
+ gen_helper_tsch(tcg_env, regs[1], o->in2);
set_cc_static(s);
return DISAS_NEXT;
}
static DisasJumpType op_chsc(DisasContext *s, DisasOps *o)
{
- gen_helper_chsc(cpu_env, o->in2);
+ gen_helper_chsc(tcg_env, o->in2);
set_cc_static(s);
return DISAS_NEXT;
}
static DisasJumpType op_stpx(DisasContext *s, DisasOps *o)
{
- tcg_gen_ld_i64(o->out, cpu_env, offsetof(CPUS390XState, psa));
+ tcg_gen_ld_i64(o->out, tcg_env, offsetof(CPUS390XState, psa));
tcg_gen_andi_i64(o->out, o->out, 0x7fffe000);
return DISAS_NEXT;
}
if (s->base.tb->flags & FLAG_MASK_PER) {
update_psw_addr(s);
- gen_helper_per_store_real(cpu_env);
+ gen_helper_per_store_real(tcg_env);
}
return DISAS_NEXT;
}
static DisasJumpType op_stfle(DisasContext *s, DisasOps *o)
{
- gen_helper_stfle(cc_op, cpu_env, o->in2);
+ gen_helper_stfle(cc_op, tcg_env, o->in2);
set_cc_static(s);
return DISAS_NEXT;
}
TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1));
TCGv_i32 r3 = tcg_constant_i32(get_field(s, r3));
- gen_helper_stam(cpu_env, r1, o->in2, r3);
+ gen_helper_stam(tcg_env, r1, o->in2, r3);
return DISAS_NEXT;
}
TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1));
TCGv_i32 r2 = tcg_constant_i32(get_field(s, r2));
- gen_helper_srst(cpu_env, r1, r2);
+ gen_helper_srst(tcg_env, r1, r2);
set_cc_static(s);
return DISAS_NEXT;
}
TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1));
TCGv_i32 r2 = tcg_constant_i32(get_field(s, r2));
- gen_helper_srstu(cpu_env, r1, r2);
+ gen_helper_srstu(tcg_env, r1, r2);
set_cc_static(s);
return DISAS_NEXT;
}
update_cc_op(s);
t = tcg_constant_i32(get_field(s, i1) & 0xff);
- tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, int_svc_code));
+ tcg_gen_st_i32(t, tcg_env, offsetof(CPUS390XState, int_svc_code));
t = tcg_constant_i32(s->ilen);
- tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, int_svc_ilen));
+ tcg_gen_st_i32(t, tcg_env, offsetof(CPUS390XState, int_svc_ilen));
gen_exception(EXCP_SVC);
return DISAS_NORETURN;
static DisasJumpType op_tceb(DisasContext *s, DisasOps *o)
{
- gen_helper_tceb(cc_op, cpu_env, o->in1, o->in2);
+ gen_helper_tceb(cc_op, tcg_env, o->in1, o->in2);
set_cc_static(s);
return DISAS_NEXT;
}
static DisasJumpType op_tcdb(DisasContext *s, DisasOps *o)
{
- gen_helper_tcdb(cc_op, cpu_env, o->in1, o->in2);
+ gen_helper_tcdb(cc_op, tcg_env, o->in1, o->in2);
set_cc_static(s);
return DISAS_NEXT;
}
static DisasJumpType op_tcxb(DisasContext *s, DisasOps *o)
{
- gen_helper_tcxb(cc_op, cpu_env, o->in1_128, o->in2);
+ gen_helper_tcxb(cc_op, tcg_env, o->in1_128, o->in2);
set_cc_static(s);
return DISAS_NEXT;
}
static DisasJumpType op_testblock(DisasContext *s, DisasOps *o)
{
- gen_helper_testblock(cc_op, cpu_env, o->in2);
+ gen_helper_testblock(cc_op, tcg_env, o->in2);
set_cc_static(s);
return DISAS_NEXT;
}
static DisasJumpType op_tprot(DisasContext *s, DisasOps *o)
{
- gen_helper_tprot(cc_op, cpu_env, o->addr1, o->in2);
+ gen_helper_tprot(cc_op, tcg_env, o->addr1, o->in2);
set_cc_static(s);
return DISAS_NEXT;
}
{
TCGv_i32 l1 = tcg_constant_i32(get_field(s, l1) + 1);
- gen_helper_tp(cc_op, cpu_env, o->addr1, l1);
+ gen_helper_tp(cc_op, tcg_env, o->addr1, l1);
set_cc_static(s);
return DISAS_NEXT;
}
{
TCGv_i32 l = tcg_constant_i32(get_field(s, l1));
- gen_helper_tr(cpu_env, l, o->addr1, o->in2);
+ gen_helper_tr(tcg_env, l, o->addr1, o->in2);
set_cc_static(s);
return DISAS_NEXT;
}
{
TCGv_i128 pair = tcg_temp_new_i128();
- gen_helper_tre(pair, cpu_env, o->out, o->out2, o->in2);
+ gen_helper_tre(pair, tcg_env, o->out, o->out2, o->in2);
tcg_gen_extr_i128_i64(o->out2, o->out, pair);
set_cc_static(s);
return DISAS_NEXT;
{
TCGv_i32 l = tcg_constant_i32(get_field(s, l1));
- gen_helper_trt(cc_op, cpu_env, l, o->addr1, o->in2);
+ gen_helper_trt(cc_op, tcg_env, l, o->addr1, o->in2);
set_cc_static(s);
return DISAS_NEXT;
}
{
TCGv_i32 l = tcg_constant_i32(get_field(s, l1));
- gen_helper_trtr(cc_op, cpu_env, l, o->addr1, o->in2);
+ gen_helper_trtr(cc_op, tcg_env, l, o->addr1, o->in2);
set_cc_static(s);
return DISAS_NEXT;
}
tcg_gen_ext16u_i32(tst, tst);
}
}
- gen_helper_trXX(cc_op, cpu_env, r1, r2, tst, sizes);
+ gen_helper_trXX(cc_op, tcg_env, r1, r2, tst, sizes);
set_cc_static(s);
return DISAS_NEXT;
{
TCGv_i32 l = tcg_constant_i32(get_field(s, l1));
- gen_helper_unpk(cpu_env, l, o->addr1, o->in2);
+ gen_helper_unpk(tcg_env, l, o->addr1, o->in2);
return DISAS_NEXT;
}
return DISAS_NORETURN;
}
l = tcg_constant_i32(l1);
- gen_helper_unpka(cc_op, cpu_env, o->addr1, l, o->in2);
+ gen_helper_unpka(cc_op, tcg_env, o->addr1, l, o->in2);
set_cc_static(s);
return DISAS_NEXT;
}
return DISAS_NORETURN;
}
l = tcg_constant_i32(l1);
- gen_helper_unpku(cc_op, cpu_env, o->addr1, l, o->in2);
+ gen_helper_unpku(cc_op, tcg_env, o->addr1, l, o->in2);
set_cc_static(s);
return DISAS_NEXT;
}
/* But in general we'll defer to a helper. */
o->in2 = get_address(s, 0, b2, d2);
t32 = tcg_constant_i32(l);
- gen_helper_xc(cc_op, cpu_env, t32, o->addr1, o->in2);
+ gen_helper_xc(cc_op, tcg_env, t32, o->addr1, o->in2);
set_cc_static(s);
return DISAS_NEXT;
}
{
TCGv_i32 r2 = tcg_constant_i32(get_field(s, r2));
- gen_helper_clp(cpu_env, r2);
+ gen_helper_clp(tcg_env, r2);
set_cc_static(s);
return DISAS_NEXT;
}
TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1));
TCGv_i32 r2 = tcg_constant_i32(get_field(s, r2));
- gen_helper_pcilg(cpu_env, r1, r2);
+ gen_helper_pcilg(tcg_env, r1, r2);
set_cc_static(s);
return DISAS_NEXT;
}
TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1));
TCGv_i32 r2 = tcg_constant_i32(get_field(s, r2));
- gen_helper_pcistg(cpu_env, r1, r2);
+ gen_helper_pcistg(tcg_env, r1, r2);
set_cc_static(s);
return DISAS_NEXT;
}
TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1));
TCGv_i32 ar = tcg_constant_i32(get_field(s, b2));
- gen_helper_stpcifc(cpu_env, r1, o->addr1, ar);
+ gen_helper_stpcifc(tcg_env, r1, o->addr1, ar);
set_cc_static(s);
return DISAS_NEXT;
}
static DisasJumpType op_sic(DisasContext *s, DisasOps *o)
{
- gen_helper_sic(cpu_env, o->in1, o->in2);
+ gen_helper_sic(tcg_env, o->in1, o->in2);
return DISAS_NEXT;
}
TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1));
TCGv_i32 r2 = tcg_constant_i32(get_field(s, r2));
- gen_helper_rpcit(cpu_env, r1, r2);
+ gen_helper_rpcit(tcg_env, r1, r2);
set_cc_static(s);
return DISAS_NEXT;
}
TCGv_i32 r3 = tcg_constant_i32(get_field(s, r3));
TCGv_i32 ar = tcg_constant_i32(get_field(s, b2));
- gen_helper_pcistb(cpu_env, r1, r3, o->addr1, ar);
+ gen_helper_pcistb(tcg_env, r1, r3, o->addr1, ar);
set_cc_static(s);
return DISAS_NEXT;
}
TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1));
TCGv_i32 ar = tcg_constant_i32(get_field(s, b2));
- gen_helper_mpcifc(cpu_env, r1, o->addr1, ar);
+ gen_helper_mpcifc(tcg_env, r1, o->addr1, ar);
set_cc_static(s);
return DISAS_NEXT;
}
if (unlikely(s->ex_value)) {
/* Drop the EX data now, so that it's clear on exception paths. */
- tcg_gen_st_i64(tcg_constant_i64(0), cpu_env,
+ tcg_gen_st_i64(tcg_constant_i64(0), tcg_env,
offsetof(CPUS390XState, ex_value));
/* Extract the values saved by EXECUTE. */
#ifndef CONFIG_USER_ONLY
if (s->base.tb->flags & FLAG_MASK_PER) {
TCGv_i64 addr = tcg_constant_i64(s->base.pc_next);
- gen_helper_per_ifetch(cpu_env, addr);
+ gen_helper_per_ifetch(tcg_env, addr);
}
#endif
}
/* Call the helper to check for a possible PER exception. */
- gen_helper_per_check_exception(cpu_env);
+ gen_helper_per_check_exception(tcg_env);
}
#endif
*
* CC handling:
* As gvec ool-helpers can currently not return values (besides via
- * pointers like vectors or cpu_env), whenever we have to set the CC and
+ * pointers like vectors or tcg_env), whenever we have to set the CC and
* can't conclude the value from the result vector, we will directly
* set it in "env->cc_op" and mark it as static via set_cc_static()".
* Whenever this is done, the helper writes globals (cc_op).
switch ((unsigned)memop) {
case ES_8:
- tcg_gen_ld8u_i64(dst, cpu_env, offs);
+ tcg_gen_ld8u_i64(dst, tcg_env, offs);
break;
case ES_16:
- tcg_gen_ld16u_i64(dst, cpu_env, offs);
+ tcg_gen_ld16u_i64(dst, tcg_env, offs);
break;
case ES_32:
- tcg_gen_ld32u_i64(dst, cpu_env, offs);
+ tcg_gen_ld32u_i64(dst, tcg_env, offs);
break;
case ES_8 | MO_SIGN:
- tcg_gen_ld8s_i64(dst, cpu_env, offs);
+ tcg_gen_ld8s_i64(dst, tcg_env, offs);
break;
case ES_16 | MO_SIGN:
- tcg_gen_ld16s_i64(dst, cpu_env, offs);
+ tcg_gen_ld16s_i64(dst, tcg_env, offs);
break;
case ES_32 | MO_SIGN:
- tcg_gen_ld32s_i64(dst, cpu_env, offs);
+ tcg_gen_ld32s_i64(dst, tcg_env, offs);
break;
case ES_64:
case ES_64 | MO_SIGN:
- tcg_gen_ld_i64(dst, cpu_env, offs);
+ tcg_gen_ld_i64(dst, tcg_env, offs);
break;
default:
g_assert_not_reached();
switch (memop) {
case ES_8:
- tcg_gen_ld8u_i32(dst, cpu_env, offs);
+ tcg_gen_ld8u_i32(dst, tcg_env, offs);
break;
case ES_16:
- tcg_gen_ld16u_i32(dst, cpu_env, offs);
+ tcg_gen_ld16u_i32(dst, tcg_env, offs);
break;
case ES_8 | MO_SIGN:
- tcg_gen_ld8s_i32(dst, cpu_env, offs);
+ tcg_gen_ld8s_i32(dst, tcg_env, offs);
break;
case ES_16 | MO_SIGN:
- tcg_gen_ld16s_i32(dst, cpu_env, offs);
+ tcg_gen_ld16s_i32(dst, tcg_env, offs);
break;
case ES_32:
case ES_32 | MO_SIGN:
- tcg_gen_ld_i32(dst, cpu_env, offs);
+ tcg_gen_ld_i32(dst, tcg_env, offs);
break;
default:
g_assert_not_reached();
switch (memop) {
case ES_8:
- tcg_gen_st8_i64(src, cpu_env, offs);
+ tcg_gen_st8_i64(src, tcg_env, offs);
break;
case ES_16:
- tcg_gen_st16_i64(src, cpu_env, offs);
+ tcg_gen_st16_i64(src, tcg_env, offs);
break;
case ES_32:
- tcg_gen_st32_i64(src, cpu_env, offs);
+ tcg_gen_st32_i64(src, tcg_env, offs);
break;
case ES_64:
- tcg_gen_st_i64(src, cpu_env, offs);
+ tcg_gen_st_i64(src, tcg_env, offs);
break;
default:
g_assert_not_reached();
switch (memop) {
case ES_8:
- tcg_gen_st8_i32(src, cpu_env, offs);
+ tcg_gen_st8_i32(src, tcg_env, offs);
break;
case ES_16:
- tcg_gen_st16_i32(src, cpu_env, offs);
+ tcg_gen_st16_i32(src, tcg_env, offs);
break;
case ES_32:
- tcg_gen_st_i32(src, cpu_env, offs);
+ tcg_gen_st_i32(src, tcg_env, offs);
break;
default:
g_assert_not_reached();
/* mask off invalid parts from the element nr */
tcg_gen_andi_i64(tmp, enr, NUM_VEC_ELEMENTS(es) - 1);
- /* convert it to an element offset relative to cpu_env (vec_reg_offset() */
+ /* convert it to an element offset relative to tcg_env (vec_reg_offset() */
tcg_gen_shli_i64(tmp, tmp, es);
#if !HOST_BIG_ENDIAN
tcg_gen_xori_i64(tmp, tmp, 8 - NUM_VEC_ELEMENT_BYTES(es));
#endif
tcg_gen_addi_i64(tmp, tmp, vec_full_reg_offset(reg));
- /* generate the final ptr by adding cpu_env */
+ /* generate the final ptr by adding tcg_env */
tcg_gen_trunc_i64_ptr(ptr, tmp);
- tcg_gen_add_ptr(ptr, ptr, cpu_env);
+ tcg_gen_add_ptr(ptr, ptr, tcg_env);
}
#define gen_gvec_2(v1, v2, gen) \
tcg_gen_ori_i64(bytes, o->addr1, -block_size);
tcg_gen_neg_i64(bytes, bytes);
- tcg_gen_addi_ptr(a0, cpu_env, v1_offs);
- gen_helper_vll(cpu_env, a0, o->addr1, bytes);
+ tcg_gen_addi_ptr(a0, tcg_env, v1_offs);
+ gen_helper_vll(tcg_env, a0, o->addr1, bytes);
return DISAS_NEXT;
}
/* convert highest index into an actual length */
tcg_gen_addi_i64(o->in2, o->in2, 1);
- tcg_gen_addi_ptr(a0, cpu_env, v1_offs);
- gen_helper_vll(cpu_env, a0, o->addr1, o->in2);
+ tcg_gen_addi_ptr(a0, tcg_env, v1_offs);
+ gen_helper_vll(tcg_env, a0, o->addr1, o->in2);
return DISAS_NEXT;
}
switch (s->fields.op2) {
case 0x97:
if (get_field(s, m5) & 0x1) {
- gen_gvec_3_ptr(v1, v2, v3, cpu_env, 0, vpks_cc[es - 1]);
+ gen_gvec_3_ptr(v1, v2, v3, tcg_env, 0, vpks_cc[es - 1]);
set_cc_static(s);
} else {
gen_gvec_3_ool(v1, v2, v3, 0, vpks[es - 1]);
break;
case 0x95:
if (get_field(s, m5) & 0x1) {
- gen_gvec_3_ptr(v1, v2, v3, cpu_env, 0, vpkls_cc[es - 1]);
+ gen_gvec_3_ptr(v1, v2, v3, tcg_env, 0, vpkls_cc[es - 1]);
set_cc_static(s);
} else {
gen_gvec_3_ool(v1, v2, v3, 0, vpkls[es - 1]);
TCGv_i64 tmp;
/* Probe write access before actually modifying memory */
- gen_helper_probe_write_access(cpu_env, o->addr1,
+ gen_helper_probe_write_access(tcg_env, o->addr1,
tcg_constant_i64(16));
tmp = tcg_temp_new_i64();
}
/* Probe write access before actually modifying memory */
- gen_helper_probe_write_access(cpu_env, o->addr1, tcg_constant_i64(16));
+ gen_helper_probe_write_access(tcg_env, o->addr1, tcg_constant_i64(16));
t0 = tcg_temp_new_i64();
t1 = tcg_temp_new_i64();
}
/* Probe write access before actually modifying memory */
- gen_helper_probe_write_access(cpu_env, o->addr1, tcg_constant_i64(16));
+ gen_helper_probe_write_access(tcg_env, o->addr1, tcg_constant_i64(16));
/* Begin with the two doublewords swapped... */
t0 = tcg_temp_new_i64();
}
/* Probe write access before actually modifying memory */
- gen_helper_probe_write_access(cpu_env, o->addr1,
+ gen_helper_probe_write_access(tcg_env, o->addr1,
tcg_constant_i64((v3 - v1 + 1) * 16));
tmp = tcg_temp_new_i64();
/* convert highest index into an actual length */
tcg_gen_addi_i64(o->in2, o->in2, 1);
- tcg_gen_addi_ptr(a0, cpu_env, v1_offs);
- gen_helper_vstl(cpu_env, a0, o->addr1, o->in2);
+ tcg_gen_addi_ptr(a0, tcg_env, v1_offs);
+ gen_helper_vstl(tcg_env, a0, o->addr1, o->in2);
return DISAS_NEXT;
}
static DisasJumpType op_vtm(DisasContext *s, DisasOps *o)
{
gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2),
- cpu_env, 0, gen_helper_gvec_vtm);
+ tcg_env, 0, gen_helper_gvec_vtm);
set_cc_static(s);
return DISAS_NEXT;
}
if (extract32(m5, 0, 1)) {
gen_gvec_3_ptr(get_field(s, v1), get_field(s, v2),
- get_field(s, v3), cpu_env, m5, g_cc[es]);
+ get_field(s, v3), tcg_env, m5, g_cc[es]);
set_cc_static(s);
} else {
gen_gvec_3_ool(get_field(s, v1), get_field(s, v2),
if (extract32(m5, 0, 1)) {
gen_gvec_3_ptr(get_field(s, v1), get_field(s, v2),
- get_field(s, v3), cpu_env, m5, g_cc[es]);
+ get_field(s, v3), tcg_env, m5, g_cc[es]);
set_cc_static(s);
} else {
gen_gvec_3_ool(get_field(s, v1), get_field(s, v2),
if (extract32(m5, 0, 1)) {
gen_gvec_3_ptr(get_field(s, v1), get_field(s, v2),
- get_field(s, v3), cpu_env, m5, g_cc[es]);
+ get_field(s, v3), tcg_env, m5, g_cc[es]);
set_cc_static(s);
} else {
gen_gvec_3_ool(get_field(s, v1), get_field(s, v2),
if (extract32(m5, 0, 1)) {
gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2),
- cpu_env, 0, g_cc[es]);
+ tcg_env, 0, g_cc[es]);
set_cc_static(s);
} else {
gen_gvec_2_ool(get_field(s, v1), get_field(s, v2), 0,
if (extract32(m6, 2, 1)) {
gen_gvec_4_ptr(get_field(s, v1), get_field(s, v2),
get_field(s, v3), get_field(s, v4),
- cpu_env, m6, g_cc_rt[es]);
+ tcg_env, m6, g_cc_rt[es]);
} else {
gen_gvec_4_ptr(get_field(s, v1), get_field(s, v2),
get_field(s, v3), get_field(s, v4),
- cpu_env, m6, g_cc[es]);
+ tcg_env, m6, g_cc[es]);
}
set_cc_static(s);
} else {
gen_gvec_4_ptr(get_field(s, v1), get_field(s, v2),
get_field(s, v3), get_field(s, v4),
- cpu_env, 0, fns[es][zs]);
+ tcg_env, 0, fns[es][zs]);
set_cc_static(s);
return DISAS_NEXT;
}
}
gen_gvec_3_ptr(get_field(s, v1), get_field(s, v2),
- get_field(s, v3), cpu_env, m5, fn);
+ get_field(s, v3), tcg_env, m5, fn);
return DISAS_NEXT;
}
return DISAS_NORETURN;
}
- gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), cpu_env, 0, fn);
+ gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), tcg_env, 0, fn);
set_cc_static(s);
return DISAS_NEXT;
}
}
gen_gvec_3_ptr(get_field(s, v1), get_field(s, v2), get_field(s, v3),
- cpu_env, m5, fn);
+ tcg_env, m5, fn);
if (cs) {
set_cc_static(s);
}
return DISAS_NORETURN;
}
- gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), cpu_env,
+ gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), tcg_env,
deposit32(m4, 4, 4, erm), fn);
return DISAS_NEXT;
}
return DISAS_NORETURN;
}
- gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), cpu_env, m4, fn);
+ gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), tcg_env, m4, fn);
return DISAS_NEXT;
}
}
gen_gvec_3_ptr(get_field(s, v1), get_field(s, v2), get_field(s, v3),
- cpu_env, deposit32(m5, 4, 4, m6), fn);
+ tcg_env, deposit32(m5, 4, 4, m6), fn);
return DISAS_NEXT;
}
}
gen_gvec_4_ptr(get_field(s, v1), get_field(s, v2),
- get_field(s, v3), get_field(s, v4), cpu_env, m5, fn);
+ get_field(s, v3), get_field(s, v4), tcg_env, m5, fn);
return DISAS_NEXT;
}
return DISAS_NORETURN;
}
- gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), cpu_env, m4, fn);
+ gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), tcg_env, m4, fn);
return DISAS_NEXT;
}
return DISAS_NORETURN;
}
- gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), cpu_env,
+ gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), tcg_env,
deposit32(m5, 4, 12, i3), fn);
set_cc_static(s);
return DISAS_NEXT;
};
for (i = 0; i < 24; i++) {
- cpu_gregs[i] = tcg_global_mem_new_i32(cpu_env,
+ cpu_gregs[i] = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUSH4State, gregs[i]),
gregnames[i]);
}
memcpy(cpu_gregs + 24, cpu_gregs + 8, 8 * sizeof(TCGv));
- cpu_pc = tcg_global_mem_new_i32(cpu_env,
+ cpu_pc = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUSH4State, pc), "PC");
- cpu_sr = tcg_global_mem_new_i32(cpu_env,
+ cpu_sr = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUSH4State, sr), "SR");
- cpu_sr_m = tcg_global_mem_new_i32(cpu_env,
+ cpu_sr_m = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUSH4State, sr_m), "SR_M");
- cpu_sr_q = tcg_global_mem_new_i32(cpu_env,
+ cpu_sr_q = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUSH4State, sr_q), "SR_Q");
- cpu_sr_t = tcg_global_mem_new_i32(cpu_env,
+ cpu_sr_t = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUSH4State, sr_t), "SR_T");
- cpu_ssr = tcg_global_mem_new_i32(cpu_env,
+ cpu_ssr = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUSH4State, ssr), "SSR");
- cpu_spc = tcg_global_mem_new_i32(cpu_env,
+ cpu_spc = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUSH4State, spc), "SPC");
- cpu_gbr = tcg_global_mem_new_i32(cpu_env,
+ cpu_gbr = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUSH4State, gbr), "GBR");
- cpu_vbr = tcg_global_mem_new_i32(cpu_env,
+ cpu_vbr = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUSH4State, vbr), "VBR");
- cpu_sgr = tcg_global_mem_new_i32(cpu_env,
+ cpu_sgr = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUSH4State, sgr), "SGR");
- cpu_dbr = tcg_global_mem_new_i32(cpu_env,
+ cpu_dbr = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUSH4State, dbr), "DBR");
- cpu_mach = tcg_global_mem_new_i32(cpu_env,
+ cpu_mach = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUSH4State, mach), "MACH");
- cpu_macl = tcg_global_mem_new_i32(cpu_env,
+ cpu_macl = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUSH4State, macl), "MACL");
- cpu_pr = tcg_global_mem_new_i32(cpu_env,
+ cpu_pr = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUSH4State, pr), "PR");
- cpu_fpscr = tcg_global_mem_new_i32(cpu_env,
+ cpu_fpscr = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUSH4State, fpscr), "FPSCR");
- cpu_fpul = tcg_global_mem_new_i32(cpu_env,
+ cpu_fpul = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUSH4State, fpul), "FPUL");
- cpu_flags = tcg_global_mem_new_i32(cpu_env,
+ cpu_flags = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUSH4State, flags), "_flags_");
- cpu_delayed_pc = tcg_global_mem_new_i32(cpu_env,
+ cpu_delayed_pc = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUSH4State, delayed_pc),
"_delayed_pc_");
- cpu_delayed_cond = tcg_global_mem_new_i32(cpu_env,
+ cpu_delayed_cond = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUSH4State,
delayed_cond),
"_delayed_cond_");
- cpu_lock_addr = tcg_global_mem_new_i32(cpu_env,
+ cpu_lock_addr = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUSH4State, lock_addr),
"_lock_addr_");
- cpu_lock_value = tcg_global_mem_new_i32(cpu_env,
+ cpu_lock_value = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUSH4State, lock_value),
"_lock_value_");
for (i = 0; i < 32; i++)
- cpu_fregs[i] = tcg_global_mem_new_i32(cpu_env,
+ cpu_fregs[i] = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUSH4State, fregs[i]),
fregnames[i]);
}
if (opcode != 0x0093 /* ocbi */
&& opcode != 0x00c3 /* movca.l */)
{
- gen_helper_discard_movcal_backup(cpu_env);
+ gen_helper_discard_movcal_backup(tcg_env);
ctx->has_movcal = 0;
}
}
return;
case 0x0038: /* ldtlb */
CHECK_PRIVILEGED
- gen_helper_ldtlb(cpu_env);
+ gen_helper_ldtlb(tcg_env);
return;
case 0x002b: /* rte */
CHECK_PRIVILEGED
case 0x001b: /* sleep */
CHECK_PRIVILEGED
tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next + 2);
- gen_helper_sleep(cpu_env);
+ gen_helper_sleep(tcg_env);
return;
}
arg1 = tcg_temp_new();
tcg_gen_qemu_ld_i32(arg1, REG(B11_8), ctx->memidx,
MO_TESL | MO_ALIGN);
- gen_helper_macl(cpu_env, arg0, arg1);
+ gen_helper_macl(tcg_env, arg0, arg1);
tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
}
arg1 = tcg_temp_new();
tcg_gen_qemu_ld_i32(arg1, REG(B11_8), ctx->memidx,
MO_TESL | MO_ALIGN);
- gen_helper_macw(cpu_env, arg0, arg1);
+ gen_helper_macw(tcg_env, arg0, arg1);
tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 2);
tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2);
}
gen_load_fpr64(ctx, fp1, B7_4);
switch (ctx->opcode & 0xf00f) {
case 0xf000: /* fadd Rm,Rn */
- gen_helper_fadd_DT(fp0, cpu_env, fp0, fp1);
+ gen_helper_fadd_DT(fp0, tcg_env, fp0, fp1);
break;
case 0xf001: /* fsub Rm,Rn */
- gen_helper_fsub_DT(fp0, cpu_env, fp0, fp1);
+ gen_helper_fsub_DT(fp0, tcg_env, fp0, fp1);
break;
case 0xf002: /* fmul Rm,Rn */
- gen_helper_fmul_DT(fp0, cpu_env, fp0, fp1);
+ gen_helper_fmul_DT(fp0, tcg_env, fp0, fp1);
break;
case 0xf003: /* fdiv Rm,Rn */
- gen_helper_fdiv_DT(fp0, cpu_env, fp0, fp1);
+ gen_helper_fdiv_DT(fp0, tcg_env, fp0, fp1);
break;
case 0xf004: /* fcmp/eq Rm,Rn */
- gen_helper_fcmp_eq_DT(cpu_sr_t, cpu_env, fp0, fp1);
+ gen_helper_fcmp_eq_DT(cpu_sr_t, tcg_env, fp0, fp1);
return;
case 0xf005: /* fcmp/gt Rm,Rn */
- gen_helper_fcmp_gt_DT(cpu_sr_t, cpu_env, fp0, fp1);
+ gen_helper_fcmp_gt_DT(cpu_sr_t, tcg_env, fp0, fp1);
return;
}
gen_store_fpr64(ctx, fp0, B11_8);
} else {
switch (ctx->opcode & 0xf00f) {
case 0xf000: /* fadd Rm,Rn */
- gen_helper_fadd_FT(FREG(B11_8), cpu_env,
+ gen_helper_fadd_FT(FREG(B11_8), tcg_env,
FREG(B11_8), FREG(B7_4));
break;
case 0xf001: /* fsub Rm,Rn */
- gen_helper_fsub_FT(FREG(B11_8), cpu_env,
+ gen_helper_fsub_FT(FREG(B11_8), tcg_env,
FREG(B11_8), FREG(B7_4));
break;
case 0xf002: /* fmul Rm,Rn */
- gen_helper_fmul_FT(FREG(B11_8), cpu_env,
+ gen_helper_fmul_FT(FREG(B11_8), tcg_env,
FREG(B11_8), FREG(B7_4));
break;
case 0xf003: /* fdiv Rm,Rn */
- gen_helper_fdiv_FT(FREG(B11_8), cpu_env,
+ gen_helper_fdiv_FT(FREG(B11_8), tcg_env,
FREG(B11_8), FREG(B7_4));
break;
case 0xf004: /* fcmp/eq Rm,Rn */
- gen_helper_fcmp_eq_FT(cpu_sr_t, cpu_env,
+ gen_helper_fcmp_eq_FT(cpu_sr_t, tcg_env,
FREG(B11_8), FREG(B7_4));
return;
case 0xf005: /* fcmp/gt Rm,Rn */
- gen_helper_fcmp_gt_FT(cpu_sr_t, cpu_env,
+ gen_helper_fcmp_gt_FT(cpu_sr_t, tcg_env,
FREG(B11_8), FREG(B7_4));
return;
}
case 0xf00e: /* fmac FR0,RM,Rn */
CHECK_FPU_ENABLED
CHECK_FPSCR_PR_0
- gen_helper_fmac_FT(FREG(B11_8), cpu_env,
+ gen_helper_fmac_FT(FREG(B11_8), tcg_env,
FREG(0), FREG(B7_4), FREG(B11_8));
return;
}
CHECK_NOT_DELAY_SLOT
gen_save_cpu_state(ctx, true);
imm = tcg_constant_i32(B7_0);
- gen_helper_trapa(cpu_env, imm);
+ gen_helper_trapa(tcg_env, imm);
ctx->base.is_jmp = DISAS_NORETURN;
}
return;
LDST(fpul, 0x405a, 0x4056, 0x005a, 0x4052, {CHECK_FPU_ENABLED})
case 0x406a: /* lds Rm,FPSCR */
CHECK_FPU_ENABLED
- gen_helper_ld_fpscr(cpu_env, REG(B11_8));
+ gen_helper_ld_fpscr(tcg_env, REG(B11_8));
ctx->base.is_jmp = DISAS_STOP;
return;
case 0x4066: /* lds.l @Rm+,FPSCR */
tcg_gen_qemu_ld_i32(addr, REG(B11_8), ctx->memidx,
MO_TESL | MO_ALIGN);
tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
- gen_helper_ld_fpscr(cpu_env, addr);
+ gen_helper_ld_fpscr(tcg_env, addr);
ctx->base.is_jmp = DISAS_STOP;
}
return;
TCGv val = tcg_temp_new();
tcg_gen_qemu_ld_i32(val, REG(B11_8), ctx->memidx,
MO_TEUL | MO_ALIGN);
- gen_helper_movcal(cpu_env, REG(B11_8), val);
+ gen_helper_movcal(tcg_env, REG(B11_8), val);
tcg_gen_qemu_st_i32(REG(0), REG(B11_8), ctx->memidx,
MO_TEUL | MO_ALIGN);
}
return;
case 0x0093: /* ocbi @Rn */
{
- gen_helper_ocbi(cpu_env, REG(B11_8));
+ gen_helper_ocbi(tcg_env, REG(B11_8));
}
return;
case 0x00a3: /* ocbp @Rn */
goto do_illegal;
}
fp = tcg_temp_new_i64();
- gen_helper_float_DT(fp, cpu_env, cpu_fpul);
+ gen_helper_float_DT(fp, tcg_env, cpu_fpul);
gen_store_fpr64(ctx, fp, B11_8);
}
else {
- gen_helper_float_FT(FREG(B11_8), cpu_env, cpu_fpul);
+ gen_helper_float_FT(FREG(B11_8), tcg_env, cpu_fpul);
}
return;
case 0xf03d: /* ftrc FRm/DRm,FPUL - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
}
fp = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp, B11_8);
- gen_helper_ftrc_DT(cpu_fpul, cpu_env, fp);
+ gen_helper_ftrc_DT(cpu_fpul, tcg_env, fp);
}
else {
- gen_helper_ftrc_FT(cpu_fpul, cpu_env, FREG(B11_8));
+ gen_helper_ftrc_FT(cpu_fpul, tcg_env, FREG(B11_8));
}
return;
case 0xf04d: /* fneg FRn/DRn - FPSCR: Nothing */
}
TCGv_i64 fp = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp, B11_8);
- gen_helper_fsqrt_DT(fp, cpu_env, fp);
+ gen_helper_fsqrt_DT(fp, tcg_env, fp);
gen_store_fpr64(ctx, fp, B11_8);
} else {
- gen_helper_fsqrt_FT(FREG(B11_8), cpu_env, FREG(B11_8));
+ gen_helper_fsqrt_FT(FREG(B11_8), tcg_env, FREG(B11_8));
}
return;
case 0xf07d: /* fsrra FRn */
CHECK_FPU_ENABLED
CHECK_FPSCR_PR_0
- gen_helper_fsrra_FT(FREG(B11_8), cpu_env, FREG(B11_8));
+ gen_helper_fsrra_FT(FREG(B11_8), tcg_env, FREG(B11_8));
break;
case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */
CHECK_FPU_ENABLED
CHECK_FPU_ENABLED
{
TCGv_i64 fp = tcg_temp_new_i64();
- gen_helper_fcnvsd_FT_DT(fp, cpu_env, cpu_fpul);
+ gen_helper_fcnvsd_FT_DT(fp, tcg_env, cpu_fpul);
gen_store_fpr64(ctx, fp, B11_8);
}
return;
{
TCGv_i64 fp = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp, B11_8);
- gen_helper_fcnvds_DT_FT(cpu_fpul, cpu_env, fp);
+ gen_helper_fcnvds_DT_FT(cpu_fpul, tcg_env, fp);
}
return;
case 0xf0ed: /* fipr FVm,FVn */
{
TCGv m = tcg_constant_i32((ctx->opcode >> 8) & 3);
TCGv n = tcg_constant_i32((ctx->opcode >> 10) & 3);
- gen_helper_fipr(cpu_env, m, n);
+ gen_helper_fipr(tcg_env, m, n);
return;
}
break;
goto do_illegal;
}
TCGv n = tcg_constant_i32((ctx->opcode >> 10) & 3);
- gen_helper_ftrv(cpu_env, n);
+ gen_helper_ftrv(tcg_env, n);
return;
}
break;
if (ctx->envflags & TB_FLAG_DELAY_SLOT_MASK) {
do_illegal_slot:
gen_save_cpu_state(ctx, true);
- gen_helper_raise_slot_illegal_instruction(cpu_env);
+ gen_helper_raise_slot_illegal_instruction(tcg_env);
} else {
gen_save_cpu_state(ctx, true);
- gen_helper_raise_illegal_instruction(cpu_env);
+ gen_helper_raise_illegal_instruction(tcg_env);
}
ctx->base.is_jmp = DISAS_NORETURN;
return;
do_fpu_disabled:
gen_save_cpu_state(ctx, true);
if (ctx->envflags & TB_FLAG_DELAY_SLOT_MASK) {
- gen_helper_raise_slot_fpu_disable(cpu_env);
+ gen_helper_raise_slot_fpu_disable(tcg_env);
} else {
- gen_helper_raise_fpu_disable(cpu_env);
+ gen_helper_raise_fpu_disable(tcg_env);
}
ctx->base.is_jmp = DISAS_NORETURN;
return;
cpu_exec_step_atomic holding the exclusive lock. */
ctx->envflags |= TB_FLAG_GUSA_EXCLUSIVE;
gen_save_cpu_state(ctx, false);
- gen_helper_exclusive(cpu_env);
+ gen_helper_exclusive(tcg_env);
ctx->base.is_jmp = DISAS_NORETURN;
/* We're not executing an instruction, but we must report one for the
static void gen_op_load_fpr_QT0(unsigned int src)
{
- tcg_gen_st_i64(cpu_fpr[src / 2], cpu_env, offsetof(CPUSPARCState, qt0) +
+ tcg_gen_st_i64(cpu_fpr[src / 2], tcg_env, offsetof(CPUSPARCState, qt0) +
offsetof(CPU_QuadU, ll.upper));
- tcg_gen_st_i64(cpu_fpr[src/2 + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
+ tcg_gen_st_i64(cpu_fpr[src/2 + 1], tcg_env, offsetof(CPUSPARCState, qt0) +
offsetof(CPU_QuadU, ll.lower));
}
static void gen_op_load_fpr_QT1(unsigned int src)
{
- tcg_gen_st_i64(cpu_fpr[src / 2], cpu_env, offsetof(CPUSPARCState, qt1) +
+ tcg_gen_st_i64(cpu_fpr[src / 2], tcg_env, offsetof(CPUSPARCState, qt1) +
offsetof(CPU_QuadU, ll.upper));
- tcg_gen_st_i64(cpu_fpr[src/2 + 1], cpu_env, offsetof(CPUSPARCState, qt1) +
+ tcg_gen_st_i64(cpu_fpr[src/2 + 1], tcg_env, offsetof(CPUSPARCState, qt1) +
offsetof(CPU_QuadU, ll.lower));
}
static void gen_op_store_QT0_fpr(unsigned int dst)
{
- tcg_gen_ld_i64(cpu_fpr[dst / 2], cpu_env, offsetof(CPUSPARCState, qt0) +
+ tcg_gen_ld_i64(cpu_fpr[dst / 2], tcg_env, offsetof(CPUSPARCState, qt0) +
offsetof(CPU_QuadU, ll.upper));
- tcg_gen_ld_i64(cpu_fpr[dst/2 + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
+ tcg_gen_ld_i64(cpu_fpr[dst/2 + 1], tcg_env, offsetof(CPUSPARCState, qt0) +
offsetof(CPU_QuadU, ll.lower));
}
default:
/* We need external help to produce the carry. */
carry_32 = tcg_temp_new_i32();
- gen_helper_compute_C_icc(carry_32, cpu_env);
+ gen_helper_compute_C_icc(carry_32, tcg_env);
break;
}
default:
/* We need external help to produce the carry. */
carry_32 = tcg_temp_new_i32();
- gen_helper_compute_C_icc(carry_32, cpu_env);
+ gen_helper_compute_C_icc(carry_32, tcg_env);
break;
}
{
if (dc->cc_op != CC_OP_FLAGS) {
dc->cc_op = CC_OP_FLAGS;
- gen_helper_compute_psr(cpu_env);
+ gen_helper_compute_psr(tcg_env);
}
}
static void gen_exception(DisasContext *dc, int which)
{
save_state(dc);
- gen_helper_raise_exception(cpu_env, tcg_constant_i32(which));
+ gen_helper_raise_exception(tcg_env, tcg_constant_i32(which));
dc->base.is_jmp = DISAS_NORETURN;
}
static void gen_check_align(TCGv addr, int mask)
{
- gen_helper_check_align(cpu_env, addr, tcg_constant_i32(mask));
+ gen_helper_check_align(tcg_env, addr, tcg_constant_i32(mask));
}
static void gen_mov_pc_npc(DisasContext *dc)
default:
do_dynamic:
- gen_helper_compute_psr(cpu_env);
+ gen_helper_compute_psr(tcg_env);
dc->cc_op = CC_OP_FLAGS;
/* FALLTHRU */
{
switch (fccno) {
case 0:
- gen_helper_fcmps(cpu_fsr, cpu_env, r_rs1, r_rs2);
+ gen_helper_fcmps(cpu_fsr, tcg_env, r_rs1, r_rs2);
break;
case 1:
- gen_helper_fcmps_fcc1(cpu_fsr, cpu_env, r_rs1, r_rs2);
+ gen_helper_fcmps_fcc1(cpu_fsr, tcg_env, r_rs1, r_rs2);
break;
case 2:
- gen_helper_fcmps_fcc2(cpu_fsr, cpu_env, r_rs1, r_rs2);
+ gen_helper_fcmps_fcc2(cpu_fsr, tcg_env, r_rs1, r_rs2);
break;
case 3:
- gen_helper_fcmps_fcc3(cpu_fsr, cpu_env, r_rs1, r_rs2);
+ gen_helper_fcmps_fcc3(cpu_fsr, tcg_env, r_rs1, r_rs2);
break;
}
}
{
switch (fccno) {
case 0:
- gen_helper_fcmpd(cpu_fsr, cpu_env, r_rs1, r_rs2);
+ gen_helper_fcmpd(cpu_fsr, tcg_env, r_rs1, r_rs2);
break;
case 1:
- gen_helper_fcmpd_fcc1(cpu_fsr, cpu_env, r_rs1, r_rs2);
+ gen_helper_fcmpd_fcc1(cpu_fsr, tcg_env, r_rs1, r_rs2);
break;
case 2:
- gen_helper_fcmpd_fcc2(cpu_fsr, cpu_env, r_rs1, r_rs2);
+ gen_helper_fcmpd_fcc2(cpu_fsr, tcg_env, r_rs1, r_rs2);
break;
case 3:
- gen_helper_fcmpd_fcc3(cpu_fsr, cpu_env, r_rs1, r_rs2);
+ gen_helper_fcmpd_fcc3(cpu_fsr, tcg_env, r_rs1, r_rs2);
break;
}
}
{
switch (fccno) {
case 0:
- gen_helper_fcmpq(cpu_fsr, cpu_env);
+ gen_helper_fcmpq(cpu_fsr, tcg_env);
break;
case 1:
- gen_helper_fcmpq_fcc1(cpu_fsr, cpu_env);
+ gen_helper_fcmpq_fcc1(cpu_fsr, tcg_env);
break;
case 2:
- gen_helper_fcmpq_fcc2(cpu_fsr, cpu_env);
+ gen_helper_fcmpq_fcc2(cpu_fsr, tcg_env);
break;
case 3:
- gen_helper_fcmpq_fcc3(cpu_fsr, cpu_env);
+ gen_helper_fcmpq_fcc3(cpu_fsr, tcg_env);
break;
}
}
{
switch (fccno) {
case 0:
- gen_helper_fcmpes(cpu_fsr, cpu_env, r_rs1, r_rs2);
+ gen_helper_fcmpes(cpu_fsr, tcg_env, r_rs1, r_rs2);
break;
case 1:
- gen_helper_fcmpes_fcc1(cpu_fsr, cpu_env, r_rs1, r_rs2);
+ gen_helper_fcmpes_fcc1(cpu_fsr, tcg_env, r_rs1, r_rs2);
break;
case 2:
- gen_helper_fcmpes_fcc2(cpu_fsr, cpu_env, r_rs1, r_rs2);
+ gen_helper_fcmpes_fcc2(cpu_fsr, tcg_env, r_rs1, r_rs2);
break;
case 3:
- gen_helper_fcmpes_fcc3(cpu_fsr, cpu_env, r_rs1, r_rs2);
+ gen_helper_fcmpes_fcc3(cpu_fsr, tcg_env, r_rs1, r_rs2);
break;
}
}
{
switch (fccno) {
case 0:
- gen_helper_fcmped(cpu_fsr, cpu_env, r_rs1, r_rs2);
+ gen_helper_fcmped(cpu_fsr, tcg_env, r_rs1, r_rs2);
break;
case 1:
- gen_helper_fcmped_fcc1(cpu_fsr, cpu_env, r_rs1, r_rs2);
+ gen_helper_fcmped_fcc1(cpu_fsr, tcg_env, r_rs1, r_rs2);
break;
case 2:
- gen_helper_fcmped_fcc2(cpu_fsr, cpu_env, r_rs1, r_rs2);
+ gen_helper_fcmped_fcc2(cpu_fsr, tcg_env, r_rs1, r_rs2);
break;
case 3:
- gen_helper_fcmped_fcc3(cpu_fsr, cpu_env, r_rs1, r_rs2);
+ gen_helper_fcmped_fcc3(cpu_fsr, tcg_env, r_rs1, r_rs2);
break;
}
}
{
switch (fccno) {
case 0:
- gen_helper_fcmpeq(cpu_fsr, cpu_env);
+ gen_helper_fcmpeq(cpu_fsr, tcg_env);
break;
case 1:
- gen_helper_fcmpeq_fcc1(cpu_fsr, cpu_env);
+ gen_helper_fcmpeq_fcc1(cpu_fsr, tcg_env);
break;
case 2:
- gen_helper_fcmpeq_fcc2(cpu_fsr, cpu_env);
+ gen_helper_fcmpeq_fcc2(cpu_fsr, tcg_env);
break;
case 3:
- gen_helper_fcmpeq_fcc3(cpu_fsr, cpu_env);
+ gen_helper_fcmpeq_fcc3(cpu_fsr, tcg_env);
break;
}
}
static void gen_op_fcmps(int fccno, TCGv r_rs1, TCGv r_rs2)
{
- gen_helper_fcmps(cpu_fsr, cpu_env, r_rs1, r_rs2);
+ gen_helper_fcmps(cpu_fsr, tcg_env, r_rs1, r_rs2);
}
static void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
{
- gen_helper_fcmpd(cpu_fsr, cpu_env, r_rs1, r_rs2);
+ gen_helper_fcmpd(cpu_fsr, tcg_env, r_rs1, r_rs2);
}
static void gen_op_fcmpq(int fccno)
{
- gen_helper_fcmpq(cpu_fsr, cpu_env);
+ gen_helper_fcmpq(cpu_fsr, tcg_env);
}
static void gen_op_fcmpes(int fccno, TCGv r_rs1, TCGv r_rs2)
{
- gen_helper_fcmpes(cpu_fsr, cpu_env, r_rs1, r_rs2);
+ gen_helper_fcmpes(cpu_fsr, tcg_env, r_rs1, r_rs2);
}
static void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
{
- gen_helper_fcmped(cpu_fsr, cpu_env, r_rs1, r_rs2);
+ gen_helper_fcmped(cpu_fsr, tcg_env, r_rs1, r_rs2);
}
static void gen_op_fcmpeq(int fccno)
{
- gen_helper_fcmpeq(cpu_fsr, cpu_env);
+ gen_helper_fcmpeq(cpu_fsr, tcg_env);
}
#endif
src = gen_load_fpr_F(dc, rs);
dst = gen_dest_fpr_F(dc);
- gen(dst, cpu_env, src);
- gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
+ gen(dst, tcg_env, src);
+ gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
gen_store_fpr_F(dc, rd, dst);
}
src2 = gen_load_fpr_F(dc, rs2);
dst = gen_dest_fpr_F(dc);
- gen(dst, cpu_env, src1, src2);
- gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
+ gen(dst, tcg_env, src1, src2);
+ gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
gen_store_fpr_F(dc, rd, dst);
}
src = gen_load_fpr_D(dc, rs);
dst = gen_dest_fpr_D(dc, rd);
- gen(dst, cpu_env, src);
- gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
+ gen(dst, tcg_env, src);
+ gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
gen_store_fpr_D(dc, rd, dst);
}
src2 = gen_load_fpr_D(dc, rs2);
dst = gen_dest_fpr_D(dc, rd);
- gen(dst, cpu_env, src1, src2);
- gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
+ gen(dst, tcg_env, src1, src2);
+ gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
gen_store_fpr_D(dc, rd, dst);
}
{
gen_op_load_fpr_QT1(QFPREG(rs));
- gen(cpu_env);
- gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
+ gen(tcg_env);
+ gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
gen_op_store_QT0_fpr(QFPREG(rd));
gen_update_fprs_dirty(dc, QFPREG(rd));
{
gen_op_load_fpr_QT1(QFPREG(rs));
- gen(cpu_env);
+ gen(tcg_env);
gen_op_store_QT0_fpr(QFPREG(rd));
gen_update_fprs_dirty(dc, QFPREG(rd));
gen_op_load_fpr_QT0(QFPREG(rs1));
gen_op_load_fpr_QT1(QFPREG(rs2));
- gen(cpu_env);
- gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
+ gen(tcg_env);
+ gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
gen_op_store_QT0_fpr(QFPREG(rd));
gen_update_fprs_dirty(dc, QFPREG(rd));
src2 = gen_load_fpr_F(dc, rs2);
dst = gen_dest_fpr_D(dc, rd);
- gen(dst, cpu_env, src1, src2);
- gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
+ gen(dst, tcg_env, src1, src2);
+ gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
gen_store_fpr_D(dc, rd, dst);
}
src1 = gen_load_fpr_D(dc, rs1);
src2 = gen_load_fpr_D(dc, rs2);
- gen(cpu_env, src1, src2);
- gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
+ gen(tcg_env, src1, src2);
+ gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
gen_op_store_QT0_fpr(QFPREG(rd));
gen_update_fprs_dirty(dc, QFPREG(rd));
src = gen_load_fpr_F(dc, rs);
dst = gen_dest_fpr_D(dc, rd);
- gen(dst, cpu_env, src);
- gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
+ gen(dst, tcg_env, src);
+ gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
gen_store_fpr_D(dc, rd, dst);
}
src = gen_load_fpr_F(dc, rs);
dst = gen_dest_fpr_D(dc, rd);
- gen(dst, cpu_env, src);
+ gen(dst, tcg_env, src);
gen_store_fpr_D(dc, rd, dst);
}
src = gen_load_fpr_D(dc, rs);
dst = gen_dest_fpr_F(dc);
- gen(dst, cpu_env, src);
- gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
+ gen(dst, tcg_env, src);
+ gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
gen_store_fpr_F(dc, rd, dst);
}
gen_op_load_fpr_QT1(QFPREG(rs));
dst = gen_dest_fpr_F(dc);
- gen(dst, cpu_env);
- gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
+ gen(dst, tcg_env);
+ gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
gen_store_fpr_F(dc, rd, dst);
}
gen_op_load_fpr_QT1(QFPREG(rs));
dst = gen_dest_fpr_D(dc, rd);
- gen(dst, cpu_env);
- gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
+ gen(dst, tcg_env);
+ gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
gen_store_fpr_D(dc, rd, dst);
}
src = gen_load_fpr_F(dc, rs);
- gen(cpu_env, src);
+ gen(tcg_env, src);
gen_op_store_QT0_fpr(QFPREG(rd));
gen_update_fprs_dirty(dc, QFPREG(rd));
src = gen_load_fpr_D(dc, rs);
- gen(cpu_env, src);
+ gen(tcg_env, src);
gen_op_store_QT0_fpr(QFPREG(rd));
gen_update_fprs_dirty(dc, QFPREG(rd));
save_state(dc);
#ifdef TARGET_SPARC64
- gen_helper_ld_asi(dst, cpu_env, addr, r_asi, r_mop);
+ gen_helper_ld_asi(dst, tcg_env, addr, r_asi, r_mop);
#else
{
TCGv_i64 t64 = tcg_temp_new_i64();
- gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_mop);
+ gen_helper_ld_asi(t64, tcg_env, addr, r_asi, r_mop);
tcg_gen_trunc_i64_tl(dst, t64);
}
#endif
save_state(dc);
#ifdef TARGET_SPARC64
- gen_helper_st_asi(cpu_env, addr, src, r_asi, r_mop);
+ gen_helper_st_asi(tcg_env, addr, src, r_asi, r_mop);
#else
{
TCGv_i64 t64 = tcg_temp_new_i64();
tcg_gen_extu_tl_i64(t64, src);
- gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_mop);
+ gen_helper_st_asi(tcg_env, addr, t64, r_asi, r_mop);
}
#endif
/* ??? In theory, this should be raise DAE_invalid_asi.
But the SS-20 roms do ldstuba [%l0] #ASI_M_CTL, %o1. */
if (tb_cflags(dc->base.tb) & CF_PARALLEL) {
- gen_helper_exit_atomic(cpu_env);
+ gen_helper_exit_atomic(tcg_env);
} else {
TCGv_i32 r_asi = tcg_constant_i32(da.asi);
TCGv_i32 r_mop = tcg_constant_i32(MO_UB);
save_state(dc);
t64 = tcg_temp_new_i64();
- gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_mop);
+ gen_helper_ld_asi(t64, tcg_env, addr, r_asi, r_mop);
s64 = tcg_constant_i64(0xff);
- gen_helper_st_asi(cpu_env, addr, s64, r_asi, r_mop);
+ gen_helper_st_asi(tcg_env, addr, s64, r_asi, r_mop);
tcg_gen_trunc_i64_tl(dst, t64);
switch (size) {
case 4:
d64 = tcg_temp_new_i64();
- gen_helper_ld_asi(d64, cpu_env, addr, r_asi, r_mop);
+ gen_helper_ld_asi(d64, tcg_env, addr, r_asi, r_mop);
d32 = gen_dest_fpr_F(dc);
tcg_gen_extrl_i64_i32(d32, d64);
gen_store_fpr_F(dc, rd, d32);
break;
case 8:
- gen_helper_ld_asi(cpu_fpr[rd / 2], cpu_env, addr, r_asi, r_mop);
+ gen_helper_ld_asi(cpu_fpr[rd / 2], tcg_env, addr, r_asi, r_mop);
break;
case 16:
d64 = tcg_temp_new_i64();
- gen_helper_ld_asi(d64, cpu_env, addr, r_asi, r_mop);
+ gen_helper_ld_asi(d64, tcg_env, addr, r_asi, r_mop);
tcg_gen_addi_tl(addr, addr, 8);
- gen_helper_ld_asi(cpu_fpr[rd/2+1], cpu_env, addr, r_asi, r_mop);
+ gen_helper_ld_asi(cpu_fpr[rd/2+1], tcg_env, addr, r_asi, r_mop);
tcg_gen_mov_i64(cpu_fpr[rd / 2], d64);
break;
default:
TCGv_i64 tmp = tcg_temp_new_i64();
save_state(dc);
- gen_helper_ld_asi(tmp, cpu_env, addr, r_asi, r_mop);
+ gen_helper_ld_asi(tmp, tcg_env, addr, r_asi, r_mop);
/* See above. */
if ((da.memop & MO_BSWAP) == MO_TE) {
}
save_state(dc);
- gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_mop);
+ gen_helper_st_asi(tcg_env, addr, t64, r_asi, r_mop);
}
break;
}
TCGv_i32 r_mop = tcg_constant_i32(MO_UQ);
save_state(dc);
- gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_mop);
+ gen_helper_ld_asi(t64, tcg_env, addr, r_asi, r_mop);
}
break;
}
TCGv_i32 r_mop = tcg_constant_i32(MO_UQ);
save_state(dc);
- gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_mop);
+ gen_helper_st_asi(tcg_env, addr, t64, r_asi, r_mop);
}
break;
}
}
#ifndef CONFIG_USER_ONLY
-static void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr, TCGv_env cpu_env)
+static void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr, TCGv_env tcg_env)
{
TCGv_i32 r_tl = tcg_temp_new_i32();
/* load env->tl into r_tl */
- tcg_gen_ld_i32(r_tl, cpu_env, offsetof(CPUSPARCState, tl));
+ tcg_gen_ld_i32(r_tl, tcg_env, offsetof(CPUSPARCState, tl));
/* tl = [0 ... MAXTL_MASK] where MAXTL_MASK must be power of 2 */
tcg_gen_andi_i32(r_tl, r_tl, MAXTL_MASK);
/* calculate offset to current trap state from env->ts, reuse r_tl */
tcg_gen_muli_i32(r_tl, r_tl, sizeof (trap_state));
- tcg_gen_addi_ptr(r_tsptr, cpu_env, offsetof(CPUSPARCState, ts));
+ tcg_gen_addi_ptr(r_tsptr, tcg_env, offsetof(CPUSPARCState, ts));
/* tsptr = env->ts[env->tl & MAXTL_MASK] */
{
tcg_gen_addi_i32(trap, trap, TT_TRAP);
}
- gen_helper_raise_exception(cpu_env, trap);
+ gen_helper_raise_exception(tcg_env, trap);
if (cond == 8) {
/* An unconditional trap ends the TB. */
#ifdef TARGET_SPARC64
case 0x2: /* V9 rdccr */
update_psr(dc);
- gen_helper_rdccr(cpu_dst, cpu_env);
+ gen_helper_rdccr(cpu_dst, tcg_env);
gen_store_gpr(dc, rd, cpu_dst);
break;
case 0x3: /* V9 rdasi */
r_tickptr = tcg_temp_new_ptr();
r_const = tcg_constant_i32(dc->mem_idx);
- tcg_gen_ld_ptr(r_tickptr, cpu_env,
+ tcg_gen_ld_ptr(r_tickptr, tcg_env,
offsetof(CPUSPARCState, tick));
if (translator_io_start(&dc->base)) {
dc->base.is_jmp = DISAS_EXIT;
}
- gen_helper_tick_get_count(cpu_dst, cpu_env, r_tickptr,
+ gen_helper_tick_get_count(cpu_dst, tcg_env, r_tickptr,
r_const);
gen_store_gpr(dc, rd, cpu_dst);
}
gen_store_gpr(dc, rd, cpu_gsr);
break;
case 0x16: /* Softint */
- tcg_gen_ld32s_tl(cpu_dst, cpu_env,
+ tcg_gen_ld32s_tl(cpu_dst, tcg_env,
offsetof(CPUSPARCState, softint));
gen_store_gpr(dc, rd, cpu_dst);
break;
r_tickptr = tcg_temp_new_ptr();
r_const = tcg_constant_i32(dc->mem_idx);
- tcg_gen_ld_ptr(r_tickptr, cpu_env,
+ tcg_gen_ld_ptr(r_tickptr, tcg_env,
offsetof(CPUSPARCState, stick));
if (translator_io_start(&dc->base)) {
dc->base.is_jmp = DISAS_EXIT;
}
- gen_helper_tick_get_count(cpu_dst, cpu_env, r_tickptr,
+ gen_helper_tick_get_count(cpu_dst, tcg_env, r_tickptr,
r_const);
gen_store_gpr(dc, rd, cpu_dst);
}
goto priv_insn;
}
update_psr(dc);
- gen_helper_rdpsr(cpu_dst, cpu_env);
+ gen_helper_rdpsr(cpu_dst, tcg_env);
#else
CHECK_IU_FEATURE(dc, HYPV);
if (!hypervisor(dc))
rs1 = GET_FIELD(insn, 13, 17);
switch (rs1) {
case 0: // hpstate
- tcg_gen_ld_i64(cpu_dst, cpu_env,
+ tcg_gen_ld_i64(cpu_dst, tcg_env,
offsetof(CPUSPARCState, hpstate));
break;
case 1: // htstate
TCGv_ptr r_tsptr;
r_tsptr = tcg_temp_new_ptr();
- gen_load_trap_state_at_tl(r_tsptr, cpu_env);
+ gen_load_trap_state_at_tl(r_tsptr, tcg_env);
tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
offsetof(trap_state, tpc));
}
TCGv_ptr r_tsptr;
r_tsptr = tcg_temp_new_ptr();
- gen_load_trap_state_at_tl(r_tsptr, cpu_env);
+ gen_load_trap_state_at_tl(r_tsptr, tcg_env);
tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
offsetof(trap_state, tnpc));
}
TCGv_ptr r_tsptr;
r_tsptr = tcg_temp_new_ptr();
- gen_load_trap_state_at_tl(r_tsptr, cpu_env);
+ gen_load_trap_state_at_tl(r_tsptr, tcg_env);
tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
offsetof(trap_state, tstate));
}
{
TCGv_ptr r_tsptr = tcg_temp_new_ptr();
- gen_load_trap_state_at_tl(r_tsptr, cpu_env);
+ gen_load_trap_state_at_tl(r_tsptr, tcg_env);
tcg_gen_ld32s_tl(cpu_tmp0, r_tsptr,
offsetof(trap_state, tt));
}
r_tickptr = tcg_temp_new_ptr();
r_const = tcg_constant_i32(dc->mem_idx);
- tcg_gen_ld_ptr(r_tickptr, cpu_env,
+ tcg_gen_ld_ptr(r_tickptr, tcg_env,
offsetof(CPUSPARCState, tick));
if (translator_io_start(&dc->base)) {
dc->base.is_jmp = DISAS_EXIT;
}
- gen_helper_tick_get_count(cpu_tmp0, cpu_env,
+ gen_helper_tick_get_count(cpu_tmp0, tcg_env,
r_tickptr, r_const);
}
break;
tcg_gen_mov_tl(cpu_tmp0, cpu_tbr);
break;
case 6: // pstate
- tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
+ tcg_gen_ld32s_tl(cpu_tmp0, tcg_env,
offsetof(CPUSPARCState, pstate));
break;
case 7: // tl
- tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
+ tcg_gen_ld32s_tl(cpu_tmp0, tcg_env,
offsetof(CPUSPARCState, tl));
break;
case 8: // pil
- tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
+ tcg_gen_ld32s_tl(cpu_tmp0, tcg_env,
offsetof(CPUSPARCState, psrpil));
break;
case 9: // cwp
- gen_helper_rdcwp(cpu_tmp0, cpu_env);
+ gen_helper_rdcwp(cpu_tmp0, tcg_env);
break;
case 10: // cansave
- tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
+ tcg_gen_ld32s_tl(cpu_tmp0, tcg_env,
offsetof(CPUSPARCState, cansave));
break;
case 11: // canrestore
- tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
+ tcg_gen_ld32s_tl(cpu_tmp0, tcg_env,
offsetof(CPUSPARCState, canrestore));
break;
case 12: // cleanwin
- tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
+ tcg_gen_ld32s_tl(cpu_tmp0, tcg_env,
offsetof(CPUSPARCState, cleanwin));
break;
case 13: // otherwin
- tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
+ tcg_gen_ld32s_tl(cpu_tmp0, tcg_env,
offsetof(CPUSPARCState, otherwin));
break;
case 14: // wstate
- tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
+ tcg_gen_ld32s_tl(cpu_tmp0, tcg_env,
offsetof(CPUSPARCState, wstate));
break;
case 16: // UA2005 gl
CHECK_IU_FEATURE(dc, GL);
- tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
+ tcg_gen_ld32s_tl(cpu_tmp0, tcg_env,
offsetof(CPUSPARCState, gl));
break;
case 26: // UA2005 strand status
#if defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)
} else if (xop == 0x2b) { /* rdtbr / V9 flushw */
#ifdef TARGET_SPARC64
- gen_helper_flushw(cpu_env);
+ gen_helper_flushw(tcg_env);
#else
if (!supervisor(dc))
goto priv_insn;
break;
#ifdef TARGET_SPARC64
case 0xd: /* V9 udivx */
- gen_helper_udivx(cpu_dst, cpu_env, cpu_src1, cpu_src2);
+ gen_helper_udivx(cpu_dst, tcg_env, cpu_src1, cpu_src2);
break;
#endif
case 0xe: /* udiv */
CHECK_IU_FEATURE(dc, DIV);
if (xop & 0x10) {
- gen_helper_udiv_cc(cpu_dst, cpu_env, cpu_src1,
+ gen_helper_udiv_cc(cpu_dst, tcg_env, cpu_src1,
cpu_src2);
dc->cc_op = CC_OP_DIV;
} else {
- gen_helper_udiv(cpu_dst, cpu_env, cpu_src1,
+ gen_helper_udiv(cpu_dst, tcg_env, cpu_src1,
cpu_src2);
}
break;
case 0xf: /* sdiv */
CHECK_IU_FEATURE(dc, DIV);
if (xop & 0x10) {
- gen_helper_sdiv_cc(cpu_dst, cpu_env, cpu_src1,
+ gen_helper_sdiv_cc(cpu_dst, tcg_env, cpu_src1,
cpu_src2);
dc->cc_op = CC_OP_DIV;
} else {
- gen_helper_sdiv(cpu_dst, cpu_env, cpu_src1,
+ gen_helper_sdiv(cpu_dst, tcg_env, cpu_src1,
cpu_src2);
}
break;
dc->cc_op = CC_OP_TSUB;
break;
case 0x22: /* taddcctv */
- gen_helper_taddcctv(cpu_dst, cpu_env,
+ gen_helper_taddcctv(cpu_dst, tcg_env,
cpu_src1, cpu_src2);
gen_store_gpr(dc, rd, cpu_dst);
dc->cc_op = CC_OP_TADDTV;
break;
case 0x23: /* tsubcctv */
- gen_helper_tsubcctv(cpu_dst, cpu_env,
+ gen_helper_tsubcctv(cpu_dst, tcg_env,
cpu_src1, cpu_src2);
gen_store_gpr(dc, rd, cpu_dst);
dc->cc_op = CC_OP_TSUBTV;
CPU_FEATURE_POWERDOWN)) {
/* LEON3 power-down */
save_state(dc);
- gen_helper_power_down(cpu_env);
+ gen_helper_power_down(tcg_env);
}
break;
#else
case 0x2: /* V9 wrccr */
tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
- gen_helper_wrccr(cpu_env, cpu_tmp0);
+ gen_helper_wrccr(tcg_env, cpu_tmp0);
tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
dc->cc_op = CC_OP_FLAGS;
break;
case 0x3: /* V9 wrasi */
tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xff);
- tcg_gen_st32_tl(cpu_tmp0, cpu_env,
+ tcg_gen_st32_tl(cpu_tmp0, tcg_env,
offsetof(CPUSPARCState, asi));
/*
* End TB to notice changed ASI.
if (!supervisor(dc))
goto illegal_insn;
tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
- gen_helper_set_softint(cpu_env, cpu_tmp0);
+ gen_helper_set_softint(tcg_env, cpu_tmp0);
break;
case 0x15: /* Softint clear */
if (!supervisor(dc))
goto illegal_insn;
tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
- gen_helper_clear_softint(cpu_env, cpu_tmp0);
+ gen_helper_clear_softint(tcg_env, cpu_tmp0);
break;
case 0x16: /* Softint write */
if (!supervisor(dc))
goto illegal_insn;
tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
- gen_helper_write_softint(cpu_env, cpu_tmp0);
+ gen_helper_write_softint(tcg_env, cpu_tmp0);
break;
case 0x17: /* Tick compare */
#if !defined(CONFIG_USER_ONLY)
tcg_gen_xor_tl(cpu_tick_cmpr, cpu_src1,
cpu_src2);
r_tickptr = tcg_temp_new_ptr();
- tcg_gen_ld_ptr(r_tickptr, cpu_env,
+ tcg_gen_ld_ptr(r_tickptr, tcg_env,
offsetof(CPUSPARCState, tick));
translator_io_start(&dc->base);
gen_helper_tick_set_limit(r_tickptr,
tcg_gen_xor_tl(cpu_tmp0, cpu_src1,
cpu_src2);
r_tickptr = tcg_temp_new_ptr();
- tcg_gen_ld_ptr(r_tickptr, cpu_env,
+ tcg_gen_ld_ptr(r_tickptr, tcg_env,
offsetof(CPUSPARCState, stick));
translator_io_start(&dc->base);
gen_helper_tick_set_count(r_tickptr,
tcg_gen_xor_tl(cpu_stick_cmpr, cpu_src1,
cpu_src2);
r_tickptr = tcg_temp_new_ptr();
- tcg_gen_ld_ptr(r_tickptr, cpu_env,
+ tcg_gen_ld_ptr(r_tickptr, tcg_env,
offsetof(CPUSPARCState, stick));
translator_io_start(&dc->base);
gen_helper_tick_set_limit(r_tickptr,
#ifdef TARGET_SPARC64
switch (rd) {
case 0:
- gen_helper_saved(cpu_env);
+ gen_helper_saved(tcg_env);
break;
case 1:
- gen_helper_restored(cpu_env);
+ gen_helper_restored(tcg_env);
break;
case 2: /* UA2005 allclean */
case 3: /* UA2005 otherw */
#else
cpu_tmp0 = tcg_temp_new();
tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
- gen_helper_wrpsr(cpu_env, cpu_tmp0);
+ gen_helper_wrpsr(tcg_env, cpu_tmp0);
tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
dc->cc_op = CC_OP_FLAGS;
save_state(dc);
TCGv_ptr r_tsptr;
r_tsptr = tcg_temp_new_ptr();
- gen_load_trap_state_at_tl(r_tsptr, cpu_env);
+ gen_load_trap_state_at_tl(r_tsptr, tcg_env);
tcg_gen_st_tl(cpu_tmp0, r_tsptr,
offsetof(trap_state, tpc));
}
TCGv_ptr r_tsptr;
r_tsptr = tcg_temp_new_ptr();
- gen_load_trap_state_at_tl(r_tsptr, cpu_env);
+ gen_load_trap_state_at_tl(r_tsptr, tcg_env);
tcg_gen_st_tl(cpu_tmp0, r_tsptr,
offsetof(trap_state, tnpc));
}
TCGv_ptr r_tsptr;
r_tsptr = tcg_temp_new_ptr();
- gen_load_trap_state_at_tl(r_tsptr, cpu_env);
+ gen_load_trap_state_at_tl(r_tsptr, tcg_env);
tcg_gen_st_tl(cpu_tmp0, r_tsptr,
offsetof(trap_state,
tstate));
TCGv_ptr r_tsptr;
r_tsptr = tcg_temp_new_ptr();
- gen_load_trap_state_at_tl(r_tsptr, cpu_env);
+ gen_load_trap_state_at_tl(r_tsptr, tcg_env);
tcg_gen_st32_tl(cpu_tmp0, r_tsptr,
offsetof(trap_state, tt));
}
TCGv_ptr r_tickptr;
r_tickptr = tcg_temp_new_ptr();
- tcg_gen_ld_ptr(r_tickptr, cpu_env,
+ tcg_gen_ld_ptr(r_tickptr, tcg_env,
offsetof(CPUSPARCState, tick));
translator_io_start(&dc->base);
gen_helper_tick_set_count(r_tickptr,
if (translator_io_start(&dc->base)) {
dc->base.is_jmp = DISAS_EXIT;
}
- gen_helper_wrpstate(cpu_env, cpu_tmp0);
+ gen_helper_wrpstate(tcg_env, cpu_tmp0);
dc->npc = DYNAMIC_PC;
break;
case 7: // tl
save_state(dc);
- tcg_gen_st32_tl(cpu_tmp0, cpu_env,
+ tcg_gen_st32_tl(cpu_tmp0, tcg_env,
offsetof(CPUSPARCState, tl));
dc->npc = DYNAMIC_PC;
break;
if (translator_io_start(&dc->base)) {
dc->base.is_jmp = DISAS_EXIT;
}
- gen_helper_wrpil(cpu_env, cpu_tmp0);
+ gen_helper_wrpil(tcg_env, cpu_tmp0);
break;
case 9: // cwp
- gen_helper_wrcwp(cpu_env, cpu_tmp0);
+ gen_helper_wrcwp(tcg_env, cpu_tmp0);
break;
case 10: // cansave
- tcg_gen_st32_tl(cpu_tmp0, cpu_env,
+ tcg_gen_st32_tl(cpu_tmp0, tcg_env,
offsetof(CPUSPARCState,
cansave));
break;
case 11: // canrestore
- tcg_gen_st32_tl(cpu_tmp0, cpu_env,
+ tcg_gen_st32_tl(cpu_tmp0, tcg_env,
offsetof(CPUSPARCState,
canrestore));
break;
case 12: // cleanwin
- tcg_gen_st32_tl(cpu_tmp0, cpu_env,
+ tcg_gen_st32_tl(cpu_tmp0, tcg_env,
offsetof(CPUSPARCState,
cleanwin));
break;
case 13: // otherwin
- tcg_gen_st32_tl(cpu_tmp0, cpu_env,
+ tcg_gen_st32_tl(cpu_tmp0, tcg_env,
offsetof(CPUSPARCState,
otherwin));
break;
case 14: // wstate
- tcg_gen_st32_tl(cpu_tmp0, cpu_env,
+ tcg_gen_st32_tl(cpu_tmp0, tcg_env,
offsetof(CPUSPARCState,
wstate));
break;
case 16: // UA2005 gl
CHECK_IU_FEATURE(dc, GL);
- gen_helper_wrgl(cpu_env, cpu_tmp0);
+ gen_helper_wrgl(tcg_env, cpu_tmp0);
break;
case 26: // UA2005 strand status
CHECK_IU_FEATURE(dc, HYPV);
tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
switch (rd) {
case 0: // hpstate
- tcg_gen_st_i64(cpu_tmp0, cpu_env,
+ tcg_gen_st_i64(cpu_tmp0, tcg_env,
offsetof(CPUSPARCState,
hpstate));
save_state(dc);
tcg_gen_mov_tl(cpu_hstick_cmpr, cpu_tmp0);
r_tickptr = tcg_temp_new_ptr();
- tcg_gen_ld_ptr(r_tickptr, cpu_env,
+ tcg_gen_ld_ptr(r_tickptr, tcg_env,
offsetof(CPUSPARCState, hstick));
translator_io_start(&dc->base);
gen_helper_tick_set_limit(r_tickptr,
break;
}
case 0x2d: /* V9 sdivx */
- gen_helper_sdivx(cpu_dst, cpu_env, cpu_src1, cpu_src2);
+ gen_helper_sdivx(cpu_dst, tcg_env, cpu_src1, cpu_src2);
gen_store_gpr(dc, rd, cpu_dst);
break;
case 0x2e: /* V9 popc */
tcg_gen_mov_tl(cpu_tmp0, cpu_src1);
}
}
- gen_helper_restore(cpu_env);
+ gen_helper_restore(tcg_env);
gen_mov_pc_npc(dc);
gen_check_align(cpu_tmp0, 3);
tcg_gen_mov_tl(cpu_npc, cpu_tmp0);
gen_check_align(cpu_tmp0, 3);
tcg_gen_mov_tl(cpu_npc, cpu_tmp0);
dc->npc = DYNAMIC_PC;
- gen_helper_rett(cpu_env);
+ gen_helper_rett(tcg_env);
}
goto jmp_insn;
#endif
/* nop */
break;
case 0x3c: /* save */
- gen_helper_save(cpu_env);
+ gen_helper_save(tcg_env);
gen_store_gpr(dc, rd, cpu_tmp0);
break;
case 0x3d: /* restore */
- gen_helper_restore(cpu_env);
+ gen_helper_restore(tcg_env);
gen_store_gpr(dc, rd, cpu_tmp0);
break;
#if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
dc->npc = DYNAMIC_PC;
dc->pc = DYNAMIC_PC;
translator_io_start(&dc->base);
- gen_helper_done(cpu_env);
+ gen_helper_done(tcg_env);
goto jmp_insn;
case 1:
if (!supervisor(dc))
dc->npc = DYNAMIC_PC;
dc->pc = DYNAMIC_PC;
translator_io_start(&dc->base);
- gen_helper_retry(cpu_env);
+ gen_helper_retry(tcg_env);
goto jmp_insn;
default:
goto illegal_insn;
TCGv_i64 t64 = tcg_temp_new_i64();
tcg_gen_qemu_ld_i64(t64, cpu_addr,
dc->mem_idx, MO_TEUQ | MO_ALIGN);
- gen_helper_ldxfsr(cpu_fsr, cpu_env, cpu_fsr, t64);
+ gen_helper_ldxfsr(cpu_fsr, tcg_env, cpu_fsr, t64);
break;
}
#endif
cpu_dst_32 = tcg_temp_new_i32();
tcg_gen_qemu_ld_i32(cpu_dst_32, cpu_addr,
dc->mem_idx, MO_TEUL | MO_ALIGN);
- gen_helper_ldfsr(cpu_fsr, cpu_env, cpu_fsr, cpu_dst_32);
+ gen_helper_ldfsr(cpu_fsr, tcg_env, cpu_fsr, cpu_dst_32);
break;
case 0x22: /* ldqf, load quad fpreg */
CHECK_FPU_FEATURE(dc, FLOAT128);
unsigned int i;
- cpu_regwptr = tcg_global_mem_new_ptr(cpu_env,
+ cpu_regwptr = tcg_global_mem_new_ptr(tcg_env,
offsetof(CPUSPARCState, regwptr),
"regwptr");
for (i = 0; i < ARRAY_SIZE(r32); ++i) {
- *r32[i].ptr = tcg_global_mem_new_i32(cpu_env, r32[i].off, r32[i].name);
+ *r32[i].ptr = tcg_global_mem_new_i32(tcg_env, r32[i].off, r32[i].name);
}
for (i = 0; i < ARRAY_SIZE(rtl); ++i) {
- *rtl[i].ptr = tcg_global_mem_new(cpu_env, rtl[i].off, rtl[i].name);
+ *rtl[i].ptr = tcg_global_mem_new(tcg_env, rtl[i].off, rtl[i].name);
}
cpu_regs[0] = NULL;
for (i = 1; i < 8; ++i) {
- cpu_regs[i] = tcg_global_mem_new(cpu_env,
+ cpu_regs[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUSPARCState, gregs[i]),
gregnames[i]);
}
}
for (i = 0; i < TARGET_DPREGS; i++) {
- cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
+ cpu_fpr[i] = tcg_global_mem_new_i64(tcg_env,
offsetof(CPUSPARCState, fpr[i]),
fregnames[i]);
}
#define gen_helper_1arg(name, arg) do { \
TCGv_i32 helper_tmp = tcg_constant_i32(arg); \
- gen_helper_##name(cpu_env, helper_tmp); \
+ gen_helper_##name(tcg_env, helper_tmp); \
} while (0)
#define GEN_HELPER_LL(name, ret, arg0, arg1, n) do { \
#define GEN_HELPER_RR(name, rl, rh, arg1, arg2) do { \
TCGv_i64 ret = tcg_temp_new_i64(); \
\
- gen_helper_##name(ret, cpu_env, arg1, arg2); \
+ gen_helper_##name(ret, tcg_env, arg1, arg2); \
tcg_gen_extr_i64_i32(rl, rh, ret); \
} while (0)
#define R(ADDRESS, REG, FEATURE) \
case ADDRESS: \
if (has_feature(ctx, FEATURE)) { \
- tcg_gen_ld_tl(ret, cpu_env, offsetof(CPUTriCoreState, REG)); \
+ tcg_gen_ld_tl(ret, tcg_env, offsetof(CPUTriCoreState, REG)); \
} \
break;
#define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE)
{
/* since we're caching PSW make this a special case */
if (offset == 0xfe04) {
- gen_helper_psw_read(ret, cpu_env);
+ gen_helper_psw_read(ret, tcg_env);
} else {
switch (offset) {
#include "csfr.h.inc"
#define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) \
case ADDRESS: \
if (has_feature(ctx, FEATURE)) { \
- tcg_gen_st_tl(r1, cpu_env, offsetof(CPUTriCoreState, REG)); \
+ tcg_gen_st_tl(r1, tcg_env, offsetof(CPUTriCoreState, REG)); \
} \
break;
/* Endinit protected registers
if (ctx->priv == TRICORE_PRIV_SM) {
/* since we're caching PSW make this a special case */
if (offset == 0xfe04) {
- gen_helper_psw_write(cpu_env, r1);
+ gen_helper_psw_write(tcg_env, r1);
ctx->base.is_jmp = DISAS_EXIT_UPDATE;
} else {
switch (offset) {
tcg_gen_shli_i64(temp64, temp64, 16);
tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
- gen_helper_add64_ssov(temp64, cpu_env, temp64_2, temp64);
+ gen_helper_add64_ssov(temp64, tcg_env, temp64_2, temp64);
tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
}
break;
}
tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
- gen_helper_add64_ssov(temp64, cpu_env, temp64_2, temp64);
+ gen_helper_add64_ssov(temp64, tcg_env, temp64_2, temp64);
tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
}
GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
break;
}
- gen_helper_addr_h(ret, cpu_env, temp64, r1_low, r1_high);
+ gen_helper_addr_h(ret, tcg_env, temp64, r1_low, r1_high);
}
static inline void
}
tcg_gen_andi_tl(temp2, r1, 0xffff0000);
tcg_gen_shli_tl(temp, r1, 16);
- gen_helper_addsur_h(ret, cpu_env, temp64, temp, temp2);
+ gen_helper_addsur_h(ret, tcg_env, temp64, temp, temp2);
}
GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
break;
}
- gen_helper_addr_h_ssov(ret, cpu_env, temp64, r1_low, r1_high);
+ gen_helper_addr_h_ssov(ret, tcg_env, temp64, r1_low, r1_high);
}
static inline void
}
tcg_gen_andi_tl(temp2, r1, 0xffff0000);
tcg_gen_shli_tl(temp, r1, 16);
- gen_helper_addsur_h_ssov(ret, cpu_env, temp64, temp, temp2);
+ gen_helper_addsur_h_ssov(ret, tcg_env, temp64, temp, temp2);
}
static inline void
gen_maddr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
{
TCGv t_n = tcg_constant_i32(n);
- gen_helper_maddr_q(ret, cpu_env, r1, r2, r3, t_n);
+ gen_helper_maddr_q(ret, tcg_env, r1, r2, r3, t_n);
}
static inline void
gen_maddrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
{
TCGv t_n = tcg_constant_i32(n);
- gen_helper_maddr_q_ssov(ret, cpu_env, r1, r2, r3, t_n);
+ gen_helper_maddr_q_ssov(ret, tcg_env, r1, r2, r3, t_n);
}
static inline void
tcg_gen_shli_i64(t2, t2, 16);
tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
- gen_helper_add64_ssov(t1, cpu_env, t1, t2);
+ gen_helper_add64_ssov(t1, tcg_env, t1, t2);
tcg_gen_extr_i64_i32(rl, rh, t1);
}
tcg_gen_mul_i64(t2, t2, t3);
tcg_gen_sari_i64(t2, t2, up_shift - n);
- gen_helper_madd32_q_add_ssov(ret, cpu_env, t1, t2);
+ gen_helper_madd32_q_add_ssov(ret, tcg_env, t1, t2);
}
static inline void
TCGv t_n = tcg_constant_i32(n);
tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high);
- gen_helper_madd64_q_ssov(r1, cpu_env, r1, arg2, arg3, t_n);
+ gen_helper_madd64_q_ssov(r1, tcg_env, r1, arg2, arg3, t_n);
tcg_gen_extr_i64_i32(rl, rh, r1);
}
break;
}
tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
- gen_helper_sub64_ssov(temp64, cpu_env, temp64_2, temp64);
+ gen_helper_sub64_ssov(temp64, tcg_env, temp64_2, temp64);
tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
}
GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
break;
}
- gen_helper_subr_h(ret, cpu_env, temp64, r1_low, r1_high);
+ gen_helper_subr_h(ret, tcg_env, temp64, r1_low, r1_high);
}
static inline void
GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
break;
}
- gen_helper_subr_h_ssov(ret, cpu_env, temp64, r1_low, r1_high);
+ gen_helper_subr_h_ssov(ret, tcg_env, temp64, r1_low, r1_high);
}
static inline void
gen_msubr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
{
TCGv temp = tcg_constant_i32(n);
- gen_helper_msubr_q(ret, cpu_env, r1, r2, r3, temp);
+ gen_helper_msubr_q(ret, tcg_env, r1, r2, r3, temp);
}
static inline void
gen_msubrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
{
TCGv temp = tcg_constant_i32(n);
- gen_helper_msubr_q_ssov(ret, cpu_env, r1, r2, r3, temp);
+ gen_helper_msubr_q_ssov(ret, tcg_env, r1, r2, r3, temp);
}
static inline void
tcg_gen_shli_i64(t2, t2, 16);
tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
- gen_helper_sub64_ssov(t1, cpu_env, t1, t2);
+ gen_helper_sub64_ssov(t1, tcg_env, t1, t2);
tcg_gen_extr_i64_i32(rl, rh, t1);
}
tcg_gen_sari_i64(t3, t2, up_shift - n);
tcg_gen_add_i64(t3, t3, t4);
- gen_helper_msub32_q_sub_ssov(ret, cpu_env, t1, t3);
+ gen_helper_msub32_q_sub_ssov(ret, tcg_env, t1, t3);
}
static inline void
TCGv t_n = tcg_constant_i32(n);
tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high);
- gen_helper_msub64_q_ssov(r1, cpu_env, r1, arg2, arg3, t_n);
+ gen_helper_msub64_q_ssov(r1, tcg_env, r1, arg2, arg3, t_n);
tcg_gen_extr_i64_i32(rl, rh, r1);
}
}
tcg_gen_andi_tl(temp2, r1, 0xffff0000);
tcg_gen_shli_tl(temp, r1, 16);
- gen_helper_subadr_h(ret, cpu_env, temp64, temp, temp2);
+ gen_helper_subadr_h(ret, tcg_env, temp64, temp, temp2);
}
static inline void
tcg_gen_shli_i64(temp64, temp64, 16);
tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
- gen_helper_sub64_ssov(temp64, cpu_env, temp64_2, temp64);
+ gen_helper_sub64_ssov(temp64, tcg_env, temp64_2, temp64);
tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
}
}
tcg_gen_andi_tl(temp2, r1, 0xffff0000);
tcg_gen_shli_tl(temp, r1, 16);
- gen_helper_subadr_h_ssov(ret, cpu_env, temp64, temp, temp2);
+ gen_helper_subadr_h_ssov(ret, tcg_env, temp64, temp, temp2);
}
static inline void gen_abs(TCGv ret, TCGv r1)
static inline void gen_absdifsi(TCGv ret, TCGv r1, int32_t con)
{
TCGv temp = tcg_constant_i32(con);
- gen_helper_absdif_ssov(ret, cpu_env, r1, temp);
+ gen_helper_absdif_ssov(ret, tcg_env, r1, temp);
}
static inline void gen_mul_i32s(TCGv ret, TCGv r1, TCGv r2)
static inline void gen_mulsi_i32(TCGv ret, TCGv r1, int32_t con)
{
TCGv temp = tcg_constant_i32(con);
- gen_helper_mul_ssov(ret, cpu_env, r1, temp);
+ gen_helper_mul_ssov(ret, tcg_env, r1, temp);
}
static inline void gen_mulsui_i32(TCGv ret, TCGv r1, int32_t con)
{
TCGv temp = tcg_constant_i32(con);
- gen_helper_mul_suov(ret, cpu_env, r1, temp);
+ gen_helper_mul_suov(ret, tcg_env, r1, temp);
}
/* gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); */
static inline void gen_maddsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
{
TCGv temp = tcg_constant_i32(con);
- gen_helper_madd32_ssov(ret, cpu_env, r1, r2, temp);
+ gen_helper_madd32_ssov(ret, tcg_env, r1, r2, temp);
}
static inline void gen_maddsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
{
TCGv temp = tcg_constant_i32(con);
- gen_helper_madd32_suov(ret, cpu_env, r1, r2, temp);
+ gen_helper_madd32_suov(ret, tcg_env, r1, r2, temp);
}
static void
{
TCGv_i64 temp64 = tcg_temp_new_i64();
tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
- gen_helper_madd64_ssov(temp64, cpu_env, r1, temp64, r3);
+ gen_helper_madd64_ssov(temp64, tcg_env, r1, temp64, r3);
tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
}
{
TCGv_i64 temp64 = tcg_temp_new_i64();
tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
- gen_helper_madd64_suov(temp64, cpu_env, r1, temp64, r3);
+ gen_helper_madd64_suov(temp64, tcg_env, r1, temp64, r3);
tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
}
static inline void gen_msubsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
{
TCGv temp = tcg_constant_i32(con);
- gen_helper_msub32_ssov(ret, cpu_env, r1, r2, temp);
+ gen_helper_msub32_ssov(ret, tcg_env, r1, r2, temp);
}
static inline void gen_msubsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
{
TCGv temp = tcg_constant_i32(con);
- gen_helper_msub32_suov(ret, cpu_env, r1, r2, temp);
+ gen_helper_msub32_suov(ret, tcg_env, r1, r2, temp);
}
static inline void
{
TCGv_i64 temp64 = tcg_temp_new_i64();
tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
- gen_helper_msub64_ssov(temp64, cpu_env, r1, temp64, r3);
+ gen_helper_msub64_ssov(temp64, tcg_env, r1, temp64, r3);
tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
}
{
TCGv_i64 temp64 = tcg_temp_new_i64();
tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
- gen_helper_msub64_suov(temp64, cpu_env, r1, temp64, r3);
+ gen_helper_msub64_suov(temp64, tcg_env, r1, temp64, r3);
tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
}
static void gen_shas(TCGv ret, TCGv r1, TCGv r2)
{
- gen_helper_sha_ssov(ret, cpu_env, r1, r2);
+ gen_helper_sha_ssov(ret, tcg_env, r1, r2);
}
static void gen_shasi(TCGv ret, TCGv r1, int32_t con)
static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2)
{
- gen_helper_add_ssov(ret, cpu_env, r1, r2);
+ gen_helper_add_ssov(ret, tcg_env, r1, r2);
}
static inline void gen_addsi(TCGv ret, TCGv r1, int32_t con)
{
TCGv temp = tcg_constant_i32(con);
- gen_helper_add_ssov(ret, cpu_env, r1, temp);
+ gen_helper_add_ssov(ret, tcg_env, r1, temp);
}
static inline void gen_addsui(TCGv ret, TCGv r1, int32_t con)
{
TCGv temp = tcg_constant_i32(con);
- gen_helper_add_suov(ret, cpu_env, r1, temp);
+ gen_helper_add_suov(ret, tcg_env, r1, temp);
}
static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2)
{
- gen_helper_sub_ssov(ret, cpu_env, r1, r2);
+ gen_helper_sub_ssov(ret, tcg_env, r1, r2);
}
static inline void gen_subsu(TCGv ret, TCGv r1, TCGv r2)
{
- gen_helper_sub_suov(ret, cpu_env, r1, r2);
+ gen_helper_sub_suov(ret, tcg_env, r1, r2);
}
static inline void gen_bit_2op(TCGv ret, TCGv r1, TCGv r2,
TCGv_i64 ret = tcg_temp_new_i64();
if (!has_feature(ctx, TRICORE_FEATURE_131)) {
- gen_helper_dvinit_b_13(ret, cpu_env, r1, r2);
+ gen_helper_dvinit_b_13(ret, tcg_env, r1, r2);
} else {
- gen_helper_dvinit_b_131(ret, cpu_env, r1, r2);
+ gen_helper_dvinit_b_131(ret, tcg_env, r1, r2);
}
tcg_gen_extr_i64_i32(rl, rh, ret);
}
TCGv_i64 ret = tcg_temp_new_i64();
if (!has_feature(ctx, TRICORE_FEATURE_131)) {
- gen_helper_dvinit_h_13(ret, cpu_env, r1, r2);
+ gen_helper_dvinit_h_13(ret, tcg_env, r1, r2);
} else {
- gen_helper_dvinit_h_131(ret, cpu_env, r1, r2);
+ gen_helper_dvinit_h_131(ret, tcg_env, r1, r2);
}
tcg_gen_extr_i64_i32(rl, rh, ret);
}
TCGv_i32 tintemp = tcg_constant_i32(tin);
gen_save_pc(ctx->base.pc_next);
- gen_helper_raise_exception_sync(cpu_env, classtemp, tintemp);
+ gen_helper_raise_exception_sync(tcg_env, classtemp, tintemp);
ctx->base.is_jmp = DISAS_NORETURN;
}
break;
case OPC2_32_SYS_RET:
case OPC2_16_SR_RET:
- gen_helper_ret(cpu_env);
+ gen_helper_ret(tcg_env);
ctx->base.is_jmp = DISAS_EXIT;
break;
/* B-format */
gen_compute_branch(ctx, op2, 0, 0, 0, 0);
break;
case OPC2_16_SR_RFE:
- gen_helper_rfe(cpu_env);
+ gen_helper_rfe(tcg_env);
ctx->base.is_jmp = DISAS_EXIT;
break;
case OPC2_16_SR_DEBUG:
switch (op2) {
case OPC2_32_BO_LDLCX_SHORTOFF:
tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
- gen_helper_ldlcx(cpu_env, temp);
+ gen_helper_ldlcx(tcg_env, temp);
break;
case OPC2_32_BO_LDMST_SHORTOFF:
tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_LDUCX_SHORTOFF:
tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
- gen_helper_lducx(cpu_env, temp);
+ gen_helper_lducx(tcg_env, temp);
break;
case OPC2_32_BO_LEA_SHORTOFF:
tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_STLCX_SHORTOFF:
tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
- gen_helper_stlcx(cpu_env, temp);
+ gen_helper_stlcx(tcg_env, temp);
break;
case OPC2_32_BO_STUCX_SHORTOFF:
tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
- gen_helper_stucx(cpu_env, temp);
+ gen_helper_stucx(tcg_env, temp);
break;
case OPC2_32_BO_SWAP_W_SHORTOFF:
tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
gen_abs(cpu_gpr_d[r3], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_ABS_B:
- gen_helper_abs_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]);
+ gen_helper_abs_b(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r2]);
break;
case OPC2_32_RR_ABS_H:
- gen_helper_abs_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]);
+ gen_helper_abs_h(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r2]);
break;
case OPC2_32_RR_ABSDIF:
gen_absdif(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_ABSDIF_B:
- gen_helper_absdif_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
+ gen_helper_absdif_b(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
case OPC2_32_RR_ABSDIF_H:
- gen_helper_absdif_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
+ gen_helper_absdif_h(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
case OPC2_32_RR_ABSDIFS:
- gen_helper_absdif_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
+ gen_helper_absdif_ssov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
case OPC2_32_RR_ABSDIFS_H:
- gen_helper_absdif_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
+ gen_helper_absdif_h_ssov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
case OPC2_32_RR_ABSS:
- gen_helper_abs_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]);
+ gen_helper_abs_ssov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r2]);
break;
case OPC2_32_RR_ABSS_H:
- gen_helper_abs_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]);
+ gen_helper_abs_h_ssov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r2]);
break;
case OPC2_32_RR_ADD:
gen_add_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_ADD_B:
- gen_helper_add_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ gen_helper_add_b(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_ADD_H:
- gen_helper_add_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ gen_helper_add_h(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_ADDC:
gen_addc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
gen_adds(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_ADDS_H:
- gen_helper_add_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
+ gen_helper_add_h_ssov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
case OPC2_32_RR_ADDS_HU:
- gen_helper_add_h_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
+ gen_helper_add_h_suov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
case OPC2_32_RR_ADDS_U:
- gen_helper_add_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
+ gen_helper_add_suov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
case OPC2_32_RR_ADDX:
gen_sub_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_SUB_B:
- gen_helper_sub_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ gen_helper_sub_b(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_SUB_H:
- gen_helper_sub_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ gen_helper_sub_h(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_SUBC:
gen_subc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
gen_subsu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_SUBS_H:
- gen_helper_sub_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
+ gen_helper_sub_h_ssov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
case OPC2_32_RR_SUBS_HU:
- gen_helper_sub_h_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
+ gen_helper_sub_h_suov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
case OPC2_32_RR_SUBX:
gen_helper_sh_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_SHA:
- gen_helper_sha(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ gen_helper_sha(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_SHA_H:
gen_helper_sha_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
}
break;
case OPC2_32_RR_MUL_F:
- gen_helper_fmul(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ gen_helper_fmul(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_DIV_F:
- gen_helper_fdiv(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ gen_helper_fdiv(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_FTOHP:
if (has_feature(ctx, TRICORE_FEATURE_162)) {
- gen_helper_ftohp(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
+ gen_helper_ftohp(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]);
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
case OPC2_32_RR_HPTOF:
if (has_feature(ctx, TRICORE_FEATURE_162)) {
- gen_helper_hptof(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
+ gen_helper_hptof(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]);
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
case OPC2_32_RR_CMP_F:
- gen_helper_fcmp(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ gen_helper_fcmp(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_FTOI:
- gen_helper_ftoi(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
+ gen_helper_ftoi(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]);
break;
case OPC2_32_RR_ITOF:
- gen_helper_itof(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
+ gen_helper_itof(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]);
break;
case OPC2_32_RR_FTOU:
- gen_helper_ftou(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
+ gen_helper_ftou(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]);
break;
case OPC2_32_RR_FTOUZ:
if (has_feature(ctx, TRICORE_FEATURE_131)) {
- gen_helper_ftouz(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
+ gen_helper_ftouz(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]);
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
case OPC2_32_RR_UPDFL:
- gen_helper_updfl(cpu_env, cpu_gpr_d[r1]);
+ gen_helper_updfl(tcg_env, cpu_gpr_d[r1]);
break;
case OPC2_32_RR_UTOF:
- gen_helper_utof(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
+ gen_helper_utof(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]);
break;
case OPC2_32_RR_FTOIZ:
- gen_helper_ftoiz(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
+ gen_helper_ftoiz(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]);
break;
case OPC2_32_RR_QSEED_F:
- gen_helper_qseed(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
+ gen_helper_qseed(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
cpu_gpr_d[r2]);
break;
case OPC2_32_RR2_MULS_32:
- gen_helper_mul_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
+ gen_helper_mul_ssov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
case OPC2_32_RR2_MUL_U_64:
cpu_gpr_d[r2]);
break;
case OPC2_32_RR2_MULS_U_32:
- gen_helper_mul_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
+ gen_helper_mul_suov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
default:
}
break;
case OPC2_32_RRR_ADD_F:
- gen_helper_fadd(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r3]);
+ gen_helper_fadd(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r3]);
break;
case OPC2_32_RRR_SUB_F:
- gen_helper_fsub(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r3]);
+ gen_helper_fsub(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r3]);
break;
case OPC2_32_RRR_MADD_F:
- gen_helper_fmadd(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
+ gen_helper_fmadd(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1],
cpu_gpr_d[r2], cpu_gpr_d[r3]);
break;
case OPC2_32_RRR_MSUB_F:
- gen_helper_fmsub(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
+ gen_helper_fmsub(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1],
cpu_gpr_d[r2], cpu_gpr_d[r3]);
break;
default:
cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR2_MADDS_32:
- gen_helper_madd32_ssov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
+ gen_helper_madd32_ssov(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1],
cpu_gpr_d[r3], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR2_MADDS_64:
cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR2_MADDS_U_32:
- gen_helper_madd32_suov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
+ gen_helper_madd32_suov(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1],
cpu_gpr_d[r3], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR2_MADDS_U_64:
cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR2_MSUBS_32:
- gen_helper_msub32_ssov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
+ gen_helper_msub32_ssov(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1],
cpu_gpr_d[r3], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR2_MSUBS_64:
cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR2_MSUBS_U_32:
- gen_helper_msub32_suov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
+ gen_helper_msub32_suov(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1],
cpu_gpr_d[r3], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR2_MSUBS_U_64:
gen_fret(ctx);
break;
case OPC2_32_SYS_RFE:
- gen_helper_rfe(cpu_env);
+ gen_helper_rfe(tcg_env);
ctx->base.is_jmp = DISAS_EXIT;
break;
case OPC2_32_SYS_RFM:
tmp = tcg_temp_new();
l1 = gen_new_label();
- tcg_gen_ld32u_tl(tmp, cpu_env, offsetof(CPUTriCoreState, DBGSR));
+ tcg_gen_ld32u_tl(tmp, tcg_env, offsetof(CPUTriCoreState, DBGSR));
tcg_gen_andi_tl(tmp, tmp, MASK_DBGSR_DE);
tcg_gen_brcondi_tl(TCG_COND_NE, tmp, 1, l1);
- gen_helper_rfm(cpu_env);
+ gen_helper_rfm(tcg_env);
gen_set_label(l1);
ctx->base.is_jmp = DISAS_EXIT;
} else {
}
break;
case OPC2_32_SYS_RSLCX:
- gen_helper_rslcx(cpu_env);
+ gen_helper_rslcx(tcg_env);
break;
case OPC2_32_SYS_SVLCX:
- gen_helper_svlcx(cpu_env);
+ gen_helper_svlcx(tcg_env);
break;
case OPC2_32_SYS_RESTORE:
if (has_feature(ctx, TRICORE_FEATURE_16)) {
static void tricore_tcg_init_csfr(void)
{
- cpu_PCXI = tcg_global_mem_new(cpu_env,
+ cpu_PCXI = tcg_global_mem_new(tcg_env,
offsetof(CPUTriCoreState, PCXI), "PCXI");
- cpu_PSW = tcg_global_mem_new(cpu_env,
+ cpu_PSW = tcg_global_mem_new(tcg_env,
offsetof(CPUTriCoreState, PSW), "PSW");
- cpu_PC = tcg_global_mem_new(cpu_env,
+ cpu_PC = tcg_global_mem_new(tcg_env,
offsetof(CPUTriCoreState, PC), "PC");
- cpu_ICR = tcg_global_mem_new(cpu_env,
+ cpu_ICR = tcg_global_mem_new(tcg_env,
offsetof(CPUTriCoreState, ICR), "ICR");
}
/* reg init */
for (i = 0 ; i < 16 ; i++) {
- cpu_gpr_a[i] = tcg_global_mem_new(cpu_env,
+ cpu_gpr_a[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUTriCoreState, gpr_a[i]),
regnames_a[i]);
}
for (i = 0 ; i < 16 ; i++) {
- cpu_gpr_d[i] = tcg_global_mem_new(cpu_env,
+ cpu_gpr_d[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUTriCoreState, gpr_d[i]),
regnames_d[i]);
}
tricore_tcg_init_csfr();
/* init PSW flag cache */
- cpu_PSW_C = tcg_global_mem_new(cpu_env,
+ cpu_PSW_C = tcg_global_mem_new(tcg_env,
offsetof(CPUTriCoreState, PSW_USB_C),
"PSW_C");
- cpu_PSW_V = tcg_global_mem_new(cpu_env,
+ cpu_PSW_V = tcg_global_mem_new(tcg_env,
offsetof(CPUTriCoreState, PSW_USB_V),
"PSW_V");
- cpu_PSW_SV = tcg_global_mem_new(cpu_env,
+ cpu_PSW_SV = tcg_global_mem_new(tcg_env,
offsetof(CPUTriCoreState, PSW_USB_SV),
"PSW_SV");
- cpu_PSW_AV = tcg_global_mem_new(cpu_env,
+ cpu_PSW_AV = tcg_global_mem_new(tcg_env,
offsetof(CPUTriCoreState, PSW_USB_AV),
"PSW_AV");
- cpu_PSW_SAV = tcg_global_mem_new(cpu_env,
+ cpu_PSW_SAV = tcg_global_mem_new(tcg_env,
offsetof(CPUTriCoreState, PSW_USB_SAV),
"PSW_SAV");
}
};
int i;
- cpu_pc = tcg_global_mem_new_i32(cpu_env,
+ cpu_pc = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUXtensaState, pc), "pc");
for (i = 0; i < 16; i++) {
- cpu_R[i] = tcg_global_mem_new_i32(cpu_env,
+ cpu_R[i] = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUXtensaState, regs[i]),
regnames[i]);
}
for (i = 0; i < 16; i++) {
- cpu_FR[i] = tcg_global_mem_new_i32(cpu_env,
+ cpu_FR[i] = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUXtensaState,
fregs[i].f32[FP_F32_LOW]),
fregnames[i]);
}
for (i = 0; i < 16; i++) {
- cpu_FRD[i] = tcg_global_mem_new_i64(cpu_env,
+ cpu_FRD[i] = tcg_global_mem_new_i64(tcg_env,
offsetof(CPUXtensaState,
fregs[i].f64),
fregnames[i]);
}
for (i = 0; i < 4; i++) {
- cpu_MR[i] = tcg_global_mem_new_i32(cpu_env,
+ cpu_MR[i] = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUXtensaState,
sregs[MR + i]),
mregnames[i]);
}
for (i = 0; i < 16; i++) {
- cpu_BR[i] = tcg_global_mem_new_i32(cpu_env,
+ cpu_BR[i] = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUXtensaState,
sregs[BR]),
bregnames[i]);
if (i % 4 == 0) {
- cpu_BR4[i / 4] = tcg_global_mem_new_i32(cpu_env,
+ cpu_BR4[i / 4] = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUXtensaState,
sregs[BR]),
bregnames[i]);
}
if (i % 8 == 0) {
- cpu_BR8[i / 8] = tcg_global_mem_new_i32(cpu_env,
+ cpu_BR8[i / 8] = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUXtensaState,
sregs[BR]),
bregnames[i]);
for (i = 0; i < 256; ++i) {
if (sr_name[i]) {
- cpu_SR[i] = tcg_global_mem_new_i32(cpu_env,
+ cpu_SR[i] = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUXtensaState,
sregs[i]),
sr_name[i]);
for (i = 0; i < 256; ++i) {
if (ur_name[i]) {
- cpu_UR[i] = tcg_global_mem_new_i32(cpu_env,
+ cpu_UR[i] = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUXtensaState,
uregs[i]),
ur_name[i]);
}
cpu_windowbase_next =
- tcg_global_mem_new_i32(cpu_env,
+ tcg_global_mem_new_i32(tcg_env,
offsetof(CPUXtensaState, windowbase_next),
"windowbase_next");
cpu_exclusive_addr =
- tcg_global_mem_new_i32(cpu_env,
+ tcg_global_mem_new_i32(tcg_env,
offsetof(CPUXtensaState, exclusive_addr),
"exclusive_addr");
cpu_exclusive_val =
- tcg_global_mem_new_i32(cpu_env,
+ tcg_global_mem_new_i32(tcg_env,
offsetof(CPUXtensaState, exclusive_val),
"exclusive_val");
}
static void gen_exception(DisasContext *dc, int excp)
{
- gen_helper_exception(cpu_env, tcg_constant_i32(excp));
+ gen_helper_exception(tcg_env, tcg_constant_i32(excp));
}
static void gen_exception_cause(DisasContext *dc, uint32_t cause)
{
TCGv_i32 pc = tcg_constant_i32(dc->pc);
- gen_helper_exception_cause(cpu_env, pc, tcg_constant_i32(cause));
+ gen_helper_exception_cause(tcg_env, pc, tcg_constant_i32(cause));
if (cause == ILLEGAL_INSTRUCTION_CAUSE ||
cause == SYSCALL_CAUSE) {
dc->base.is_jmp = DISAS_NORETURN;
static void gen_debug_exception(DisasContext *dc, uint32_t cause)
{
TCGv_i32 pc = tcg_constant_i32(dc->pc);
- gen_helper_debug_exception(cpu_env, pc, tcg_constant_i32(cause));
+ gen_helper_debug_exception(tcg_env, pc, tcg_constant_i32(cause));
if (cause & (DEBUGCAUSE_IB | DEBUGCAUSE_BI | DEBUGCAUSE_BN)) {
dc->base.is_jmp = DISAS_NORETURN;
}
TCGv_i32 pc = tcg_constant_i32(dc->pc);
TCGv_i32 w = tcg_constant_i32(r / 4);
- gen_helper_window_check(cpu_env, pc, w);
+ gen_helper_window_check(tcg_env, pc, w);
dc->base.is_jmp = DISAS_NORETURN;
return false;
}
#ifndef CONFIG_USER_ONLY
if (op_flags & XTENSA_OP_CHECK_INTERRUPTS) {
translator_io_start(&dc->base);
- gen_helper_check_interrupts(cpu_env);
+ gen_helper_check_interrupts(tcg_env);
}
#endif
if (op_flags & XTENSA_OP_SYNC_REGISTER_WINDOW) {
- gen_helper_sync_windowbase(cpu_env);
+ gen_helper_sync_windowbase(tcg_env);
}
if (op_flags & XTENSA_OP_EXIT_TB_M1) {
slot = -1;
if (op_flags & XTENSA_OP_UNDERFLOW) {
TCGv_i32 pc = tcg_constant_i32(dc->pc);
- gen_helper_test_underflow_retw(cpu_env, pc);
+ gen_helper_test_underflow_retw(tcg_env, pc);
}
if (op_flags & XTENSA_OP_ALLOCA) {
TCGv_i32 pc = tcg_constant_i32(dc->pc);
- gen_helper_movsp(cpu_env, pc);
+ gen_helper_movsp(tcg_env, pc);
}
if (coprocessor && !gen_check_cpenable(dc, coprocessor)) {
TCGv_i32 pc = tcg_constant_i32(dc->pc);
TCGv_i32 s = tcg_constant_i32(arg[0].imm);
TCGv_i32 imm = tcg_constant_i32(arg[1].imm);
- gen_helper_entry(cpu_env, pc, s, imm);
+ gen_helper_entry(tcg_env, pc, s, imm);
}
static void translate_extui(DisasContext *dc, const OpcodeArg arg[],
tcg_gen_movi_i32(cpu_pc, dc->pc);
tcg_gen_addi_i32(addr, arg[0].in, arg[1].imm);
- gen_helper_itlb_hit_test(cpu_env, addr);
+ gen_helper_itlb_hit_test(tcg_env, addr);
#endif
}
#ifndef CONFIG_USER_ONLY
TCGv_i32 dtlb = tcg_constant_i32(par[0]);
- gen_helper_itlb(cpu_env, arg[0].in, dtlb);
+ gen_helper_itlb(tcg_env, arg[0].in, dtlb);
#endif
}
if (!option_enabled(dc, XTENSA_OPTION_MPU)) {
TCGv_i32 pc = tcg_constant_i32(dc->pc);
- gen_helper_check_exclusive(cpu_env, pc, addr,
+ gen_helper_check_exclusive(tcg_env, pc, addr,
tcg_constant_i32(is_write));
}
}
TCGv_i32 dtlb = tcg_constant_i32(par[0]);
tcg_gen_movi_i32(cpu_pc, dc->pc);
- gen_helper_ptlb(arg[0].out, cpu_env, arg[1].in, dtlb);
+ gen_helper_ptlb(arg[0].out, tcg_env, arg[1].in, dtlb);
#endif
}
{
#ifndef CONFIG_USER_ONLY
tcg_gen_movi_i32(cpu_pc, dc->pc);
- gen_helper_pptlb(arg[0].out, cpu_env, arg[1].in);
+ gen_helper_pptlb(arg[0].out, tcg_env, arg[1].in);
#endif
}
static void translate_rer(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- gen_helper_rer(arg[0].out, cpu_env, arg[1].in);
+ gen_helper_rer(arg[0].out, tcg_env, arg[1].in);
}
static void translate_ret(DisasContext *dc, const OpcodeArg arg[],
} else {
TCGv_i32 pc = tcg_constant_i32(dc->pc);
- gen_helper_test_ill_retw(cpu_env, pc);
+ gen_helper_test_ill_retw(tcg_env, pc);
return 0;
}
}
cpu_SR[WINDOW_START], tmp);
tcg_gen_movi_i32(tmp, dc->pc);
tcg_gen_deposit_i32(tmp, tmp, cpu_R[0], 0, 30);
- gen_helper_retw(cpu_env, cpu_R[0]);
+ gen_helper_retw(tcg_env, cpu_R[0]);
gen_jump(dc, tmp);
}
cpu_SR[WINDOW_START], tmp);
}
- gen_helper_restore_owb(cpu_env);
+ gen_helper_restore_owb(tcg_env);
gen_jump(dc, cpu_SR[EPC1]);
}
{
#ifndef CONFIG_USER_ONLY
translator_io_start(&dc->base);
- gen_helper_update_ccount(cpu_env);
+ gen_helper_update_ccount(tcg_env);
tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]);
#endif
}
};
TCGv_i32 dtlb = tcg_constant_i32(par[0]);
- helper[par[1]](arg[0].out, cpu_env, arg[1].in, dtlb);
+ helper[par[1]](arg[0].out, tcg_env, arg[1].in, dtlb);
#endif
}
const uint32_t par[])
{
#ifndef CONFIG_USER_ONLY
- gen_helper_rptlb0(arg[0].out, cpu_env, arg[1].in);
+ gen_helper_rptlb0(arg[0].out, tcg_env, arg[1].in);
#endif
}
const uint32_t par[])
{
#ifndef CONFIG_USER_ONLY
- gen_helper_rptlb1(arg[0].out, cpu_env, arg[1].in);
+ gen_helper_rptlb1(arg[0].out, tcg_env, arg[1].in);
#endif
}
{
TCGv_i32 pc = tcg_constant_i32(dc->pc);
- gen_helper_check_atomctl(cpu_env, pc, addr);
+ gen_helper_check_atomctl(tcg_env, pc, addr);
}
#endif
{
#ifndef CONFIG_USER_ONLY
if (semihosting_enabled(dc->cring != 0)) {
- gen_helper_simcall(cpu_env);
+ gen_helper_simcall(tcg_env);
}
#endif
}
TCGv_i32 pc = tcg_constant_i32(dc->base.pc_next);
translator_io_start(&dc->base);
- gen_helper_waiti(cpu_env, pc, tcg_constant_i32(arg[0].imm));
+ gen_helper_waiti(tcg_env, pc, tcg_constant_i32(arg[0].imm));
#endif
}
#ifndef CONFIG_USER_ONLY
TCGv_i32 dtlb = tcg_constant_i32(par[0]);
- gen_helper_wtlb(cpu_env, arg[0].in, arg[1].in, dtlb);
+ gen_helper_wtlb(tcg_env, arg[0].in, arg[1].in, dtlb);
#endif
}
const uint32_t par[])
{
#ifndef CONFIG_USER_ONLY
- gen_helper_wptlb(cpu_env, arg[0].in, arg[1].in);
+ gen_helper_wptlb(tcg_env, arg[0].in, arg[1].in);
#endif
}
static void translate_wer(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- gen_helper_wer(cpu_env, arg[0].in, arg[1].in);
+ gen_helper_wer(tcg_env, arg[0].in, arg[1].in);
}
static void translate_wrmsk_expstate(DisasContext *dc, const OpcodeArg arg[],
assert(id < dc->config->nccompare);
translator_io_start(&dc->base);
tcg_gen_mov_i32(cpu_SR[par[0]], arg[0].in);
- gen_helper_update_ccompare(cpu_env, tcg_constant_i32(id));
+ gen_helper_update_ccompare(tcg_env, tcg_constant_i32(id));
#endif
}
{
#ifndef CONFIG_USER_ONLY
translator_io_start(&dc->base);
- gen_helper_wsr_ccount(cpu_env, arg[0].in);
+ gen_helper_wsr_ccount(tcg_env, arg[0].in);
#endif
}
unsigned id = par[0] - DBREAKA;
assert(id < dc->config->ndbreak);
- gen_helper_wsr_dbreaka(cpu_env, tcg_constant_i32(id), arg[0].in);
+ gen_helper_wsr_dbreaka(tcg_env, tcg_constant_i32(id), arg[0].in);
#endif
}
unsigned id = par[0] - DBREAKC;
assert(id < dc->config->ndbreak);
- gen_helper_wsr_dbreakc(cpu_env, tcg_constant_i32(id), arg[0].in);
+ gen_helper_wsr_dbreakc(tcg_env, tcg_constant_i32(id), arg[0].in);
#endif
}
unsigned id = par[0] - IBREAKA;
assert(id < dc->config->nibreak);
- gen_helper_wsr_ibreaka(cpu_env, tcg_constant_i32(id), arg[0].in);
+ gen_helper_wsr_ibreaka(tcg_env, tcg_constant_i32(id), arg[0].in);
#endif
}
const uint32_t par[])
{
#ifndef CONFIG_USER_ONLY
- gen_helper_wsr_ibreakenable(cpu_env, arg[0].in);
+ gen_helper_wsr_ibreakenable(tcg_env, arg[0].in);
#endif
}
const uint32_t par[])
{
#ifndef CONFIG_USER_ONLY
- gen_helper_intclear(cpu_env, arg[0].in);
+ gen_helper_intclear(tcg_env, arg[0].in);
#endif
}
const uint32_t par[])
{
#ifndef CONFIG_USER_ONLY
- gen_helper_intset(cpu_env, arg[0].in);
+ gen_helper_intset(tcg_env, arg[0].in);
#endif
}
const uint32_t par[])
{
#ifndef CONFIG_USER_ONLY
- gen_helper_wsr_memctl(cpu_env, arg[0].in);
+ gen_helper_wsr_memctl(tcg_env, arg[0].in);
#endif
}
const uint32_t par[])
{
#ifndef CONFIG_USER_ONLY
- gen_helper_wsr_mpuenb(cpu_env, arg[0].in);
+ gen_helper_wsr_mpuenb(tcg_env, arg[0].in);
#endif
}
const uint32_t par[])
{
#ifndef CONFIG_USER_ONLY
- gen_helper_wsr_rasid(cpu_env, arg[0].in);
+ gen_helper_wsr_rasid(tcg_env, arg[0].in);
#endif
}
TCGv_i32 tmp = tcg_temp_new_i32();
translator_io_start(&dc->base);
- gen_helper_update_ccount(cpu_env);
+ gen_helper_update_ccount(tcg_env);
tcg_gen_mov_i32(tmp, cpu_SR[par[0]]);
- gen_helper_wsr_ccount(cpu_env, arg[0].in);
+ gen_helper_wsr_ccount(tcg_env, arg[0].in);
tcg_gen_mov_i32(arg[0].out, tmp);
#endif
static void translate_fpu2k_add_s(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- gen_helper_fpu2k_add_s(arg[0].out, cpu_env,
+ gen_helper_fpu2k_add_s(arg[0].out, tcg_env,
arg[1].in, arg[2].in);
}
tcg_gen_ori_i32(set_br, arg[0].in, 1 << arg[0].imm);
tcg_gen_andi_i32(clr_br, arg[0].in, ~(1 << arg[0].imm));
- helper[par[0]](res, cpu_env, arg[1].in, arg[2].in);
+ helper[par[0]](res, tcg_env, arg[1].in, arg[2].in);
tcg_gen_movcond_i32(TCG_COND_NE,
arg[0].out, res, zero,
set_br, clr_br);
tcg_gen_andi_i32(clr_br, arg[0].in, ~(1 << arg[0].imm));
get_f32_i2(arg, arg32, 1, 2);
- helper[par[0]](res, cpu_env, arg32[1].in, arg32[2].in);
+ helper[par[0]](res, tcg_env, arg32[1].in, arg32[2].in);
tcg_gen_movcond_i32(TCG_COND_NE,
arg[0].out, res, zero,
set_br, clr_br);
TCGv_i32 scale = tcg_constant_i32(-arg[2].imm);
if (par[0]) {
- gen_helper_uitof_d(arg[0].out, cpu_env, arg[1].in, scale);
+ gen_helper_uitof_d(arg[0].out, tcg_env, arg[1].in, scale);
} else {
- gen_helper_itof_d(arg[0].out, cpu_env, arg[1].in, scale);
+ gen_helper_itof_d(arg[0].out, tcg_env, arg[1].in, scale);
}
}
get_f32_o1(arg, arg32, 0);
if (par[0]) {
- gen_helper_uitof_s(arg32[0].out, cpu_env, arg[1].in, scale);
+ gen_helper_uitof_s(arg32[0].out, tcg_env, arg[1].in, scale);
} else {
- gen_helper_itof_s(arg32[0].out, cpu_env, arg[1].in, scale);
+ gen_helper_itof_s(arg32[0].out, tcg_env, arg[1].in, scale);
}
put_f32_o1(arg, arg32, 0);
}
TCGv_i32 scale = tcg_constant_i32(arg[2].imm);
if (par[1]) {
- gen_helper_ftoui_d(arg[0].out, cpu_env, arg[1].in,
+ gen_helper_ftoui_d(arg[0].out, tcg_env, arg[1].in,
rounding_mode, scale);
} else {
- gen_helper_ftoi_d(arg[0].out, cpu_env, arg[1].in,
+ gen_helper_ftoi_d(arg[0].out, tcg_env, arg[1].in,
rounding_mode, scale);
}
}
get_f32_i1(arg, arg32, 1);
if (par[1]) {
- gen_helper_ftoui_s(arg[0].out, cpu_env, arg32[1].in,
+ gen_helper_ftoui_s(arg[0].out, tcg_env, arg32[1].in,
rounding_mode, scale);
} else {
- gen_helper_ftoi_s(arg[0].out, cpu_env, arg32[1].in,
+ gen_helper_ftoi_s(arg[0].out, tcg_env, arg32[1].in,
rounding_mode, scale);
}
put_f32_i1(arg, arg32, 1);
static void translate_fpu2k_madd_s(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- gen_helper_fpu2k_madd_s(arg[0].out, cpu_env,
+ gen_helper_fpu2k_madd_s(arg[0].out, tcg_env,
arg[0].in, arg[1].in, arg[2].in);
}
static void translate_fpu2k_mul_s(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- gen_helper_fpu2k_mul_s(arg[0].out, cpu_env,
+ gen_helper_fpu2k_mul_s(arg[0].out, tcg_env,
arg[1].in, arg[2].in);
}
static void translate_fpu2k_msub_s(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- gen_helper_fpu2k_msub_s(arg[0].out, cpu_env,
+ gen_helper_fpu2k_msub_s(arg[0].out, tcg_env,
arg[0].in, arg[1].in, arg[2].in);
}
static void translate_fpu2k_sub_s(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- gen_helper_fpu2k_sub_s(arg[0].out, cpu_env,
+ gen_helper_fpu2k_sub_s(arg[0].out, tcg_env,
arg[1].in, arg[2].in);
}
static void translate_wur_fpu2k_fcr(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- gen_helper_wur_fpu2k_fcr(cpu_env, arg[0].in);
+ gen_helper_wur_fpu2k_fcr(tcg_env, arg[0].in);
}
static void translate_wur_fpu2k_fsr(DisasContext *dc, const OpcodeArg arg[],
static void translate_add_d(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- gen_helper_add_d(arg[0].out, cpu_env, arg[1].in, arg[2].in);
+ gen_helper_add_d(arg[0].out, tcg_env, arg[1].in, arg[2].in);
}
static void translate_add_s(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
if (option_enabled(dc, XTENSA_OPTION_DFPU_SINGLE_ONLY)) {
- gen_helper_fpu2k_add_s(arg[0].out, cpu_env,
+ gen_helper_fpu2k_add_s(arg[0].out, tcg_env,
arg[1].in, arg[2].in);
} else {
OpcodeArg arg32[3];
get_f32_o1_i2(arg, arg32, 0, 1, 2);
- gen_helper_add_s(arg32[0].out, cpu_env, arg32[1].in, arg32[2].in);
+ gen_helper_add_s(arg32[0].out, tcg_env, arg32[1].in, arg32[2].in);
put_f32_o1_i2(arg, arg32, 0, 1, 2);
}
}
TCGv_i32 v = tcg_temp_new_i32();
tcg_gen_extrl_i64_i32(v, arg[1].in);
- gen_helper_cvtd_s(arg[0].out, cpu_env, v);
+ gen_helper_cvtd_s(arg[0].out, tcg_env, v);
}
static void translate_cvts_d(DisasContext *dc, const OpcodeArg arg[],
{
TCGv_i32 v = tcg_temp_new_i32();
- gen_helper_cvts_d(v, cpu_env, arg[1].in);
+ gen_helper_cvts_d(v, tcg_env, arg[1].in);
tcg_gen_extu_i32_i64(arg[0].out, v);
}
static void translate_madd_d(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- gen_helper_madd_d(arg[0].out, cpu_env,
+ gen_helper_madd_d(arg[0].out, tcg_env,
arg[0].in, arg[1].in, arg[2].in);
}
const uint32_t par[])
{
if (option_enabled(dc, XTENSA_OPTION_DFPU_SINGLE_ONLY)) {
- gen_helper_fpu2k_madd_s(arg[0].out, cpu_env,
+ gen_helper_fpu2k_madd_s(arg[0].out, tcg_env,
arg[0].in, arg[1].in, arg[2].in);
} else {
OpcodeArg arg32[3];
get_f32_o1_i3(arg, arg32, 0, 0, 1, 2);
- gen_helper_madd_s(arg32[0].out, cpu_env,
+ gen_helper_madd_s(arg32[0].out, tcg_env,
arg32[0].in, arg32[1].in, arg32[2].in);
put_f32_o1_i3(arg, arg32, 0, 0, 1, 2);
}
static void translate_mul_d(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- gen_helper_mul_d(arg[0].out, cpu_env, arg[1].in, arg[2].in);
+ gen_helper_mul_d(arg[0].out, tcg_env, arg[1].in, arg[2].in);
}
static void translate_mul_s(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
if (option_enabled(dc, XTENSA_OPTION_DFPU_SINGLE_ONLY)) {
- gen_helper_fpu2k_mul_s(arg[0].out, cpu_env,
+ gen_helper_fpu2k_mul_s(arg[0].out, tcg_env,
arg[1].in, arg[2].in);
} else {
OpcodeArg arg32[3];
get_f32_o1_i2(arg, arg32, 0, 1, 2);
- gen_helper_mul_s(arg32[0].out, cpu_env, arg32[1].in, arg32[2].in);
+ gen_helper_mul_s(arg32[0].out, tcg_env, arg32[1].in, arg32[2].in);
put_f32_o1_i2(arg, arg32, 0, 1, 2);
}
}
static void translate_msub_d(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- gen_helper_msub_d(arg[0].out, cpu_env,
+ gen_helper_msub_d(arg[0].out, tcg_env,
arg[0].in, arg[1].in, arg[2].in);
}
const uint32_t par[])
{
if (option_enabled(dc, XTENSA_OPTION_DFPU_SINGLE_ONLY)) {
- gen_helper_fpu2k_msub_s(arg[0].out, cpu_env,
+ gen_helper_fpu2k_msub_s(arg[0].out, tcg_env,
arg[0].in, arg[1].in, arg[2].in);
} else {
OpcodeArg arg32[3];
get_f32_o1_i3(arg, arg32, 0, 0, 1, 2);
- gen_helper_msub_s(arg32[0].out, cpu_env,
+ gen_helper_msub_s(arg32[0].out, tcg_env,
arg32[0].in, arg32[1].in, arg32[2].in);
put_f32_o1_i3(arg, arg32, 0, 0, 1, 2);
}
static void translate_sub_d(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- gen_helper_sub_d(arg[0].out, cpu_env, arg[1].in, arg[2].in);
+ gen_helper_sub_d(arg[0].out, tcg_env, arg[1].in, arg[2].in);
}
static void translate_sub_s(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
if (option_enabled(dc, XTENSA_OPTION_DFPU_SINGLE_ONLY)) {
- gen_helper_fpu2k_sub_s(arg[0].out, cpu_env,
+ gen_helper_fpu2k_sub_s(arg[0].out, tcg_env,
arg[1].in, arg[2].in);
} else {
OpcodeArg arg32[3];
get_f32_o1_i2(arg, arg32, 0, 1, 2);
- gen_helper_sub_s(arg32[0].out, cpu_env, arg32[1].in, arg32[2].in);
+ gen_helper_sub_s(arg32[0].out, tcg_env, arg32[1].in, arg32[2].in);
put_f32_o1_i2(arg, arg32, 0, 1, 2);
}
}
static void translate_mkdadj_d(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- gen_helper_mkdadj_d(arg[0].out, cpu_env, arg[0].in, arg[1].in);
+ gen_helper_mkdadj_d(arg[0].out, tcg_env, arg[0].in, arg[1].in);
}
static void translate_mkdadj_s(DisasContext *dc, const OpcodeArg arg[],
OpcodeArg arg32[2];
get_f32_o1_i2(arg, arg32, 0, 0, 1);
- gen_helper_mkdadj_s(arg32[0].out, cpu_env, arg32[0].in, arg32[1].in);
+ gen_helper_mkdadj_s(arg32[0].out, tcg_env, arg32[0].in, arg32[1].in);
put_f32_o1_i2(arg, arg32, 0, 0, 1);
}
static void translate_mksadj_d(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- gen_helper_mksadj_d(arg[0].out, cpu_env, arg[1].in);
+ gen_helper_mksadj_d(arg[0].out, tcg_env, arg[1].in);
}
static void translate_mksadj_s(DisasContext *dc, const OpcodeArg arg[],
OpcodeArg arg32[2];
get_f32_o1_i1(arg, arg32, 0, 1);
- gen_helper_mksadj_s(arg32[0].out, cpu_env, arg32[1].in);
+ gen_helper_mksadj_s(arg32[0].out, tcg_env, arg32[1].in);
put_f32_o1_i1(arg, arg32, 0, 1);
}
static void translate_wur_fpu_fcr(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- gen_helper_wur_fpu_fcr(cpu_env, arg[0].in);
+ gen_helper_wur_fpu_fcr(tcg_env, arg[0].in);
}
static void translate_rur_fpu_fsr(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- gen_helper_rur_fpu_fsr(arg[0].out, cpu_env);
+ gen_helper_rur_fpu_fsr(arg[0].out, tcg_env);
}
static void translate_wur_fpu_fsr(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- gen_helper_wur_fpu_fsr(cpu_env, arg[0].in);
+ gen_helper_wur_fpu_fsr(tcg_env, arg[0].in);
}
static const XtensaOpcodeOps fpu_ops[] = {
a0 = tcg_temp_ebb_new_ptr();
a1 = tcg_temp_ebb_new_ptr();
- tcg_gen_addi_ptr(a0, cpu_env, dofs);
- tcg_gen_addi_ptr(a1, cpu_env, aofs);
+ tcg_gen_addi_ptr(a0, tcg_env, dofs);
+ tcg_gen_addi_ptr(a1, tcg_env, aofs);
fn(a0, a1, desc);
a0 = tcg_temp_ebb_new_ptr();
a1 = tcg_temp_ebb_new_ptr();
- tcg_gen_addi_ptr(a0, cpu_env, dofs);
- tcg_gen_addi_ptr(a1, cpu_env, aofs);
+ tcg_gen_addi_ptr(a0, tcg_env, dofs);
+ tcg_gen_addi_ptr(a1, tcg_env, aofs);
fn(a0, a1, c, desc);
a1 = tcg_temp_ebb_new_ptr();
a2 = tcg_temp_ebb_new_ptr();
- tcg_gen_addi_ptr(a0, cpu_env, dofs);
- tcg_gen_addi_ptr(a1, cpu_env, aofs);
- tcg_gen_addi_ptr(a2, cpu_env, bofs);
+ tcg_gen_addi_ptr(a0, tcg_env, dofs);
+ tcg_gen_addi_ptr(a1, tcg_env, aofs);
+ tcg_gen_addi_ptr(a2, tcg_env, bofs);
fn(a0, a1, a2, desc);
a2 = tcg_temp_ebb_new_ptr();
a3 = tcg_temp_ebb_new_ptr();
- tcg_gen_addi_ptr(a0, cpu_env, dofs);
- tcg_gen_addi_ptr(a1, cpu_env, aofs);
- tcg_gen_addi_ptr(a2, cpu_env, bofs);
- tcg_gen_addi_ptr(a3, cpu_env, cofs);
+ tcg_gen_addi_ptr(a0, tcg_env, dofs);
+ tcg_gen_addi_ptr(a1, tcg_env, aofs);
+ tcg_gen_addi_ptr(a2, tcg_env, bofs);
+ tcg_gen_addi_ptr(a3, tcg_env, cofs);
fn(a0, a1, a2, a3, desc);
a3 = tcg_temp_ebb_new_ptr();
a4 = tcg_temp_ebb_new_ptr();
- tcg_gen_addi_ptr(a0, cpu_env, dofs);
- tcg_gen_addi_ptr(a1, cpu_env, aofs);
- tcg_gen_addi_ptr(a2, cpu_env, bofs);
- tcg_gen_addi_ptr(a3, cpu_env, cofs);
- tcg_gen_addi_ptr(a4, cpu_env, xofs);
+ tcg_gen_addi_ptr(a0, tcg_env, dofs);
+ tcg_gen_addi_ptr(a1, tcg_env, aofs);
+ tcg_gen_addi_ptr(a2, tcg_env, bofs);
+ tcg_gen_addi_ptr(a3, tcg_env, cofs);
+ tcg_gen_addi_ptr(a4, tcg_env, xofs);
fn(a0, a1, a2, a3, a4, desc);
a0 = tcg_temp_ebb_new_ptr();
a1 = tcg_temp_ebb_new_ptr();
- tcg_gen_addi_ptr(a0, cpu_env, dofs);
- tcg_gen_addi_ptr(a1, cpu_env, aofs);
+ tcg_gen_addi_ptr(a0, tcg_env, dofs);
+ tcg_gen_addi_ptr(a1, tcg_env, aofs);
fn(a0, a1, ptr, desc);
a1 = tcg_temp_ebb_new_ptr();
a2 = tcg_temp_ebb_new_ptr();
- tcg_gen_addi_ptr(a0, cpu_env, dofs);
- tcg_gen_addi_ptr(a1, cpu_env, aofs);
- tcg_gen_addi_ptr(a2, cpu_env, bofs);
+ tcg_gen_addi_ptr(a0, tcg_env, dofs);
+ tcg_gen_addi_ptr(a1, tcg_env, aofs);
+ tcg_gen_addi_ptr(a2, tcg_env, bofs);
fn(a0, a1, a2, ptr, desc);
a2 = tcg_temp_ebb_new_ptr();
a3 = tcg_temp_ebb_new_ptr();
- tcg_gen_addi_ptr(a0, cpu_env, dofs);
- tcg_gen_addi_ptr(a1, cpu_env, aofs);
- tcg_gen_addi_ptr(a2, cpu_env, bofs);
- tcg_gen_addi_ptr(a3, cpu_env, cofs);
+ tcg_gen_addi_ptr(a0, tcg_env, dofs);
+ tcg_gen_addi_ptr(a1, tcg_env, aofs);
+ tcg_gen_addi_ptr(a2, tcg_env, bofs);
+ tcg_gen_addi_ptr(a3, tcg_env, cofs);
fn(a0, a1, a2, a3, ptr, desc);
a3 = tcg_temp_ebb_new_ptr();
a4 = tcg_temp_ebb_new_ptr();
- tcg_gen_addi_ptr(a0, cpu_env, dofs);
- tcg_gen_addi_ptr(a1, cpu_env, aofs);
- tcg_gen_addi_ptr(a2, cpu_env, bofs);
- tcg_gen_addi_ptr(a3, cpu_env, cofs);
- tcg_gen_addi_ptr(a4, cpu_env, eofs);
+ tcg_gen_addi_ptr(a0, tcg_env, dofs);
+ tcg_gen_addi_ptr(a1, tcg_env, aofs);
+ tcg_gen_addi_ptr(a2, tcg_env, bofs);
+ tcg_gen_addi_ptr(a3, tcg_env, cofs);
+ tcg_gen_addi_ptr(a4, tcg_env, eofs);
fn(a0, a1, a2, a3, a4, ptr, desc);
* are misaligned wrt the maximum vector size, so do that first.
*/
if (dofs & 8) {
- tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V64);
+ tcg_gen_stl_vec(t_vec, tcg_env, dofs + i, TCG_TYPE_V64);
i += 8;
}
* that e.g. size == 80 would be expanded with 2x32 + 1x16.
*/
for (; i + 32 <= oprsz; i += 32) {
- tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V256);
+ tcg_gen_stl_vec(t_vec, tcg_env, dofs + i, TCG_TYPE_V256);
}
/* fallthru */
case TCG_TYPE_V128:
for (; i + 16 <= oprsz; i += 16) {
- tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V128);
+ tcg_gen_stl_vec(t_vec, tcg_env, dofs + i, TCG_TYPE_V128);
}
break;
case TCG_TYPE_V64:
for (; i < oprsz; i += 8) {
- tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V64);
+ tcg_gen_stl_vec(t_vec, tcg_env, dofs + i, TCG_TYPE_V64);
}
break;
default:
/* Implement inline if we picked an implementation size above. */
if (t_32) {
for (i = 0; i < oprsz; i += 4) {
- tcg_gen_st_i32(t_32, cpu_env, dofs + i);
+ tcg_gen_st_i32(t_32, tcg_env, dofs + i);
}
tcg_temp_free_i32(t_32);
goto done;
}
if (t_64) {
for (i = 0; i < oprsz; i += 8) {
- tcg_gen_st_i64(t_64, cpu_env, dofs + i);
+ tcg_gen_st_i64(t_64, tcg_env, dofs + i);
}
tcg_temp_free_i64(t_64);
goto done;
/* Otherwise implement out of line. */
t_ptr = tcg_temp_ebb_new_ptr();
- tcg_gen_addi_ptr(t_ptr, cpu_env, dofs);
+ tcg_gen_addi_ptr(t_ptr, tcg_env, dofs);
/*
* This may be expand_clr for the tail of an operation, e.g.
uint32_t i;
for (i = 0; i < oprsz; i += 4) {
- tcg_gen_ld_i32(t0, cpu_env, aofs + i);
+ tcg_gen_ld_i32(t0, tcg_env, aofs + i);
if (load_dest) {
- tcg_gen_ld_i32(t1, cpu_env, dofs + i);
+ tcg_gen_ld_i32(t1, tcg_env, dofs + i);
}
fni(t1, t0);
- tcg_gen_st_i32(t1, cpu_env, dofs + i);
+ tcg_gen_st_i32(t1, tcg_env, dofs + i);
}
tcg_temp_free_i32(t0);
tcg_temp_free_i32(t1);
uint32_t i;
for (i = 0; i < oprsz; i += 4) {
- tcg_gen_ld_i32(t0, cpu_env, aofs + i);
+ tcg_gen_ld_i32(t0, tcg_env, aofs + i);
if (load_dest) {
- tcg_gen_ld_i32(t1, cpu_env, dofs + i);
+ tcg_gen_ld_i32(t1, tcg_env, dofs + i);
}
fni(t1, t0, c);
- tcg_gen_st_i32(t1, cpu_env, dofs + i);
+ tcg_gen_st_i32(t1, tcg_env, dofs + i);
}
tcg_temp_free_i32(t0);
tcg_temp_free_i32(t1);
uint32_t i;
for (i = 0; i < oprsz; i += 4) {
- tcg_gen_ld_i32(t0, cpu_env, aofs + i);
+ tcg_gen_ld_i32(t0, tcg_env, aofs + i);
if (scalar_first) {
fni(t1, c, t0);
} else {
fni(t1, t0, c);
}
- tcg_gen_st_i32(t1, cpu_env, dofs + i);
+ tcg_gen_st_i32(t1, tcg_env, dofs + i);
}
tcg_temp_free_i32(t0);
tcg_temp_free_i32(t1);
uint32_t i;
for (i = 0; i < oprsz; i += 4) {
- tcg_gen_ld_i32(t0, cpu_env, aofs + i);
- tcg_gen_ld_i32(t1, cpu_env, bofs + i);
+ tcg_gen_ld_i32(t0, tcg_env, aofs + i);
+ tcg_gen_ld_i32(t1, tcg_env, bofs + i);
if (load_dest) {
- tcg_gen_ld_i32(t2, cpu_env, dofs + i);
+ tcg_gen_ld_i32(t2, tcg_env, dofs + i);
}
fni(t2, t0, t1);
- tcg_gen_st_i32(t2, cpu_env, dofs + i);
+ tcg_gen_st_i32(t2, tcg_env, dofs + i);
}
tcg_temp_free_i32(t2);
tcg_temp_free_i32(t1);
uint32_t i;
for (i = 0; i < oprsz; i += 4) {
- tcg_gen_ld_i32(t0, cpu_env, aofs + i);
- tcg_gen_ld_i32(t1, cpu_env, bofs + i);
+ tcg_gen_ld_i32(t0, tcg_env, aofs + i);
+ tcg_gen_ld_i32(t1, tcg_env, bofs + i);
if (load_dest) {
- tcg_gen_ld_i32(t2, cpu_env, dofs + i);
+ tcg_gen_ld_i32(t2, tcg_env, dofs + i);
}
fni(t2, t0, t1, c);
- tcg_gen_st_i32(t2, cpu_env, dofs + i);
+ tcg_gen_st_i32(t2, tcg_env, dofs + i);
}
tcg_temp_free_i32(t0);
tcg_temp_free_i32(t1);
uint32_t i;
for (i = 0; i < oprsz; i += 4) {
- tcg_gen_ld_i32(t1, cpu_env, aofs + i);
- tcg_gen_ld_i32(t2, cpu_env, bofs + i);
- tcg_gen_ld_i32(t3, cpu_env, cofs + i);
+ tcg_gen_ld_i32(t1, tcg_env, aofs + i);
+ tcg_gen_ld_i32(t2, tcg_env, bofs + i);
+ tcg_gen_ld_i32(t3, tcg_env, cofs + i);
fni(t0, t1, t2, t3);
- tcg_gen_st_i32(t0, cpu_env, dofs + i);
+ tcg_gen_st_i32(t0, tcg_env, dofs + i);
if (write_aofs) {
- tcg_gen_st_i32(t1, cpu_env, aofs + i);
+ tcg_gen_st_i32(t1, tcg_env, aofs + i);
}
}
tcg_temp_free_i32(t3);
uint32_t i;
for (i = 0; i < oprsz; i += 4) {
- tcg_gen_ld_i32(t1, cpu_env, aofs + i);
- tcg_gen_ld_i32(t2, cpu_env, bofs + i);
- tcg_gen_ld_i32(t3, cpu_env, cofs + i);
+ tcg_gen_ld_i32(t1, tcg_env, aofs + i);
+ tcg_gen_ld_i32(t2, tcg_env, bofs + i);
+ tcg_gen_ld_i32(t3, tcg_env, cofs + i);
fni(t0, t1, t2, t3, c);
- tcg_gen_st_i32(t0, cpu_env, dofs + i);
+ tcg_gen_st_i32(t0, tcg_env, dofs + i);
}
tcg_temp_free_i32(t3);
tcg_temp_free_i32(t2);
uint32_t i;
for (i = 0; i < oprsz; i += 8) {
- tcg_gen_ld_i64(t0, cpu_env, aofs + i);
+ tcg_gen_ld_i64(t0, tcg_env, aofs + i);
if (load_dest) {
- tcg_gen_ld_i64(t1, cpu_env, dofs + i);
+ tcg_gen_ld_i64(t1, tcg_env, dofs + i);
}
fni(t1, t0);
- tcg_gen_st_i64(t1, cpu_env, dofs + i);
+ tcg_gen_st_i64(t1, tcg_env, dofs + i);
}
tcg_temp_free_i64(t0);
tcg_temp_free_i64(t1);
uint32_t i;
for (i = 0; i < oprsz; i += 8) {
- tcg_gen_ld_i64(t0, cpu_env, aofs + i);
+ tcg_gen_ld_i64(t0, tcg_env, aofs + i);
if (load_dest) {
- tcg_gen_ld_i64(t1, cpu_env, dofs + i);
+ tcg_gen_ld_i64(t1, tcg_env, dofs + i);
}
fni(t1, t0, c);
- tcg_gen_st_i64(t1, cpu_env, dofs + i);
+ tcg_gen_st_i64(t1, tcg_env, dofs + i);
}
tcg_temp_free_i64(t0);
tcg_temp_free_i64(t1);
uint32_t i;
for (i = 0; i < oprsz; i += 8) {
- tcg_gen_ld_i64(t0, cpu_env, aofs + i);
+ tcg_gen_ld_i64(t0, tcg_env, aofs + i);
if (scalar_first) {
fni(t1, c, t0);
} else {
fni(t1, t0, c);
}
- tcg_gen_st_i64(t1, cpu_env, dofs + i);
+ tcg_gen_st_i64(t1, tcg_env, dofs + i);
}
tcg_temp_free_i64(t0);
tcg_temp_free_i64(t1);
uint32_t i;
for (i = 0; i < oprsz; i += 8) {
- tcg_gen_ld_i64(t0, cpu_env, aofs + i);
- tcg_gen_ld_i64(t1, cpu_env, bofs + i);
+ tcg_gen_ld_i64(t0, tcg_env, aofs + i);
+ tcg_gen_ld_i64(t1, tcg_env, bofs + i);
if (load_dest) {
- tcg_gen_ld_i64(t2, cpu_env, dofs + i);
+ tcg_gen_ld_i64(t2, tcg_env, dofs + i);
}
fni(t2, t0, t1);
- tcg_gen_st_i64(t2, cpu_env, dofs + i);
+ tcg_gen_st_i64(t2, tcg_env, dofs + i);
}
tcg_temp_free_i64(t2);
tcg_temp_free_i64(t1);
uint32_t i;
for (i = 0; i < oprsz; i += 8) {
- tcg_gen_ld_i64(t0, cpu_env, aofs + i);
- tcg_gen_ld_i64(t1, cpu_env, bofs + i);
+ tcg_gen_ld_i64(t0, tcg_env, aofs + i);
+ tcg_gen_ld_i64(t1, tcg_env, bofs + i);
if (load_dest) {
- tcg_gen_ld_i64(t2, cpu_env, dofs + i);
+ tcg_gen_ld_i64(t2, tcg_env, dofs + i);
}
fni(t2, t0, t1, c);
- tcg_gen_st_i64(t2, cpu_env, dofs + i);
+ tcg_gen_st_i64(t2, tcg_env, dofs + i);
}
tcg_temp_free_i64(t0);
tcg_temp_free_i64(t1);
uint32_t i;
for (i = 0; i < oprsz; i += 8) {
- tcg_gen_ld_i64(t1, cpu_env, aofs + i);
- tcg_gen_ld_i64(t2, cpu_env, bofs + i);
- tcg_gen_ld_i64(t3, cpu_env, cofs + i);
+ tcg_gen_ld_i64(t1, tcg_env, aofs + i);
+ tcg_gen_ld_i64(t2, tcg_env, bofs + i);
+ tcg_gen_ld_i64(t3, tcg_env, cofs + i);
fni(t0, t1, t2, t3);
- tcg_gen_st_i64(t0, cpu_env, dofs + i);
+ tcg_gen_st_i64(t0, tcg_env, dofs + i);
if (write_aofs) {
- tcg_gen_st_i64(t1, cpu_env, aofs + i);
+ tcg_gen_st_i64(t1, tcg_env, aofs + i);
}
}
tcg_temp_free_i64(t3);
uint32_t i;
for (i = 0; i < oprsz; i += 8) {
- tcg_gen_ld_i64(t1, cpu_env, aofs + i);
- tcg_gen_ld_i64(t2, cpu_env, bofs + i);
- tcg_gen_ld_i64(t3, cpu_env, cofs + i);
+ tcg_gen_ld_i64(t1, tcg_env, aofs + i);
+ tcg_gen_ld_i64(t2, tcg_env, bofs + i);
+ tcg_gen_ld_i64(t3, tcg_env, cofs + i);
fni(t0, t1, t2, t3, c);
- tcg_gen_st_i64(t0, cpu_env, dofs + i);
+ tcg_gen_st_i64(t0, tcg_env, dofs + i);
}
tcg_temp_free_i64(t3);
tcg_temp_free_i64(t2);
uint32_t i;
for (i = 0; i < oprsz; i += tysz) {
- tcg_gen_ld_vec(t0, cpu_env, aofs + i);
+ tcg_gen_ld_vec(t0, tcg_env, aofs + i);
if (load_dest) {
- tcg_gen_ld_vec(t1, cpu_env, dofs + i);
+ tcg_gen_ld_vec(t1, tcg_env, dofs + i);
}
fni(vece, t1, t0);
- tcg_gen_st_vec(t1, cpu_env, dofs + i);
+ tcg_gen_st_vec(t1, tcg_env, dofs + i);
}
tcg_temp_free_vec(t0);
tcg_temp_free_vec(t1);
uint32_t i;
for (i = 0; i < oprsz; i += tysz) {
- tcg_gen_ld_vec(t0, cpu_env, aofs + i);
+ tcg_gen_ld_vec(t0, tcg_env, aofs + i);
if (load_dest) {
- tcg_gen_ld_vec(t1, cpu_env, dofs + i);
+ tcg_gen_ld_vec(t1, tcg_env, dofs + i);
}
fni(vece, t1, t0, c);
- tcg_gen_st_vec(t1, cpu_env, dofs + i);
+ tcg_gen_st_vec(t1, tcg_env, dofs + i);
}
tcg_temp_free_vec(t0);
tcg_temp_free_vec(t1);
uint32_t i;
for (i = 0; i < oprsz; i += tysz) {
- tcg_gen_ld_vec(t0, cpu_env, aofs + i);
+ tcg_gen_ld_vec(t0, tcg_env, aofs + i);
if (scalar_first) {
fni(vece, t1, c, t0);
} else {
fni(vece, t1, t0, c);
}
- tcg_gen_st_vec(t1, cpu_env, dofs + i);
+ tcg_gen_st_vec(t1, tcg_env, dofs + i);
}
tcg_temp_free_vec(t0);
tcg_temp_free_vec(t1);
uint32_t i;
for (i = 0; i < oprsz; i += tysz) {
- tcg_gen_ld_vec(t0, cpu_env, aofs + i);
- tcg_gen_ld_vec(t1, cpu_env, bofs + i);
+ tcg_gen_ld_vec(t0, tcg_env, aofs + i);
+ tcg_gen_ld_vec(t1, tcg_env, bofs + i);
if (load_dest) {
- tcg_gen_ld_vec(t2, cpu_env, dofs + i);
+ tcg_gen_ld_vec(t2, tcg_env, dofs + i);
}
fni(vece, t2, t0, t1);
- tcg_gen_st_vec(t2, cpu_env, dofs + i);
+ tcg_gen_st_vec(t2, tcg_env, dofs + i);
}
tcg_temp_free_vec(t2);
tcg_temp_free_vec(t1);
uint32_t i;
for (i = 0; i < oprsz; i += tysz) {
- tcg_gen_ld_vec(t0, cpu_env, aofs + i);
- tcg_gen_ld_vec(t1, cpu_env, bofs + i);
+ tcg_gen_ld_vec(t0, tcg_env, aofs + i);
+ tcg_gen_ld_vec(t1, tcg_env, bofs + i);
if (load_dest) {
- tcg_gen_ld_vec(t2, cpu_env, dofs + i);
+ tcg_gen_ld_vec(t2, tcg_env, dofs + i);
}
fni(vece, t2, t0, t1, c);
- tcg_gen_st_vec(t2, cpu_env, dofs + i);
+ tcg_gen_st_vec(t2, tcg_env, dofs + i);
}
tcg_temp_free_vec(t0);
tcg_temp_free_vec(t1);
uint32_t i;
for (i = 0; i < oprsz; i += tysz) {
- tcg_gen_ld_vec(t1, cpu_env, aofs + i);
- tcg_gen_ld_vec(t2, cpu_env, bofs + i);
- tcg_gen_ld_vec(t3, cpu_env, cofs + i);
+ tcg_gen_ld_vec(t1, tcg_env, aofs + i);
+ tcg_gen_ld_vec(t2, tcg_env, bofs + i);
+ tcg_gen_ld_vec(t3, tcg_env, cofs + i);
fni(vece, t0, t1, t2, t3);
- tcg_gen_st_vec(t0, cpu_env, dofs + i);
+ tcg_gen_st_vec(t0, tcg_env, dofs + i);
if (write_aofs) {
- tcg_gen_st_vec(t1, cpu_env, aofs + i);
+ tcg_gen_st_vec(t1, tcg_env, aofs + i);
}
}
tcg_temp_free_vec(t3);
uint32_t i;
for (i = 0; i < oprsz; i += tysz) {
- tcg_gen_ld_vec(t1, cpu_env, aofs + i);
- tcg_gen_ld_vec(t2, cpu_env, bofs + i);
- tcg_gen_ld_vec(t3, cpu_env, cofs + i);
+ tcg_gen_ld_vec(t1, tcg_env, aofs + i);
+ tcg_gen_ld_vec(t2, tcg_env, bofs + i);
+ tcg_gen_ld_vec(t3, tcg_env, cofs + i);
fni(vece, t0, t1, t2, t3, c);
- tcg_gen_st_vec(t0, cpu_env, dofs + i);
+ tcg_gen_st_vec(t0, tcg_env, dofs + i);
}
tcg_temp_free_vec(t3);
tcg_temp_free_vec(t2);
TCGType type = choose_vector_type(NULL, vece, oprsz, 0);
if (type != 0) {
TCGv_vec t_vec = tcg_temp_new_vec(type);
- tcg_gen_dup_mem_vec(vece, t_vec, cpu_env, aofs);
+ tcg_gen_dup_mem_vec(vece, t_vec, tcg_env, aofs);
do_dup_store(type, dofs, oprsz, maxsz, t_vec);
tcg_temp_free_vec(t_vec);
} else if (vece <= MO_32) {
TCGv_i32 in = tcg_temp_ebb_new_i32();
switch (vece) {
case MO_8:
- tcg_gen_ld8u_i32(in, cpu_env, aofs);
+ tcg_gen_ld8u_i32(in, tcg_env, aofs);
break;
case MO_16:
- tcg_gen_ld16u_i32(in, cpu_env, aofs);
+ tcg_gen_ld16u_i32(in, tcg_env, aofs);
break;
default:
- tcg_gen_ld_i32(in, cpu_env, aofs);
+ tcg_gen_ld_i32(in, tcg_env, aofs);
break;
}
do_dup(vece, dofs, oprsz, maxsz, in, NULL, 0);
tcg_temp_free_i32(in);
} else {
TCGv_i64 in = tcg_temp_ebb_new_i64();
- tcg_gen_ld_i64(in, cpu_env, aofs);
+ tcg_gen_ld_i64(in, tcg_env, aofs);
do_dup(vece, dofs, oprsz, maxsz, NULL, in, 0);
tcg_temp_free_i64(in);
}
if (TCG_TARGET_HAS_v128) {
TCGv_vec in = tcg_temp_new_vec(TCG_TYPE_V128);
- tcg_gen_ld_vec(in, cpu_env, aofs);
+ tcg_gen_ld_vec(in, tcg_env, aofs);
for (i = (aofs == dofs) * 16; i < oprsz; i += 16) {
- tcg_gen_st_vec(in, cpu_env, dofs + i);
+ tcg_gen_st_vec(in, tcg_env, dofs + i);
}
tcg_temp_free_vec(in);
} else {
TCGv_i64 in0 = tcg_temp_ebb_new_i64();
TCGv_i64 in1 = tcg_temp_ebb_new_i64();
- tcg_gen_ld_i64(in0, cpu_env, aofs);
- tcg_gen_ld_i64(in1, cpu_env, aofs + 8);
+ tcg_gen_ld_i64(in0, tcg_env, aofs);
+ tcg_gen_ld_i64(in1, tcg_env, aofs + 8);
for (i = (aofs == dofs) * 16; i < oprsz; i += 16) {
- tcg_gen_st_i64(in0, cpu_env, dofs + i);
- tcg_gen_st_i64(in1, cpu_env, dofs + i + 8);
+ tcg_gen_st_i64(in0, tcg_env, dofs + i);
+ tcg_gen_st_i64(in1, tcg_env, dofs + i + 8);
}
tcg_temp_free_i64(in0);
tcg_temp_free_i64(in1);
if (TCG_TARGET_HAS_v256) {
TCGv_vec in = tcg_temp_new_vec(TCG_TYPE_V256);
- tcg_gen_ld_vec(in, cpu_env, aofs);
+ tcg_gen_ld_vec(in, tcg_env, aofs);
for (i = (aofs == dofs) * 32; i < oprsz; i += 32) {
- tcg_gen_st_vec(in, cpu_env, dofs + i);
+ tcg_gen_st_vec(in, tcg_env, dofs + i);
}
tcg_temp_free_vec(in);
} else if (TCG_TARGET_HAS_v128) {
TCGv_vec in0 = tcg_temp_new_vec(TCG_TYPE_V128);
TCGv_vec in1 = tcg_temp_new_vec(TCG_TYPE_V128);
- tcg_gen_ld_vec(in0, cpu_env, aofs);
- tcg_gen_ld_vec(in1, cpu_env, aofs + 16);
+ tcg_gen_ld_vec(in0, tcg_env, aofs);
+ tcg_gen_ld_vec(in1, tcg_env, aofs + 16);
for (i = (aofs == dofs) * 32; i < oprsz; i += 32) {
- tcg_gen_st_vec(in0, cpu_env, dofs + i);
- tcg_gen_st_vec(in1, cpu_env, dofs + i + 16);
+ tcg_gen_st_vec(in0, tcg_env, dofs + i);
+ tcg_gen_st_vec(in1, tcg_env, dofs + i + 16);
}
tcg_temp_free_vec(in0);
tcg_temp_free_vec(in1);
for (j = 0; j < 4; ++j) {
in[j] = tcg_temp_ebb_new_i64();
- tcg_gen_ld_i64(in[j], cpu_env, aofs + j * 8);
+ tcg_gen_ld_i64(in[j], tcg_env, aofs + j * 8);
}
for (i = (aofs == dofs) * 32; i < oprsz; i += 32) {
for (j = 0; j < 4; ++j) {
- tcg_gen_st_i64(in[j], cpu_env, dofs + i + j * 8);
+ tcg_gen_st_i64(in[j], tcg_env, dofs + i + j * 8);
}
}
for (j = 0; j < 4; ++j) {
uint32_t i;
for (i = 0; i < oprsz; i += tysz) {
- tcg_gen_ld_vec(t0, cpu_env, aofs + i);
+ tcg_gen_ld_vec(t0, tcg_env, aofs + i);
fni(vece, t0, t0, shift);
- tcg_gen_st_vec(t0, cpu_env, dofs + i);
+ tcg_gen_st_vec(t0, tcg_env, dofs + i);
}
tcg_temp_free_vec(t0);
}
tcg_gen_shli_i32(desc, shift, SIMD_DATA_SHIFT);
tcg_gen_ori_i32(desc, desc, simd_desc(oprsz, maxsz, 0));
- tcg_gen_addi_ptr(a0, cpu_env, dofs);
- tcg_gen_addi_ptr(a1, cpu_env, aofs);
+ tcg_gen_addi_ptr(a0, tcg_env, dofs);
+ tcg_gen_addi_ptr(a1, tcg_env, aofs);
g->fno[vece](a0, a1, desc);
uint32_t i;
for (i = 0; i < oprsz; i += 4) {
- tcg_gen_ld_i32(t0, cpu_env, aofs + i);
- tcg_gen_ld_i32(t1, cpu_env, bofs + i);
+ tcg_gen_ld_i32(t0, tcg_env, aofs + i);
+ tcg_gen_ld_i32(t1, tcg_env, bofs + i);
tcg_gen_negsetcond_i32(cond, t0, t0, t1);
- tcg_gen_st_i32(t0, cpu_env, dofs + i);
+ tcg_gen_st_i32(t0, tcg_env, dofs + i);
}
tcg_temp_free_i32(t1);
tcg_temp_free_i32(t0);
uint32_t i;
for (i = 0; i < oprsz; i += 8) {
- tcg_gen_ld_i64(t0, cpu_env, aofs + i);
- tcg_gen_ld_i64(t1, cpu_env, bofs + i);
+ tcg_gen_ld_i64(t0, tcg_env, aofs + i);
+ tcg_gen_ld_i64(t1, tcg_env, bofs + i);
tcg_gen_negsetcond_i64(cond, t0, t0, t1);
- tcg_gen_st_i64(t0, cpu_env, dofs + i);
+ tcg_gen_st_i64(t0, tcg_env, dofs + i);
}
tcg_temp_free_i64(t1);
tcg_temp_free_i64(t0);
uint32_t i;
for (i = 0; i < oprsz; i += tysz) {
- tcg_gen_ld_vec(t0, cpu_env, aofs + i);
- tcg_gen_ld_vec(t1, cpu_env, bofs + i);
+ tcg_gen_ld_vec(t0, tcg_env, aofs + i);
+ tcg_gen_ld_vec(t1, tcg_env, bofs + i);
tcg_gen_cmp_vec(cond, vece, t0, t0, t1);
- tcg_gen_st_vec(t0, cpu_env, dofs + i);
+ tcg_gen_st_vec(t0, tcg_env, dofs + i);
}
tcg_temp_free_vec(t1);
tcg_temp_free_vec(t0);
uint32_t i;
for (i = 0; i < oprsz; i += tysz) {
- tcg_gen_ld_vec(t1, cpu_env, aofs + i);
+ tcg_gen_ld_vec(t1, tcg_env, aofs + i);
tcg_gen_cmp_vec(cond, vece, t0, t1, c);
- tcg_gen_st_vec(t0, cpu_env, dofs + i);
+ tcg_gen_st_vec(t0, tcg_env, dofs + i);
}
}
uint32_t i;
for (i = 0; i < oprsz; i += 8) {
- tcg_gen_ld_i64(t0, cpu_env, aofs + i);
+ tcg_gen_ld_i64(t0, tcg_env, aofs + i);
tcg_gen_negsetcond_i64(cond, t0, t0, c);
- tcg_gen_st_i64(t0, cpu_env, dofs + i);
+ tcg_gen_st_i64(t0, tcg_env, dofs + i);
}
tcg_temp_free_i64(t0);
} else if (vece == MO_32 && check_size_impl(oprsz, 4)) {
tcg_gen_extrl_i64_i32(t1, c);
for (i = 0; i < oprsz; i += 8) {
- tcg_gen_ld_i32(t0, cpu_env, aofs + i);
+ tcg_gen_ld_i32(t0, tcg_env, aofs + i);
tcg_gen_negsetcond_i32(cond, t0, t0, t1);
- tcg_gen_st_i32(t0, cpu_env, dofs + i);
+ tcg_gen_st_i32(t0, tcg_env, dofs + i);
}
tcg_temp_free_i32(t0);
tcg_temp_free_i32(t1);
tcg_gen_extu_i32_i64(ext_addr, temp_tcgv_i32(addr));
addr = tcgv_i64_temp(ext_addr);
}
- gen_helper_ld_i128(val, cpu_env, temp_tcgv_i64(addr),
+ gen_helper_ld_i128(val, tcg_env, temp_tcgv_i64(addr),
tcg_constant_i32(orig_oi));
}
tcg_gen_extu_i32_i64(ext_addr, temp_tcgv_i32(addr));
addr = tcgv_i64_temp(ext_addr);
}
- gen_helper_st_i128(cpu_env, temp_tcgv_i64(addr), val,
+ gen_helper_st_i128(tcg_env, temp_tcgv_i64(addr), val,
tcg_constant_i32(orig_oi));
}
oi = make_memop_idx(memop & ~MO_SIGN, idx);
a64 = maybe_extend_addr64(addr);
- gen(retv, cpu_env, a64, cmpv, newv, tcg_constant_i32(oi));
+ gen(retv, tcg_env, a64, cmpv, newv, tcg_constant_i32(oi));
maybe_free_addr64(a64);
if (memop & MO_SIGN) {
if (gen) {
MemOpIdx oi = make_memop_idx(memop, idx);
TCGv_i64 a64 = maybe_extend_addr64(addr);
- gen(retv, cpu_env, a64, cmpv, newv, tcg_constant_i32(oi));
+ gen(retv, tcg_env, a64, cmpv, newv, tcg_constant_i32(oi));
maybe_free_addr64(a64);
return;
}
- gen_helper_exit_atomic(cpu_env);
+ gen_helper_exit_atomic(tcg_env);
/*
* Produce a result for a well-formed opcode stream. This satisfies
MemOpIdx oi = make_memop_idx(memop, idx);
TCGv_i64 a64 = maybe_extend_addr64(addr);
- gen_helper_nonatomic_cmpxchgo(retv, cpu_env, a64, cmpv, newv,
+ gen_helper_nonatomic_cmpxchgo(retv, tcg_env, a64, cmpv, newv,
tcg_constant_i32(oi));
maybe_free_addr64(a64);
} else {
if (gen) {
MemOpIdx oi = make_memop_idx(memop, idx);
TCGv_i64 a64 = maybe_extend_addr64(addr);
- gen(retv, cpu_env, a64, cmpv, newv, tcg_constant_i32(oi));
+ gen(retv, tcg_env, a64, cmpv, newv, tcg_constant_i32(oi));
maybe_free_addr64(a64);
return;
}
- gen_helper_exit_atomic(cpu_env);
+ gen_helper_exit_atomic(tcg_env);
/*
* Produce a result for a well-formed opcode stream. This satisfies
oi = make_memop_idx(memop & ~MO_SIGN, idx);
a64 = maybe_extend_addr64(addr);
- gen(ret, cpu_env, a64, val, tcg_constant_i32(oi));
+ gen(ret, tcg_env, a64, val, tcg_constant_i32(oi));
maybe_free_addr64(a64);
if (memop & MO_SIGN) {
if (gen) {
MemOpIdx oi = make_memop_idx(memop & ~MO_SIGN, idx);
TCGv_i64 a64 = maybe_extend_addr64(addr);
- gen(ret, cpu_env, a64, val, tcg_constant_i32(oi));
+ gen(ret, tcg_env, a64, val, tcg_constant_i32(oi));
maybe_free_addr64(a64);
return;
}
- gen_helper_exit_atomic(cpu_env);
+ gen_helper_exit_atomic(tcg_env);
/* Produce a result, so that we have a well-formed opcode stream
with respect to uses of the result in the (dead) code following. */
tcg_gen_movi_i64(ret, 0);
plugin_gen_disable_mem_helpers();
ptr = tcg_temp_ebb_new_ptr();
- gen_helper_lookup_tb_ptr(ptr, cpu_env);
+ gen_helper_lookup_tb_ptr(ptr, tcg_env);
tcg_gen_op1i(INDEX_op_goto_ptr, tcgv_ptr_arg(ptr));
tcg_temp_free_ptr(ptr);
}
TCGContext **tcg_ctxs;
unsigned int tcg_cur_ctxs;
unsigned int tcg_max_ctxs;
-TCGv_env cpu_env = 0;
+TCGv_env tcg_env;
const void *tcg_code_gen_epilogue;
uintptr_t tcg_splitwx_diff;
tcg_debug_assert(!tcg_regset_test_reg(s->reserved_regs, TCG_AREG0));
ts = tcg_global_reg_new_internal(s, TCG_TYPE_PTR, TCG_AREG0, "env");
- cpu_env = temp_tcgv_ptr(ts);
+ tcg_env = temp_tcgv_ptr(ts);
}
void tcg_init(size_t tb_size, int splitwx, unsigned max_cpus)
projects / qemu.git / commitdiff