drm/i915/fbc: Parametrize FBC register offsets

Parametrize ilk+ FBC register offsets based on the FBC instance.

v2: More intel_ namespace (Jani)
v3: Don't break gvt (Jani)

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211214184616.1410-1-ville.syrjala@linux.intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index b33941c9e089b8f0877a9fb45062ce1f344deeea..0ee71ca35286d7fa94a45249a6e50188234fa494 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -85,6 +85,8 @@ struct intel_fbc {
        struct drm_mm_node compressed_fb;
        struct drm_mm_node compressed_llb;
 
+       enum intel_fbc_id id;
+
        u8 limit;
 
        bool false_color;
@@ -454,10 +456,10 @@ static void ilk_fbc_activate(struct intel_fbc *fbc)
        struct intel_fbc_state *fbc_state = &fbc->state;
        struct drm_i915_private *i915 = fbc->i915;
 
-       intel_de_write(i915, ILK_DPFC_FENCE_YOFF,
+       intel_de_write(i915, ILK_DPFC_FENCE_YOFF(fbc->id),
                       fbc_state->fence_y_offset);
 
-       intel_de_write(i915, ILK_DPFC_CONTROL,
+       intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id),
                       DPFC_CTL_EN | g4x_dpfc_ctl(fbc));
 }
 
@@ -467,28 +469,28 @@ static void ilk_fbc_deactivate(struct intel_fbc *fbc)
        u32 dpfc_ctl;
 
        /* Disable compression */
-       dpfc_ctl = intel_de_read(i915, ILK_DPFC_CONTROL);
+       dpfc_ctl = intel_de_read(i915, ILK_DPFC_CONTROL(fbc->id));
        if (dpfc_ctl & DPFC_CTL_EN) {
                dpfc_ctl &= ~DPFC_CTL_EN;
-               intel_de_write(i915, ILK_DPFC_CONTROL, dpfc_ctl);
+               intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl);
        }
 }
 
 static bool ilk_fbc_is_active(struct intel_fbc *fbc)
 {
-       return intel_de_read(fbc->i915, ILK_DPFC_CONTROL) & DPFC_CTL_EN;
+       return intel_de_read(fbc->i915, ILK_DPFC_CONTROL(fbc->id)) & DPFC_CTL_EN;
 }
 
 static bool ilk_fbc_is_compressing(struct intel_fbc *fbc)
 {
-       return intel_de_read(fbc->i915, ILK_DPFC_STATUS) & DPFC_COMP_SEG_MASK;
+       return intel_de_read(fbc->i915, ILK_DPFC_STATUS(fbc->id)) & DPFC_COMP_SEG_MASK;
 }
 
 static void ilk_fbc_program_cfb(struct intel_fbc *fbc)
 {
        struct drm_i915_private *i915 = fbc->i915;
 
-       intel_de_write(i915, ILK_DPFC_CB_BASE, fbc->compressed_fb.start);
+       intel_de_write(i915, ILK_DPFC_CB_BASE(fbc->id), fbc->compressed_fb.start);
 }
 
 static const struct intel_fbc_funcs ilk_fbc_funcs = {
@@ -524,8 +526,8 @@ static void snb_fbc_nuke(struct intel_fbc *fbc)
 {
        struct drm_i915_private *i915 = fbc->i915;
 
-       intel_de_write(i915, MSG_FBC_REND_STATE, FBC_REND_NUKE);
-       intel_de_posting_read(i915, MSG_FBC_REND_STATE);
+       intel_de_write(i915, MSG_FBC_REND_STATE(fbc->id), FBC_REND_NUKE);
+       intel_de_posting_read(i915, MSG_FBC_REND_STATE(fbc->id));
 }
 
 static const struct intel_fbc_funcs snb_fbc_funcs = {
@@ -547,7 +549,7 @@ static void glk_fbc_program_cfb_stride(struct intel_fbc *fbc)
                val |= FBC_STRIDE_OVERRIDE |
                        FBC_STRIDE(fbc_state->override_cfb_stride / fbc->limit);
 
-       intel_de_write(i915, GLK_FBC_STRIDE, val);
+       intel_de_write(i915, GLK_FBC_STRIDE(fbc->id), val);
 }
 
 static void skl_fbc_program_cfb_stride(struct intel_fbc *fbc)
@@ -598,19 +600,19 @@ static void ivb_fbc_activate(struct intel_fbc *fbc)
        if (i915->ggtt.num_fences)
                snb_fbc_program_fence(fbc);
 
-       intel_de_write(i915, ILK_DPFC_CONTROL,
+       intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id),
                       DPFC_CTL_EN | ivb_dpfc_ctl(fbc));
 }
 
 static bool ivb_fbc_is_compressing(struct intel_fbc *fbc)
 {
-       return intel_de_read(fbc->i915, ILK_DPFC_STATUS2) & DPFC_COMP_SEG_MASK_IVB;
+       return intel_de_read(fbc->i915, ILK_DPFC_STATUS2(fbc->id)) & DPFC_COMP_SEG_MASK_IVB;
 }
 
 static void ivb_fbc_set_false_color(struct intel_fbc *fbc,
                                    bool enable)
 {
-       intel_de_rmw(fbc->i915, ILK_DPFC_CONTROL,
+       intel_de_rmw(fbc->i915, ILK_DPFC_CONTROL(fbc->id),
                     DPFC_CTL_FALSE_COLOR, enable ? DPFC_CTL_FALSE_COLOR : 0);
 }
 
@@ -1620,7 +1622,8 @@ void intel_fbc_add_plane(struct intel_fbc *fbc, struct intel_plane *plane)
        fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
 }
 
-static struct intel_fbc *intel_fbc_create(struct drm_i915_private *i915)
+static struct intel_fbc *intel_fbc_create(struct drm_i915_private *i915,
+                                         enum intel_fbc_id fbc_id)
 {
        struct intel_fbc *fbc;
 
@@ -1628,6 +1631,7 @@ static struct intel_fbc *intel_fbc_create(struct drm_i915_private *i915)
        if (!fbc)
                return NULL;
 
+       fbc->id = fbc_id;
        fbc->i915 = i915;
        INIT_WORK(&fbc->underrun_work, intel_fbc_underrun_work_fn);
        mutex_init(&fbc->lock);
@@ -1671,7 +1675,7 @@ void intel_fbc_init(struct drm_i915_private *i915)
        if (!HAS_FBC(i915))
                return;
 
-       fbc = intel_fbc_create(i915);
+       fbc = intel_fbc_create(i915, INTEL_FBC_A);
        if (!fbc)
                return;
 

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h b/drivers/gpu/drm/i915/display/intel_fbc.h
index 07ad0411fcc3fac5a32671b2960e64c9d63bdcf5..7b7631aec52701050760f0726cca6d11f94dc763 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_fbc.h
+++ b/drivers/gpu/drm/i915/display/intel_fbc.h
@@ -17,6 +17,12 @@ struct intel_fbc;
 struct intel_plane;
 struct intel_plane_state;
 
+enum intel_fbc_id {
+       INTEL_FBC_A,
+
+       I915_MAX_FBCS,
+};
+
 int intel_fbc_atomic_check(struct intel_atomic_state *state);
 bool intel_fbc_pre_update(struct intel_atomic_state *state,
                          struct intel_crtc *crtc);

diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index cde0a477fb497ef02c6d8a31f24be496fb00c722..3938df0db1887332f0cab1fdd80fe7119c546f2b 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -40,6 +40,7 @@
 #include "gvt.h"
 #include "i915_pvinfo.h"
 #include "display/intel_display_types.h"
+#include "display/intel_fbc.h"
 
 /* XXX FIXME i915 has changed PP_XXX definition */
 #define PCH_PP_STATUS  _MMIO(0xc7200)
@@ -2647,12 +2648,12 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
        MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL);
        MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL);
 
-       MMIO_D(ILK_DPFC_CB_BASE, D_ALL);
-       MMIO_D(ILK_DPFC_CONTROL, D_ALL);
-       MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL);
-       MMIO_D(ILK_DPFC_STATUS, D_ALL);
-       MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL);
-       MMIO_D(ILK_DPFC_CHICKEN, D_ALL);
+       MMIO_D(ILK_DPFC_CB_BASE(INTEL_FBC_A), D_ALL);
+       MMIO_D(ILK_DPFC_CONTROL(INTEL_FBC_A), D_ALL);
+       MMIO_D(ILK_DPFC_RECOMP_CTL(INTEL_FBC_A), D_ALL);
+       MMIO_D(ILK_DPFC_STATUS(INTEL_FBC_A), D_ALL);
+       MMIO_D(ILK_DPFC_FENCE_YOFF(INTEL_FBC_A), D_ALL);
+       MMIO_D(ILK_DPFC_CHICKEN(INTEL_FBC_A), D_ALL);
        MMIO_D(ILK_FBC_RT_BASE, D_ALL);
 
        MMIO_D(IPS_CTL, D_ALL);

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9e5ccf86088c046a51de0c757a8576d3dfdc158a..8528db2588277eaf5e0bbb0ca5146c2fe8b11268 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3353,10 +3353,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define FBC_LL_SIZE            (1536)
 
 /* Framebuffer compression for GM45+ */
-#define DPFC_CB_BASE           _MMIO(0x3200)
-#define ILK_DPFC_CB_BASE       _MMIO(0x43200)
-#define DPFC_CONTROL           _MMIO(0x3208)
-#define ILK_DPFC_CONTROL       _MMIO(0x43208)
+#define DPFC_CB_BASE                   _MMIO(0x3200)
+#define ILK_DPFC_CB_BASE(fbc_id)       _MMIO_PIPE((fbc_id), 0x43200, 0x43240)
+#define DPFC_CONTROL                   _MMIO(0x3208)
+#define ILK_DPFC_CONTROL(fbc_id)       _MMIO_PIPE((fbc_id), 0x43208, 0x43248)
 #define   DPFC_CTL_EN                          REG_BIT(31)
 #define   DPFC_CTL_PLANE_MASK_G4X              REG_BIT(30) /* g4x-snb */
 #define   DPFC_CTL_PLANE_G4X(i9xx_plane)       REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_G4X, (i9xx_plane))
@@ -3374,28 +3374,28 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define   DPFC_CTL_LIMIT_4X                    REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 2)
 #define   DPFC_CTL_FENCENO_MASK                        REG_GENMASK(3, 0)
 #define   DPFC_CTL_FENCENO(fence)              REG_FIELD_PREP(DPFC_CTL_FENCENO_MASK, (fence))
-#define DPFC_RECOMP_CTL                _MMIO(0x320c)
-#define ILK_DPFC_RECOMP_CTL    _MMIO(0x4320c)
+#define DPFC_RECOMP_CTL                        _MMIO(0x320c)
+#define ILK_DPFC_RECOMP_CTL(fbc_id)    _MMIO_PIPE((fbc_id), 0x4320c, 0x4324c)
 #define   DPFC_RECOMP_STALL_EN                 REG_BIT(27)
 #define   DPFC_RECOMP_STALL_WM_MASK            REG_GENMASK(26, 16)
 #define   DPFC_RECOMP_TIMER_COUNT_MASK         REG_GENMASK(5, 0)
-#define DPFC_STATUS            _MMIO(0x3210)
-#define ILK_DPFC_STATUS                _MMIO(0x43210)
+#define DPFC_STATUS                    _MMIO(0x3210)
+#define ILK_DPFC_STATUS(fbc_id)                _MMIO_PIPE((fbc_id), 0x43210, 0x43250)
 #define   DPFC_INVAL_SEG_MASK                  REG_GENMASK(26, 16)
 #define   DPFC_COMP_SEG_MASK                   REG_GENMASK(10, 0)
-#define DPFC_STATUS2           _MMIO(0x3214)
-#define ILK_DPFC_STATUS2               _MMIO(0x43214)
+#define DPFC_STATUS2                   _MMIO(0x3214)
+#define ILK_DPFC_STATUS2(fbc_id)       _MMIO_PIPE((fbc_id), 0x43214, 0x43254)
 #define   DPFC_COMP_SEG_MASK_IVB               REG_GENMASK(11, 0)
-#define DPFC_FENCE_YOFF                _MMIO(0x3218)
-#define ILK_DPFC_FENCE_YOFF    _MMIO(0x43218)
-#define DPFC_CHICKEN           _MMIO(0x3224)
-#define ILK_DPFC_CHICKEN       _MMIO(0x43224)
+#define DPFC_FENCE_YOFF                        _MMIO(0x3218)
+#define ILK_DPFC_FENCE_YOFF(fbc_id)    _MMIO_PIPE((fbc_id), 0x43218, 0x43258)
+#define DPFC_CHICKEN                   _MMIO(0x3224)
+#define ILK_DPFC_CHICKEN(fbc_id)       _MMIO_PIPE((fbc_id), 0x43224, 0x43264)
 #define   DPFC_HT_MODIFY                       REG_BIT(31) /* pre-ivb */
 #define   DPFC_NUKE_ON_ANY_MODIFICATION                REG_BIT(23) /* bdw+ */
 #define   DPFC_CHICKEN_COMP_DUMMY_PIXEL                REG_BIT(14) /* glk+ */
 #define   DPFC_DISABLE_DUMMY0                  REG_BIT(8) /* ivb+ */
 
-#define GLK_FBC_STRIDE         _MMIO(0x43228)
+#define GLK_FBC_STRIDE(fbc_id) _MMIO_PIPE((fbc_id), 0x43228, 0x43268)
 #define   FBC_STRIDE_OVERRIDE  REG_BIT(15)
 #define   FBC_STRIDE_MASK      REG_GENMASK(14, 0)
 #define   FBC_STRIDE(x)                REG_FIELD_PREP(FBC_STRIDE_MASK, (x))
@@ -3438,9 +3438,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define IPS_CTL                _MMIO(0x43408)
 #define   IPS_ENABLE   (1 << 31)
 
-#define MSG_FBC_REND_STATE     _MMIO(0x50380)
+#define MSG_FBC_REND_STATE(fbc_id)     _MMIO_PIPE((fbc_id), 0x50380, 0x50384)
 #define   FBC_REND_NUKE                        REG_BIT(2)
-#define   FBC_REND_CACHE_CLEAN                 REG_BIT(1)
+#define   FBC_REND_CACHE_CLEAN         REG_BIT(1)
 
 /*
  * GPIO regs

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index fe1a83c028521bf62585b55a503e92bf57d58981..3714f96f17b3573c60c106b1afc5a7a207b46061 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -160,8 +160,9 @@ static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
         * WaFbcHighMemBwCorruptionAvoidance:bxt
         * Display WA #0883: bxt
         */
-       intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
-                  DPFC_DISABLE_DUMMY0);
+       intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
+                          intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A)) |
+                          DPFC_DISABLE_DUMMY0);
 }
 
 static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
@@ -7451,8 +7452,8 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
 static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
 {
        /* Wa_1409120013:icl,ehl */
-       intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN,
-                  DPFC_CHICKEN_COMP_DUMMY_PIXEL);
+       intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
+                          DPFC_CHICKEN_COMP_DUMMY_PIXEL);
 
        /*Wa_14010594013:icl, ehl */
        intel_uncore_rmw(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1,
@@ -7464,7 +7465,7 @@ static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv)
        /* Wa_1409120013:tgl,rkl,adl-s,dg1,dg2 */
        if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
            IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv) || IS_DG2(dev_priv))
-               intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN,
+               intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
                                   DPFC_CHICKEN_COMP_DUMMY_PIXEL);
 
        /* Wa_1409825376:tgl (pre-prod)*/
@@ -7526,8 +7527,9 @@ static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)
         * WaFbcNukeOnHostModify:cfl
         * Display WA #0873: cfl
         */
-       intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
-                  DPFC_NUKE_ON_ANY_MODIFICATION);
+       intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
+                          intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A)) |
+                          DPFC_NUKE_ON_ANY_MODIFICATION);
 }
 
 static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
@@ -7559,8 +7561,9 @@ static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
         * WaFbcNukeOnHostModify:kbl
         * Display WA #0873: kbl
         */
-       intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
-                  DPFC_NUKE_ON_ANY_MODIFICATION);
+       intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
+                          intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A)) |
+                          DPFC_NUKE_ON_ANY_MODIFICATION);
 }
 
 static void skl_init_clock_gating(struct drm_i915_private *dev_priv)
@@ -7586,15 +7589,17 @@ static void skl_init_clock_gating(struct drm_i915_private *dev_priv)
         * WaFbcNukeOnHostModify:skl
         * Display WA #0873: skl
         */
-       intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
-                  DPFC_NUKE_ON_ANY_MODIFICATION);
+       intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
+                          intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A)) |
+                          DPFC_NUKE_ON_ANY_MODIFICATION);
 
        /*
         * WaFbcHighMemBwCorruptionAvoidance:skl
         * Display WA #0883: skl
         */
-       intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
-                  DPFC_DISABLE_DUMMY0);
+       intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
+                          intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A)) |
+                          DPFC_DISABLE_DUMMY0);
 }
 
 static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)