clk: mediatek: mt2712: Move apmixedsys clock driver to its own file

The only clock driver that does not support mtk_clk_simple_probe() is
apmixedsys: in preparation for enabling module build of non-critical
mt2712 clocks, move this to its own file.
While at it, also fix some indentation issues in the PLLs table.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230306140543.1813621-9-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index e5d018270ed0d691cff8873395512e766ea5ed73..9ba8f666221c31b79385ad0ff5f39d900f572d05 100644 (file)
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -38,7 +38,7 @@ obj-$(CONFIG_COMMON_CLK_MT2701_HIFSYS) += clk-mt2701-hif.o
 obj-$(CONFIG_COMMON_CLK_MT2701_IMGSYS) += clk-mt2701-img.o
 obj-$(CONFIG_COMMON_CLK_MT2701_MMSYS) += clk-mt2701-mm.o
 obj-$(CONFIG_COMMON_CLK_MT2701_VDECSYS) += clk-mt2701-vdec.o
-obj-$(CONFIG_COMMON_CLK_MT2712) += clk-mt2712.o
+obj-$(CONFIG_COMMON_CLK_MT2712) += clk-mt2712-apmixedsys.o clk-mt2712.o
 obj-$(CONFIG_COMMON_CLK_MT2712_BDPSYS) += clk-mt2712-bdp.o
 obj-$(CONFIG_COMMON_CLK_MT2712_IMGSYS) += clk-mt2712-img.o
 obj-$(CONFIG_COMMON_CLK_MT2712_JPGDECSYS) += clk-mt2712-jpgdec.o

diff --git a/drivers/clk/mediatek/clk-mt2712-apmixedsys.c b/drivers/clk/mediatek/clk-mt2712-apmixedsys.c
new file mode 100644 (file)
index 0000000..1e1a827
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt2712-apmixedsys.c
@@ -0,0 +1,153 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ *                    Weiyi Lu <weiyi.lu@mediatek.com>
+ * Copyright (c) 2023 Collabora Ltd.
+ *                    AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+ */
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+
+#include "clk-pll.h"
+#include "clk-mtk.h"
+
+#include <dt-bindings/clock/mt2712-clk.h>
+
+#define MT2712_PLL_FMAX                (3000UL * MHZ)
+
+#define CON0_MT2712_RST_BAR    BIT(24)
+
+#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,  \
+                       _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg,  \
+                       _tuner_en_bit, _pcw_reg, _pcw_shift,            \
+                       _div_table) {                                   \
+               .id = _id,                                              \
+               .name = _name,                                          \
+               .reg = _reg,                                            \
+               .pwr_reg = _pwr_reg,                                    \
+               .en_mask = _en_mask,                                    \
+               .flags = _flags,                                        \
+               .rst_bar_mask = CON0_MT2712_RST_BAR,                    \
+               .fmax = MT2712_PLL_FMAX,                                \
+               .pcwbits = _pcwbits,                                    \
+               .pd_reg = _pd_reg,                                      \
+               .pd_shift = _pd_shift,                                  \
+               .tuner_reg = _tuner_reg,                                \
+               .tuner_en_reg = _tuner_en_reg,                          \
+               .tuner_en_bit = _tuner_en_bit,                          \
+               .pcw_reg = _pcw_reg,                                    \
+               .pcw_shift = _pcw_shift,                                \
+               .div_table = _div_table,                                \
+       }
+
+#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,    \
+                       _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg,  \
+                       _tuner_en_bit, _pcw_reg, _pcw_shift)            \
+               PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags,     \
+                       _pcwbits, _pd_reg, _pd_shift, _tuner_reg,       \
+                       _tuner_en_reg, _tuner_en_bit, _pcw_reg,         \
+                       _pcw_shift, NULL)
+
+static const struct mtk_pll_div_table armca35pll_div_table[] = {
+       { .div = 0, .freq = MT2712_PLL_FMAX },
+       { .div = 1, .freq = 1202500000 },
+       { .div = 2, .freq = 500500000 },
+       { .div = 3, .freq = 315250000 },
+       { .div = 4, .freq = 157625000 },
+       { /* sentinel */ }
+};
+
+static const struct mtk_pll_div_table armca72pll_div_table[] = {
+       { .div = 0, .freq = MT2712_PLL_FMAX },
+       { .div = 1, .freq = 994500000 },
+       { .div = 2, .freq = 520000000 },
+       { .div = 3, .freq = 315250000 },
+       { .div = 4, .freq = 157625000 },
+       { /* sentinel */ }
+};
+
+static const struct mtk_pll_div_table mmpll_div_table[] = {
+       { .div = 0, .freq = MT2712_PLL_FMAX },
+       { .div = 1, .freq = 1001000000 },
+       { .div = 2, .freq = 601250000 },
+       { .div = 3, .freq = 250250000 },
+       { .div = 4, .freq = 125125000 },
+       { /* sentinel */ }
+};
+
+static const struct mtk_pll_data plls[] = {
+       PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, 0xf0000100,
+           HAVE_RST_BAR, 31, 0x0230, 4, 0, 0, 0, 0x0234, 0),
+       PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0240, 0x024C, 0xfe000100,
+           HAVE_RST_BAR, 31, 0x0240, 4, 0, 0, 0, 0x0244, 0),
+       PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x0320, 0x032C, 0xc0000100,
+           0, 31, 0x0320, 4, 0, 0, 0, 0x0324, 0),
+       PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x0280, 0x028C, 0x00000100,
+           0, 31, 0x0280, 4, 0, 0, 0, 0x0284, 0),
+       PLL(CLK_APMIXED_APLL1, "apll1", 0x0330, 0x0340, 0x00000100,
+           0, 31, 0x0330, 4, 0x0338, 0x0014, 0, 0x0334, 0),
+       PLL(CLK_APMIXED_APLL2, "apll2", 0x0350, 0x0360, 0x00000100,
+           0, 31, 0x0350, 4, 0x0358, 0x0014, 1, 0x0354, 0),
+       PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x0370, 0x037c, 0x00000100,
+           0, 31, 0x0370, 4, 0, 0, 0, 0x0374, 0),
+       PLL(CLK_APMIXED_LVDSPLL2, "lvdspll2", 0x0390, 0x039C, 0x00000100,
+           0, 31, 0x0390, 4, 0, 0, 0, 0x0394, 0),
+       PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0270, 0x027C, 0x00000100,
+           0, 31, 0x0270, 4, 0, 0, 0, 0x0274, 0),
+       PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x0410, 0x041C, 0x00000100,
+           0, 31, 0x0410, 4, 0, 0, 0, 0x0414, 0),
+       PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0290, 0x029C, 0xc0000100,
+           0, 31, 0x0290, 4, 0, 0, 0, 0x0294, 0),
+       PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0250, 0x0260, 0x00000100,
+             0, 31, 0x0250, 4, 0, 0, 0, 0x0254, 0, mmpll_div_table),
+       PLL_B(CLK_APMIXED_ARMCA35PLL, "armca35pll", 0x0100, 0x0110, 0xf0000100,
+             HAVE_RST_BAR, 31, 0x0100, 4, 0, 0, 0, 0x0104, 0, armca35pll_div_table),
+       PLL_B(CLK_APMIXED_ARMCA72PLL, "armca72pll", 0x0210, 0x0220, 0x00000100,
+             0, 31, 0x0210, 4, 0, 0, 0, 0x0214, 0, armca72pll_div_table),
+       PLL(CLK_APMIXED_ETHERPLL, "etherpll", 0x0300, 0x030C, 0xc0000100,
+           0, 31, 0x0300, 4, 0, 0, 0, 0x0304, 0),
+};
+
+static int clk_mt2712_apmixed_probe(struct platform_device *pdev)
+{
+       struct clk_hw_onecell_data *clk_data;
+       int r;
+       struct device_node *node = pdev->dev.of_node;
+
+       clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
+       if (!clk_data)
+               return -ENOMEM;
+
+       r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
+       if (r)
+               goto free_clk_data;
+
+       r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+       if (r) {
+               dev_err(&pdev->dev, "Cannot register clock provider: %d\n", r);
+               goto unregister_plls;
+       }
+
+       return 0;
+
+unregister_plls:
+       mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
+free_clk_data:
+       mtk_free_clk_data(clk_data);
+       return r;
+}
+
+static const struct of_device_id of_match_clk_mt2712_apmixed[] = {
+       { .compatible = "mediatek,mt2712-apmixedsys" },
+       { /* sentinel */ }
+};
+
+static struct platform_driver clk_mt2712_apmixed_drv = {
+       .probe = clk_mt2712_apmixed_probe,
+       .driver = {
+               .name = "clk-mt2712-apmixed",
+               .of_match_table = of_match_clk_mt2712_apmixed,
+       },
+};
+builtin_platform_driver(clk_mt2712_apmixed_drv)

diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-mt2712.c
index 8aa361f0fa1380d953a3eecbf2f5385172191bd2..c5fd76d1b9dfa279f954c7d44c5dc99521403099 100644 (file)
--- a/drivers/clk/mediatek/clk-mt2712.c
+++ b/drivers/clk/mediatek/clk-mt2712.c
@@ -14,7 +14,6 @@
 #include <linux/slab.h>
 
 #include "clk-gate.h"
-#include "clk-pll.h"
 #include "clk-mtk.h"
 
 #include <dt-bindings/clock/mt2712-clk.h>
@@ -971,101 +970,6 @@ static const struct mtk_gate peri_clks[] = {
        GATE_PERI2(CLK_PERI_MSDC30_3_QTR_EN, "per_msdc30_3_q", "mem_sel", 7),
 };
 
-#define MT2712_PLL_FMAX                (3000UL * MHZ)
-
-#define CON0_MT2712_RST_BAR    BIT(24)
-
-#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,  \
-                       _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg,  \
-                       _tuner_en_bit, _pcw_reg, _pcw_shift,            \
-                       _div_table) {                                   \
-               .id = _id,                                              \
-               .name = _name,                                          \
-               .reg = _reg,                                            \
-               .pwr_reg = _pwr_reg,                                    \
-               .en_mask = _en_mask,                                    \
-               .flags = _flags,                                        \
-               .rst_bar_mask = CON0_MT2712_RST_BAR,                    \
-               .fmax = MT2712_PLL_FMAX,                                \
-               .pcwbits = _pcwbits,                                    \
-               .pd_reg = _pd_reg,                                      \
-               .pd_shift = _pd_shift,                                  \
-               .tuner_reg = _tuner_reg,                                \
-               .tuner_en_reg = _tuner_en_reg,                          \
-               .tuner_en_bit = _tuner_en_bit,                          \
-               .pcw_reg = _pcw_reg,                                    \
-               .pcw_shift = _pcw_shift,                                \
-               .div_table = _div_table,                                \
-       }
-
-#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,    \
-                       _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg,  \
-                       _tuner_en_bit, _pcw_reg, _pcw_shift)            \
-               PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags,     \
-                       _pcwbits, _pd_reg, _pd_shift, _tuner_reg,       \
-                       _tuner_en_reg, _tuner_en_bit, _pcw_reg,         \
-                       _pcw_shift, NULL)
-
-static const struct mtk_pll_div_table armca35pll_div_table[] = {
-       { .div = 0, .freq = MT2712_PLL_FMAX },
-       { .div = 1, .freq = 1202500000 },
-       { .div = 2, .freq = 500500000 },
-       { .div = 3, .freq = 315250000 },
-       { .div = 4, .freq = 157625000 },
-       { } /* sentinel */
-};
-
-static const struct mtk_pll_div_table armca72pll_div_table[] = {
-       { .div = 0, .freq = MT2712_PLL_FMAX },
-       { .div = 1, .freq = 994500000 },
-       { .div = 2, .freq = 520000000 },
-       { .div = 3, .freq = 315250000 },
-       { .div = 4, .freq = 157625000 },
-       { } /* sentinel */
-};
-
-static const struct mtk_pll_div_table mmpll_div_table[] = {
-       { .div = 0, .freq = MT2712_PLL_FMAX },
-       { .div = 1, .freq = 1001000000 },
-       { .div = 2, .freq = 601250000 },
-       { .div = 3, .freq = 250250000 },
-       { .div = 4, .freq = 125125000 },
-       { } /* sentinel */
-};
-
-static const struct mtk_pll_data plls[] = {
-       PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, 0xf0000100,
-           HAVE_RST_BAR, 31, 0x0230, 4, 0, 0, 0, 0x0234, 0),
-       PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0240, 0x024C, 0xfe000100,
-           HAVE_RST_BAR, 31, 0x0240, 4, 0, 0, 0, 0x0244, 0),
-       PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x0320, 0x032C, 0xc0000100,
-           0, 31, 0x0320, 4, 0, 0, 0, 0x0324, 0),
-       PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x0280, 0x028C, 0x00000100,
-           0, 31, 0x0280, 4, 0, 0, 0, 0x0284, 0),
-       PLL(CLK_APMIXED_APLL1, "apll1", 0x0330, 0x0340, 0x00000100,
-           0, 31, 0x0330, 4, 0x0338, 0x0014, 0, 0x0334, 0),
-       PLL(CLK_APMIXED_APLL2, "apll2", 0x0350, 0x0360, 0x00000100,
-           0, 31, 0x0350, 4, 0x0358, 0x0014, 1, 0x0354, 0),
-       PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x0370, 0x037c, 0x00000100,
-           0, 31, 0x0370, 4, 0, 0, 0, 0x0374, 0),
-       PLL(CLK_APMIXED_LVDSPLL2, "lvdspll2", 0x0390, 0x039C, 0x00000100,
-           0, 31, 0x0390, 4, 0, 0, 0, 0x0394, 0),
-       PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0270, 0x027C, 0x00000100,
-           0, 31, 0x0270, 4, 0, 0, 0, 0x0274, 0),
-       PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x0410, 0x041C, 0x00000100,
-           0, 31, 0x0410, 4, 0, 0, 0, 0x0414, 0),
-       PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0290, 0x029C, 0xc0000100,
-           0, 31, 0x0290, 4, 0, 0, 0, 0x0294, 0),
-       PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0250, 0x0260, 0x00000100,
-           0, 31, 0x0250, 4, 0, 0, 0, 0x0254, 0, mmpll_div_table),
-       PLL_B(CLK_APMIXED_ARMCA35PLL, "armca35pll", 0x0100, 0x0110, 0xf0000100,
-             HAVE_RST_BAR, 31, 0x0100, 4, 0, 0, 0, 0x0104, 0, armca35pll_div_table),
-       PLL_B(CLK_APMIXED_ARMCA72PLL, "armca72pll", 0x0210, 0x0220, 0x00000100,
-             0, 31, 0x0210, 4, 0, 0, 0, 0x0214, 0, armca72pll_div_table),
-       PLL(CLK_APMIXED_ETHERPLL, "etherpll", 0x0300, 0x030C, 0xc0000100,
-           0, 31, 0x0300, 4, 0, 0, 0, 0x0304, 0),
-};
-
 static u16 infrasys_rst_ofs[] = { 0x30, 0x34, };
 static u16 pericfg_rst_ofs[] = { 0x0, 0x4, };
 
@@ -1084,35 +988,6 @@ static const struct mtk_clk_rst_desc clk_rst_desc[] = {
        },
 };
 
-static int clk_mt2712_apmixed_probe(struct platform_device *pdev)
-{
-       struct clk_hw_onecell_data *clk_data;
-       int r;
-       struct device_node *node = pdev->dev.of_node;
-
-       clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
-       if (!clk_data)
-               return -ENOMEM;
-
-       r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
-       if (r)
-               goto free_clk_data;
-
-       r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
-       if (r) {
-               dev_err(&pdev->dev, "Cannot register clock provider: %d\n", r);
-               goto unregister_plls;
-       }
-
-       return 0;
-
-unregister_plls:
-       mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
-free_clk_data:
-       mtk_free_clk_data(clk_data);
-       return r;
-}
-
 static const struct mtk_clk_desc topck_desc = {
        .clks = top_clks,
        .num_clks = ARRAY_SIZE(top_clks),
@@ -1133,33 +1008,6 @@ static const struct mtk_clk_desc mcu_desc = {
        .clk_lock = &mt2712_clk_lock,
 };
 
-static const struct of_device_id of_match_clk_mt2712[] = {
-       {
-               .compatible = "mediatek,mt2712-apmixedsys",
-               .data = clk_mt2712_apmixed_probe,
-       }, {
-               /* sentinel */
-       }
-};
-
-static int clk_mt2712_probe(struct platform_device *pdev)
-{
-       int (*clk_probe)(struct platform_device *);
-       int r;
-
-       clk_probe = of_device_get_match_data(&pdev->dev);
-       if (!clk_probe)
-               return -EINVAL;
-
-       r = clk_probe(pdev);
-       if (r != 0)
-               dev_err(&pdev->dev,
-                       "could not register clock provider: %s: %d\n",
-                       pdev->name, r);
-
-       return r;
-}
-
 static const struct mtk_clk_desc infra_desc = {
        .clks = infra_clks,
        .num_clks = ARRAY_SIZE(infra_clks),
@@ -1189,20 +1037,8 @@ static struct platform_driver clk_mt2712_simple_drv = {
        },
 };
 
-static struct platform_driver clk_mt2712_drv = {
-       .probe = clk_mt2712_probe,
-       .driver = {
-               .name = "clk-mt2712",
-               .of_match_table = of_match_clk_mt2712,
-       },
-};
-
 static int __init clk_mt2712_init(void)
 {
-       int ret = platform_driver_register(&clk_mt2712_drv);
-
-       if (ret)
-               return ret;
        return platform_driver_register(&clk_mt2712_simple_drv);
 }