drm/vc4: hvs: Set AXI panic modes

[ Upstream commit df993fced230daa8452892406f3180c93ebf7e7b ]

The HVS can change AXI request mode based on how full the COB
FIFOs are.
Until now the vc4 driver has been relying on the firmware to
have set these to sensible values.

With HVS channel 2 now being used for live video, change the
panic mode for all channels to be explicitly set by the driver,
and the same for all channels.

Fixes: c54619b0bfb3 ("drm/vc4: Add support for the BCM2711 HVS5")
Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Link: https://lore.kernel.org/r/20221207-rpi-hvs-crtc-misc-v1-2-1f8e0770798b@cerno.tech
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/gpu/drm/vc4/vc4_hvs.c b/drivers/gpu/drm/vc4/vc4_hvs.c
index 9d88bfb50c9b06de8e676038f9d0bbe58480c55f..3856ac289d38081517926d6b740afe2c52446dcd 100644 (file)
--- a/drivers/gpu/drm/vc4/vc4_hvs.c
+++ b/drivers/gpu/drm/vc4/vc4_hvs.c
@@ -718,6 +718,17 @@ static int vc4_hvs_bind(struct device *dev, struct device *master, void *data)
                      SCALER_DISPCTRL_DSPEISLUR(2) |
                      SCALER_DISPCTRL_SCLEIRQ);
 
+       /* Set AXI panic mode.
+        * VC4 panics when < 2 lines in FIFO.
+        * VC5 panics when less than 1 line in the FIFO.
+        */
+       dispctrl &= ~(SCALER_DISPCTRL_PANIC0_MASK |
+                     SCALER_DISPCTRL_PANIC1_MASK |
+                     SCALER_DISPCTRL_PANIC2_MASK);
+       dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_PANIC0);
+       dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_PANIC1);
+       dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_PANIC2);
+
        HVS_WRITE(SCALER_DISPCTRL, dispctrl);
 
        ret = devm_request_irq(dev, platform_get_irq(pdev, 0),

diff --git a/drivers/gpu/drm/vc4/vc4_regs.h b/drivers/gpu/drm/vc4/vc4_regs.h
index 8ac2f088106a658f2e183ef864adbecc11b133d0..fe6d0e21ddd8d3bf3d6b0df1264c449fb9af123b 100644 (file)
--- a/drivers/gpu/drm/vc4/vc4_regs.h
+++ b/drivers/gpu/drm/vc4/vc4_regs.h
@@ -220,6 +220,12 @@
 #define SCALER_DISPCTRL                         0x00000000
 /* Global register for clock gating the HVS */
 # define SCALER_DISPCTRL_ENABLE                        BIT(31)
+# define SCALER_DISPCTRL_PANIC0_MASK           VC4_MASK(25, 24)
+# define SCALER_DISPCTRL_PANIC0_SHIFT          24
+# define SCALER_DISPCTRL_PANIC1_MASK           VC4_MASK(27, 26)
+# define SCALER_DISPCTRL_PANIC1_SHIFT          26
+# define SCALER_DISPCTRL_PANIC2_MASK           VC4_MASK(29, 28)
+# define SCALER_DISPCTRL_PANIC2_SHIFT          28
 # define SCALER_DISPCTRL_DSP3_MUX_MASK         VC4_MASK(19, 18)
 # define SCALER_DISPCTRL_DSP3_MUX_SHIFT                18