riscv: add ISA extension parsing for vector crypto

Add parsing of some Zv* vector crypto ISA extensions that are mentioned
in "RISC-V Cryptography Extensions Volume II" [1]. These ISA extensions
are the following:

- Zvbb: Vector Basic Bit-manipulation
- Zvbc: Vector Carryless Multiplication
- Zvkb: Vector Cryptography Bit-manipulation
- Zvkg: Vector GCM/GMAC.
- Zvkned: NIST Suite: Vector AES Block Cipher
- Zvknh[ab]: NIST Suite: Vector SHA-2 Secure Hash
- Zvksed: ShangMi Suite: SM4 Block Cipher
- Zvksh: ShangMi Suite: SM3 Secure Hash
- Zvkn: NIST Algorithm Suite
- Zvknc: NIST Algorithm Suite with carryless multiply
- Zvkng: NIST Algorithm Suite with GCM.
- Zvks: ShangMi Algorithm Suite
- Zvksc: ShangMi Algorithm Suite with carryless multiplication
- Zvksg: ShangMi Algorithm Suite with GCM.
- Zvkt: Vector Data-Independent Execution Latency.

Link: https://drive.google.com/file/d/1gb9OLH-DhbCgWp7VwpPOVrrY6f3oSJLL/view
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Link: https://lore.kernel.org/r/20231114141256.126749-7-cleger@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index b0857c64bf6e426ad395f4cd466fc1aa1456ab00..477254668d826fb67fe054d94c4d5f750dcf8f39 100644 (file)
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -68,8 +68,18 @@
 #define RISCV_ISA_EXT_ZKSED            53
 #define RISCV_ISA_EXT_ZKSH             54
 #define RISCV_ISA_EXT_ZKT              55
+#define RISCV_ISA_EXT_ZVBB             56
+#define RISCV_ISA_EXT_ZVBC             57
+#define RISCV_ISA_EXT_ZVKB             58
+#define RISCV_ISA_EXT_ZVKG             59
+#define RISCV_ISA_EXT_ZVKNED           60
+#define RISCV_ISA_EXT_ZVKNHA           61
+#define RISCV_ISA_EXT_ZVKNHB           62
+#define RISCV_ISA_EXT_ZVKSED           63
+#define RISCV_ISA_EXT_ZVKSH            64
+#define RISCV_ISA_EXT_ZVKT             65
 
-#define RISCV_ISA_EXT_MAX              64
+#define RISCV_ISA_EXT_MAX              128
 #define RISCV_ISA_EXT_INVALID          U32_MAX
 
 #ifdef CONFIG_RISCV_M_MODE

diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index a2871bceaad970b753a6d1230493a9ba6bd0e319..c4d0f16c29b915fb0d06cb6046baf753ce4fe210 100644 (file)
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -123,6 +123,10 @@ static bool riscv_isa_extension_check(int id)
 #define __RISCV_ISA_EXT_BUNDLE(_name, _bundled_exts) \
        _RISCV_ISA_EXT_DATA(_name, RISCV_ISA_EXT_INVALID, _bundled_exts, ARRAY_SIZE(_bundled_exts))
 
+/* Used to declare extensions that are a superset of other extensions (Zvbb for instance) */
+#define __RISCV_ISA_EXT_SUPERSET(_name, _id, _sub_exts) \
+       _RISCV_ISA_EXT_DATA(_name, _id, _sub_exts, ARRAY_SIZE(_sub_exts))
+
 static const unsigned int riscv_zk_bundled_exts[] = {
        RISCV_ISA_EXT_ZBKB,
        RISCV_ISA_EXT_ZBKC,
@@ -149,6 +153,50 @@ static const unsigned int riscv_zks_bundled_exts[] = {
        RISCV_ISA_EXT_ZKSH
 };
 
+#define RISCV_ISA_EXT_ZVKN     \
+       RISCV_ISA_EXT_ZVKNED,   \
+       RISCV_ISA_EXT_ZVKNHB,   \
+       RISCV_ISA_EXT_ZVKB,     \
+       RISCV_ISA_EXT_ZVKT
+
+static const unsigned int riscv_zvkn_bundled_exts[] = {
+       RISCV_ISA_EXT_ZVKN
+};
+
+static const unsigned int riscv_zvknc_bundled_exts[] = {
+       RISCV_ISA_EXT_ZVKN,
+       RISCV_ISA_EXT_ZVBC
+};
+
+static const unsigned int riscv_zvkng_bundled_exts[] = {
+       RISCV_ISA_EXT_ZVKN,
+       RISCV_ISA_EXT_ZVKG
+};
+
+#define RISCV_ISA_EXT_ZVKS     \
+       RISCV_ISA_EXT_ZVKSED,   \
+       RISCV_ISA_EXT_ZVKSH,    \
+       RISCV_ISA_EXT_ZVKB,     \
+       RISCV_ISA_EXT_ZVKT
+
+static const unsigned int riscv_zvks_bundled_exts[] = {
+       RISCV_ISA_EXT_ZVKS
+};
+
+static const unsigned int riscv_zvksc_bundled_exts[] = {
+       RISCV_ISA_EXT_ZVKS,
+       RISCV_ISA_EXT_ZVBC
+};
+
+static const unsigned int riscv_zvksg_bundled_exts[] = {
+       RISCV_ISA_EXT_ZVKS,
+       RISCV_ISA_EXT_ZVKG
+};
+
+static const unsigned int riscv_zvbb_exts[] = {
+       RISCV_ISA_EXT_ZVKB
+};
+
 /*
  * The canonical order of ISA extension names in the ISA string is defined in
  * chapter 27 of the unprivileged specification.
@@ -227,6 +275,22 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
        __RISCV_ISA_EXT_DATA(zkt, RISCV_ISA_EXT_ZKT),
        __RISCV_ISA_EXT_DATA(zksed, RISCV_ISA_EXT_ZKSED),
        __RISCV_ISA_EXT_DATA(zksh, RISCV_ISA_EXT_ZKSH),
+       __RISCV_ISA_EXT_SUPERSET(zvbb, RISCV_ISA_EXT_ZVBB, riscv_zvbb_exts),
+       __RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC),
+       __RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB),
+       __RISCV_ISA_EXT_DATA(zvkg, RISCV_ISA_EXT_ZVKG),
+       __RISCV_ISA_EXT_BUNDLE(zvkn, riscv_zvkn_bundled_exts),
+       __RISCV_ISA_EXT_BUNDLE(zvknc, riscv_zvknc_bundled_exts),
+       __RISCV_ISA_EXT_DATA(zvkned, RISCV_ISA_EXT_ZVKNED),
+       __RISCV_ISA_EXT_BUNDLE(zvkng, riscv_zvkng_bundled_exts),
+       __RISCV_ISA_EXT_DATA(zvknha, RISCV_ISA_EXT_ZVKNHA),
+       __RISCV_ISA_EXT_DATA(zvknhb, RISCV_ISA_EXT_ZVKNHB),
+       __RISCV_ISA_EXT_BUNDLE(zvks, riscv_zvks_bundled_exts),
+       __RISCV_ISA_EXT_BUNDLE(zvksc, riscv_zvksc_bundled_exts),
+       __RISCV_ISA_EXT_DATA(zvksed, RISCV_ISA_EXT_ZVKSED),
+       __RISCV_ISA_EXT_DATA(zvksh, RISCV_ISA_EXT_ZVKSH),
+       __RISCV_ISA_EXT_BUNDLE(zvksg, riscv_zvksg_bundled_exts),
+       __RISCV_ISA_EXT_DATA(zvkt, RISCV_ISA_EXT_ZVKT),
        __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA),
        __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN),
        __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA),