arm64: dts: qcom: sm8150: switch PCIe QMP PHY to new style of bindings

Change the PCIe QMP PHY to use newer style of QMP PHY bindings (single
resource region, no per-PHY subnodes). As a part of this conversion also
add the missing "ref" clock to the PCIe PHY devices.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230820142035.89903-16-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index e137dd632d755e998481b7d16d2620d7d4f2f14c..b7629f145fd1aad69c509ad35311f4a154236634 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -1875,7 +1875,7 @@
 
                        power-domains = <&gcc PCIE_0_GDSC>;
 
-                       phys = <&pcie0_lane>;
+                       phys = <&pcie0_phy>;
                        phy-names = "pciephy";
 
                        perst-gpio = <&tlmm 35 GPIO_ACTIVE_HIGH>;
@@ -1889,18 +1889,22 @@
 
                pcie0_phy: phy@1c06000 {
                        compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy";
-                       reg = <0 0x01c06000 0 0x1c0>;
-                       #address-cells = <2>;
-                       #size-cells = <2>;
-                       ranges;
+                       reg = <0 0x01c06000 0 0x1000>;
                        clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
                                 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
                                 <&gcc GCC_PCIE_0_CLKREF_CLK>,
-                                <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
+                                <&gcc GCC_PCIE0_PHY_REFGEN_CLK>,
+                                <&gcc GCC_PCIE_0_PIPE_CLK>;
                        clock-names = "aux",
                                      "cfg_ahb",
                                      "ref",
-                                     "refgen";
+                                     "refgen",
+                                     "pipe";
+
+                       clock-output-names = "pcie_0_pipe_clk";
+                       #clock-cells = <0>;
+
+                       #phy-cells = <0>;
 
                        resets = <&gcc GCC_PCIE_0_PHY_BCR>;
                        reset-names = "phy";
@@ -1909,18 +1913,6 @@
                        assigned-clock-rates = <100000000>;
 
                        status = "disabled";
-
-                       pcie0_lane: phy@1c06200 {
-                               reg = <0 0x01c06200 0 0x170>, /* tx */
-                                     <0 0x01c06400 0 0x200>, /* rx */
-                                     <0 0x01c06800 0 0x1f0>, /* pcs */
-                                     <0 0x01c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */
-                               clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
-                               clock-names = "pipe0";
-
-                               #phy-cells = <0>;
-                               clock-output-names = "pcie_0_pipe_clk";
-                       };
                };
 
                pcie1: pci@1c08000 {
@@ -1977,7 +1969,7 @@
 
                        power-domains = <&gcc PCIE_1_GDSC>;
 
-                       phys = <&pcie1_lane>;
+                       phys = <&pcie1_phy>;
                        phy-names = "pciephy";
 
                        perst-gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>;
@@ -1991,18 +1983,22 @@
 
                pcie1_phy: phy@1c0e000 {
                        compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy";
-                       reg = <0 0x01c0e000 0 0x1c0>;
-                       #address-cells = <2>;
-                       #size-cells = <2>;
-                       ranges;
+                       reg = <0 0x01c0e000 0 0x1000>;
                        clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
                                 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
                                 <&gcc GCC_PCIE_1_CLKREF_CLK>,
-                                <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
+                                <&gcc GCC_PCIE1_PHY_REFGEN_CLK>,
+                                <&gcc GCC_PCIE_1_PIPE_CLK>;
                        clock-names = "aux",
                                      "cfg_ahb",
                                      "ref",
-                                     "refgen";
+                                     "refgen",
+                                     "pipe";
+
+                       clock-output-names = "pcie_1_pipe_clk";
+                       #clock-cells = <0>;
+
+                       #phy-cells = <0>;
 
                        resets = <&gcc GCC_PCIE_1_PHY_BCR>;
                        reset-names = "phy";
@@ -2011,20 +2007,6 @@
                        assigned-clock-rates = <100000000>;
 
                        status = "disabled";
-
-                       pcie1_lane: phy@1c0e200 {
-                               reg = <0 0x01c0e200 0 0x170>, /* tx0 */
-                                     <0 0x01c0e400 0 0x200>, /* rx0 */
-                                     <0 0x01c0ea00 0 0x1f0>, /* pcs */
-                                     <0 0x01c0e600 0 0x170>, /* tx1 */
-                                     <0 0x01c0e800 0 0x200>, /* rx1 */
-                                     <0 0x01c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
-                               clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
-                               clock-names = "pipe0";
-
-                               #phy-cells = <0>;
-                               clock-output-names = "pcie_1_pipe_clk";
-                       };
                };
 
                ufs_mem_hc: ufshc@1d84000 {