arm64: dts: renesas: r9a08g045: Add Ethernet nodes

Add the Ethernet nodes available on RZ/G3S (R9A08G045).

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20231207070700.4156557-10-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
index 010bca626855b0aa9b5529e50d1e47771a089787..5facfad9615838ecf422adc71905b40d033e08b1 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
@@ -217,6 +217,44 @@
                        status = "disabled";
                };
 
+               eth0: ethernet@11c30000 {
+                       compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth";
+                       reg = <0 0x11c30000 0 0x10000>;
+                       interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "mux", "fil", "arp_ns";
+                       phy-mode = "rgmii";
+                       clocks = <&cpg CPG_MOD R9A08G045_ETH0_CLK_AXI>,
+                                <&cpg CPG_MOD R9A08G045_ETH0_CLK_CHI>,
+                                <&cpg CPG_MOD R9A08G045_ETH0_REFCLK>;
+                       clock-names = "axi", "chi", "refclk";
+                       resets = <&cpg R9A08G045_ETH0_RST_HW_N>;
+                       power-domains = <&cpg>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               eth1: ethernet@11c40000 {
+                       compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth";
+                       reg = <0 0x11c40000 0 0x10000>;
+                       interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "mux", "fil", "arp_ns";
+                       phy-mode = "rgmii";
+                       clocks = <&cpg CPG_MOD R9A08G045_ETH1_CLK_AXI>,
+                                <&cpg CPG_MOD R9A08G045_ETH1_CLK_CHI>,
+                                <&cpg CPG_MOD R9A08G045_ETH1_REFCLK>;
+                       clock-names = "axi", "chi", "refclk";
+                       resets = <&cpg R9A08G045_ETH1_RST_HW_N>;
+                       power-domains = <&cpg>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
                gic: interrupt-controller@12400000 {
                        compatible = "arm,gic-v3";
                        #interrupt-cells = <3>;