usb: dwc3: qcom: Rename hs_phy_irq to qusb2_phy_irq

For wakeup to work, driver needs to enable interrupts that depict what is
happening on the DP/DM lines. On QUSB targets, this is identified by
qusb2_phy whereas on SoCs using Femto PHY, separate {dp,dm}_hs_phy_irq's
are used instead.

The implementation incorrectly names qusb2_phy interrupts as "hs_phy_irq".
Clean this up so that driver would be using only qusb2/(dp & dm) for wakeup
purposes.

For devices running older kernels, this won't break any functionality
because the interrupt configurations in QUSB2 PHY based SoCs is done
by configuring QUSB2PHY_INTR_CTRL register in PHY address space and it was
never armed properly right from the start.

Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
Link: https://lore.kernel.org/r/20231227091951.685-3-quic_kriskura@quicinc.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c
index fdf6d5d3c2ada4357bcf1a0156410e4fc0809cfa..dbd6a5b2b2892e50098c1c752a822b8036bdfe98 100644 (file)
--- a/drivers/usb/dwc3/dwc3-qcom.c
+++ b/drivers/usb/dwc3/dwc3-qcom.c
@@ -57,7 +57,7 @@ struct dwc3_acpi_pdata {
        u32                     qscratch_base_offset;
        u32                     qscratch_base_size;
        u32                     dwc3_core_base_size;
-       int                     hs_phy_irq_index;
+       int                     qusb2_phy_irq_index;
        int                     dp_hs_phy_irq_index;
        int                     dm_hs_phy_irq_index;
        int                     ss_phy_irq_index;
@@ -73,7 +73,7 @@ struct dwc3_qcom {
        int                     num_clocks;
        struct reset_control    *resets;
 
-       int                     hs_phy_irq;
+       int                     qusb2_phy_irq;
        int                     dp_hs_phy_irq;
        int                     dm_hs_phy_irq;
        int                     ss_phy_irq;
@@ -372,7 +372,7 @@ static void dwc3_qcom_disable_wakeup_irq(int irq)
 
 static void dwc3_qcom_disable_interrupts(struct dwc3_qcom *qcom)
 {
-       dwc3_qcom_disable_wakeup_irq(qcom->hs_phy_irq);
+       dwc3_qcom_disable_wakeup_irq(qcom->qusb2_phy_irq);
 
        if (qcom->usb2_speed == USB_SPEED_LOW) {
                dwc3_qcom_disable_wakeup_irq(qcom->dm_hs_phy_irq);
@@ -389,7 +389,7 @@ static void dwc3_qcom_disable_interrupts(struct dwc3_qcom *qcom)
 
 static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom)
 {
-       dwc3_qcom_enable_wakeup_irq(qcom->hs_phy_irq, 0);
+       dwc3_qcom_enable_wakeup_irq(qcom->qusb2_phy_irq, 0);
 
        /*
         * Configure DP/DM line interrupts based on the USB2 device attached to
@@ -542,19 +542,19 @@ static int dwc3_qcom_setup_irq(struct platform_device *pdev)
        int irq;
        int ret;
 
-       irq = dwc3_qcom_get_irq(pdev, "hs_phy_irq",
-                               pdata ? pdata->hs_phy_irq_index : -1);
+       irq = dwc3_qcom_get_irq(pdev, "qusb2_phy",
+                               pdata ? pdata->qusb2_phy_irq_index : -1);
        if (irq > 0) {
                /* Keep wakeup interrupts disabled until suspend */
                ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
                                        qcom_dwc3_resume_irq,
                                        IRQF_ONESHOT | IRQF_NO_AUTOEN,
-                                       "qcom_dwc3 HS", qcom);
+                                       "qcom_dwc3 QUSB2", qcom);
                if (ret) {
-                       dev_err(qcom->dev, "hs_phy_irq failed: %d\n", ret);
+                       dev_err(qcom->dev, "qusb2_phy_irq failed: %d\n", ret);
                        return ret;
                }
-               qcom->hs_phy_irq = irq;
+               qcom->qusb2_phy_irq = irq;
        }
 
        irq = dwc3_qcom_get_irq(pdev, "dp_hs_phy_irq",
@@ -1058,7 +1058,7 @@ static const struct dwc3_acpi_pdata sdm845_acpi_pdata = {
        .qscratch_base_offset = SDM845_QSCRATCH_BASE_OFFSET,
        .qscratch_base_size = SDM845_QSCRATCH_SIZE,
        .dwc3_core_base_size = SDM845_DWC3_CORE_SIZE,
-       .hs_phy_irq_index = 1,
+       .qusb2_phy_irq_index = 1,
        .dp_hs_phy_irq_index = 4,
        .dm_hs_phy_irq_index = 3,
        .ss_phy_irq_index = 2
@@ -1068,7 +1068,7 @@ static const struct dwc3_acpi_pdata sdm845_acpi_urs_pdata = {
        .qscratch_base_offset = SDM845_QSCRATCH_BASE_OFFSET,
        .qscratch_base_size = SDM845_QSCRATCH_SIZE,
        .dwc3_core_base_size = SDM845_DWC3_CORE_SIZE,
-       .hs_phy_irq_index = 1,
+       .qusb2_phy_irq_index = 1,
        .dp_hs_phy_irq_index = 4,
        .dm_hs_phy_irq_index = 3,
        .ss_phy_irq_index = 2,