S: Supported
T: git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git sh-pfc
F: Documentation/devicetree/bindings/pinctrl/renesas,*
-F: drivers/pinctrl/pinctrl-rz*
F: drivers/pinctrl/sh-pfc/
PIN CONTROLLER - SAMSUNG
select GENERIC_IRQ_CHIP
select MFD_SYSCON
-config PINCTRL_RZA1
- bool "Renesas RZ/A1 gpio and pinctrl driver"
- depends on OF
- depends on ARCH_R7S72100 || COMPILE_TEST
- select GPIOLIB
- select GENERIC_PINCTRL_GROUPS
- select GENERIC_PINMUX_FUNCTIONS
- select GENERIC_PINCONF
- help
- This selects pinctrl driver for Renesas RZ/A1 platforms.
-
-config PINCTRL_RZA2
- bool "Renesas RZ/A2 gpio and pinctrl driver"
- depends on OF
- depends on ARCH_R7S9210 || COMPILE_TEST
- select GPIOLIB
- select GENERIC_PINCTRL_GROUPS
- select GENERIC_PINMUX_FUNCTIONS
- select GENERIC_PINCONF
- help
- This selects GPIO and pinctrl driver for Renesas RZ/A2 platforms.
-
-config PINCTRL_RZN1
- bool "Renesas RZ/N1 pinctrl driver"
- depends on OF
- depends on ARCH_RZN1 || COMPILE_TEST
- select GENERIC_PINCTRL_GROUPS
- select GENERIC_PINMUX_FUNCTIONS
- select GENERIC_PINCONF
- help
- This selects pinctrl driver for Renesas RZ/N1 devices.
-
config PINCTRL_SINGLE
tristate "One-register-per-pin type device tree based pinctrl driver"
depends on OF
obj-$(CONFIG_PINCTRL_PIC32) += pinctrl-pic32.o
obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o
obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
-obj-$(CONFIG_PINCTRL_RZA1) += pinctrl-rza1.o
-obj-$(CONFIG_PINCTRL_RZA2) += pinctrl-rza2.o
-obj-$(CONFIG_PINCTRL_RZN1) += pinctrl-rzn1.o
obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
obj-$(CONFIG_PINCTRL_SIRF) += sirf/
obj-$(CONFIG_PINCTRL_SX150X) += pinctrl-sx150x.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Combined GPIO and pin controller support for Renesas RZ/A1 (r7s72100) SoC
- *
- * Copyright (C) 2017 Jacopo Mondi
- */
-
-/*
- * This pin controller/gpio combined driver supports Renesas devices of RZ/A1
- * family.
- * This includes SoCs which are sub- or super- sets of this particular line,
- * as RZ/A1H (r7s721000), RZ/A1M (r7s721010) and RZ/A1L (r7s721020).
- */
-
-#include <linux/bitops.h>
-#include <linux/err.h>
-#include <linux/gpio/driver.h>
-#include <linux/init.h>
-#include <linux/ioport.h>
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/pinctrl/pinconf-generic.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/pinctrl/pinmux.h>
-#include <linux/slab.h>
-
-#include "core.h"
-#include "devicetree.h"
-#include "pinconf.h"
-#include "pinmux.h"
-
-#define DRIVER_NAME "pinctrl-rza1"
-
-#define RZA1_P_REG 0x0000
-#define RZA1_PPR_REG 0x0200
-#define RZA1_PM_REG 0x0300
-#define RZA1_PMC_REG 0x0400
-#define RZA1_PFC_REG 0x0500
-#define RZA1_PFCE_REG 0x0600
-#define RZA1_PFCEA_REG 0x0a00
-#define RZA1_PIBC_REG 0x4000
-#define RZA1_PBDC_REG 0x4100
-#define RZA1_PIPC_REG 0x4200
-
-#define RZA1_ADDR(mem, reg, port) ((mem) + (reg) + ((port) * 4))
-
-#define RZA1_NPORTS 12
-#define RZA1_PINS_PER_PORT 16
-#define RZA1_NPINS (RZA1_PINS_PER_PORT * RZA1_NPORTS)
-#define RZA1_PIN_ID_TO_PORT(id) ((id) / RZA1_PINS_PER_PORT)
-#define RZA1_PIN_ID_TO_PIN(id) ((id) % RZA1_PINS_PER_PORT)
-
-/*
- * Use 16 lower bits [15:0] for pin identifier
- * Use 16 higher bits [31:16] for pin mux function
- */
-#define MUX_PIN_ID_MASK GENMASK(15, 0)
-#define MUX_FUNC_MASK GENMASK(31, 16)
-
-#define MUX_FUNC_OFFS 16
-#define MUX_FUNC(pinconf) \
- ((pinconf & MUX_FUNC_MASK) >> MUX_FUNC_OFFS)
-#define MUX_FUNC_PFC_MASK BIT(0)
-#define MUX_FUNC_PFCE_MASK BIT(1)
-#define MUX_FUNC_PFCEA_MASK BIT(2)
-
-/* Pin mux flags */
-#define MUX_FLAGS_BIDIR BIT(0)
-#define MUX_FLAGS_SWIO_INPUT BIT(1)
-#define MUX_FLAGS_SWIO_OUTPUT BIT(2)
-
-/* ----------------------------------------------------------------------------
- * RZ/A1 pinmux flags
- */
-
-/*
- * rza1_bidir_pin - describe a single pin that needs bidir flag applied.
- */
-struct rza1_bidir_pin {
- u8 pin: 4;
- u8 func: 4;
-};
-
-/*
- * rza1_bidir_entry - describe a list of pins that needs bidir flag applied.
- * Each struct rza1_bidir_entry describes a port.
- */
-struct rza1_bidir_entry {
- const unsigned int npins;
- const struct rza1_bidir_pin *pins;
-};
-
-/*
- * rza1_swio_pin - describe a single pin that needs swio flag applied.
- */
-struct rza1_swio_pin {
- u16 pin: 4;
- u16 port: 4;
- u16 func: 4;
- u16 input: 1;
-};
-
-/*
- * rza1_swio_entry - describe a list of pins that needs swio flag applied
- */
-struct rza1_swio_entry {
- const unsigned int npins;
- const struct rza1_swio_pin *pins;
-};
-
-/*
- * rza1_pinmux_conf - group together bidir and swio pinmux flag tables
- */
-struct rza1_pinmux_conf {
- const struct rza1_bidir_entry *bidir_entries;
- const struct rza1_swio_entry *swio_entries;
-};
-
-/* ----------------------------------------------------------------------------
- * RZ/A1H (r7s72100) pinmux flags
- */
-
-static const struct rza1_bidir_pin rza1h_bidir_pins_p1[] = {
- { .pin = 0, .func = 1 },
- { .pin = 1, .func = 1 },
- { .pin = 2, .func = 1 },
- { .pin = 3, .func = 1 },
- { .pin = 4, .func = 1 },
- { .pin = 5, .func = 1 },
- { .pin = 6, .func = 1 },
- { .pin = 7, .func = 1 },
-};
-
-static const struct rza1_bidir_pin rza1h_bidir_pins_p2[] = {
- { .pin = 0, .func = 1 },
- { .pin = 1, .func = 1 },
- { .pin = 2, .func = 1 },
- { .pin = 3, .func = 1 },
- { .pin = 4, .func = 1 },
- { .pin = 0, .func = 4 },
- { .pin = 1, .func = 4 },
- { .pin = 2, .func = 4 },
- { .pin = 3, .func = 4 },
- { .pin = 5, .func = 1 },
- { .pin = 6, .func = 1 },
- { .pin = 7, .func = 1 },
- { .pin = 8, .func = 1 },
- { .pin = 9, .func = 1 },
- { .pin = 10, .func = 1 },
- { .pin = 11, .func = 1 },
- { .pin = 12, .func = 1 },
- { .pin = 13, .func = 1 },
- { .pin = 14, .func = 1 },
- { .pin = 15, .func = 1 },
- { .pin = 12, .func = 4 },
- { .pin = 13, .func = 4 },
- { .pin = 14, .func = 4 },
- { .pin = 15, .func = 4 },
-};
-
-static const struct rza1_bidir_pin rza1h_bidir_pins_p3[] = {
- { .pin = 3, .func = 2 },
- { .pin = 10, .func = 7 },
- { .pin = 11, .func = 7 },
- { .pin = 13, .func = 7 },
- { .pin = 14, .func = 7 },
- { .pin = 15, .func = 7 },
- { .pin = 10, .func = 8 },
- { .pin = 11, .func = 8 },
- { .pin = 13, .func = 8 },
- { .pin = 14, .func = 8 },
- { .pin = 15, .func = 8 },
-};
-
-static const struct rza1_bidir_pin rza1h_bidir_pins_p4[] = {
- { .pin = 0, .func = 8 },
- { .pin = 1, .func = 8 },
- { .pin = 2, .func = 8 },
- { .pin = 3, .func = 8 },
- { .pin = 10, .func = 3 },
- { .pin = 11, .func = 3 },
- { .pin = 13, .func = 3 },
- { .pin = 14, .func = 3 },
- { .pin = 15, .func = 3 },
- { .pin = 10, .func = 4 },
- { .pin = 11, .func = 4 },
- { .pin = 13, .func = 4 },
- { .pin = 14, .func = 4 },
- { .pin = 15, .func = 4 },
- { .pin = 12, .func = 5 },
- { .pin = 13, .func = 5 },
- { .pin = 14, .func = 5 },
- { .pin = 15, .func = 5 },
-};
-
-static const struct rza1_bidir_pin rza1h_bidir_pins_p6[] = {
- { .pin = 0, .func = 1 },
- { .pin = 1, .func = 1 },
- { .pin = 2, .func = 1 },
- { .pin = 3, .func = 1 },
- { .pin = 4, .func = 1 },
- { .pin = 5, .func = 1 },
- { .pin = 6, .func = 1 },
- { .pin = 7, .func = 1 },
- { .pin = 8, .func = 1 },
- { .pin = 9, .func = 1 },
- { .pin = 10, .func = 1 },
- { .pin = 11, .func = 1 },
- { .pin = 12, .func = 1 },
- { .pin = 13, .func = 1 },
- { .pin = 14, .func = 1 },
- { .pin = 15, .func = 1 },
-};
-
-static const struct rza1_bidir_pin rza1h_bidir_pins_p7[] = {
- { .pin = 13, .func = 3 },
-};
-
-static const struct rza1_bidir_pin rza1h_bidir_pins_p8[] = {
- { .pin = 8, .func = 3 },
- { .pin = 9, .func = 3 },
- { .pin = 10, .func = 3 },
- { .pin = 11, .func = 3 },
- { .pin = 14, .func = 2 },
- { .pin = 15, .func = 2 },
- { .pin = 14, .func = 3 },
- { .pin = 15, .func = 3 },
-};
-
-static const struct rza1_bidir_pin rza1h_bidir_pins_p9[] = {
- { .pin = 0, .func = 2 },
- { .pin = 1, .func = 2 },
- { .pin = 4, .func = 2 },
- { .pin = 5, .func = 2 },
- { .pin = 6, .func = 2 },
- { .pin = 7, .func = 2 },
-};
-
-static const struct rza1_bidir_pin rza1h_bidir_pins_p11[] = {
- { .pin = 6, .func = 2 },
- { .pin = 7, .func = 2 },
- { .pin = 9, .func = 2 },
- { .pin = 6, .func = 4 },
- { .pin = 7, .func = 4 },
- { .pin = 9, .func = 4 },
- { .pin = 10, .func = 2 },
- { .pin = 11, .func = 2 },
- { .pin = 10, .func = 4 },
- { .pin = 11, .func = 4 },
- { .pin = 12, .func = 4 },
- { .pin = 13, .func = 4 },
- { .pin = 14, .func = 4 },
- { .pin = 15, .func = 4 },
-};
-
-static const struct rza1_swio_pin rza1h_swio_pins[] = {
- { .port = 2, .pin = 7, .func = 4, .input = 0 },
- { .port = 2, .pin = 11, .func = 4, .input = 0 },
- { .port = 3, .pin = 7, .func = 3, .input = 0 },
- { .port = 3, .pin = 7, .func = 8, .input = 0 },
- { .port = 4, .pin = 7, .func = 5, .input = 0 },
- { .port = 4, .pin = 7, .func = 11, .input = 0 },
- { .port = 4, .pin = 15, .func = 6, .input = 0 },
- { .port = 5, .pin = 0, .func = 1, .input = 1 },
- { .port = 5, .pin = 1, .func = 1, .input = 1 },
- { .port = 5, .pin = 2, .func = 1, .input = 1 },
- { .port = 5, .pin = 3, .func = 1, .input = 1 },
- { .port = 5, .pin = 4, .func = 1, .input = 1 },
- { .port = 5, .pin = 5, .func = 1, .input = 1 },
- { .port = 5, .pin = 6, .func = 1, .input = 1 },
- { .port = 5, .pin = 7, .func = 1, .input = 1 },
- { .port = 7, .pin = 4, .func = 6, .input = 0 },
- { .port = 7, .pin = 11, .func = 2, .input = 0 },
- { .port = 8, .pin = 10, .func = 8, .input = 0 },
- { .port = 10, .pin = 15, .func = 2, .input = 0 },
-};
-
-static const struct rza1_bidir_entry rza1h_bidir_entries[RZA1_NPORTS] = {
- [1] = { ARRAY_SIZE(rza1h_bidir_pins_p1), rza1h_bidir_pins_p1 },
- [2] = { ARRAY_SIZE(rza1h_bidir_pins_p2), rza1h_bidir_pins_p2 },
- [3] = { ARRAY_SIZE(rza1h_bidir_pins_p3), rza1h_bidir_pins_p3 },
- [4] = { ARRAY_SIZE(rza1h_bidir_pins_p4), rza1h_bidir_pins_p4 },
- [6] = { ARRAY_SIZE(rza1h_bidir_pins_p6), rza1h_bidir_pins_p6 },
- [7] = { ARRAY_SIZE(rza1h_bidir_pins_p7), rza1h_bidir_pins_p7 },
- [8] = { ARRAY_SIZE(rza1h_bidir_pins_p8), rza1h_bidir_pins_p8 },
- [9] = { ARRAY_SIZE(rza1h_bidir_pins_p9), rza1h_bidir_pins_p9 },
- [11] = { ARRAY_SIZE(rza1h_bidir_pins_p11), rza1h_bidir_pins_p11 },
-};
-
-static const struct rza1_swio_entry rza1h_swio_entries[] = {
- [0] = { ARRAY_SIZE(rza1h_swio_pins), rza1h_swio_pins },
-};
-
-/* RZ/A1H (r7s72100x) pinmux flags table */
-static const struct rza1_pinmux_conf rza1h_pmx_conf = {
- .bidir_entries = rza1h_bidir_entries,
- .swio_entries = rza1h_swio_entries,
-};
-
-/* ----------------------------------------------------------------------------
- * RZ/A1L (r7s72102) pinmux flags
- */
-
-static const struct rza1_bidir_pin rza1l_bidir_pins_p1[] = {
- { .pin = 0, .func = 1 },
- { .pin = 1, .func = 1 },
- { .pin = 2, .func = 1 },
- { .pin = 3, .func = 1 },
- { .pin = 4, .func = 1 },
- { .pin = 5, .func = 1 },
- { .pin = 6, .func = 1 },
- { .pin = 7, .func = 1 },
-};
-
-static const struct rza1_bidir_pin rza1l_bidir_pins_p3[] = {
- { .pin = 0, .func = 2 },
- { .pin = 1, .func = 2 },
- { .pin = 2, .func = 2 },
- { .pin = 4, .func = 2 },
- { .pin = 5, .func = 2 },
- { .pin = 10, .func = 2 },
- { .pin = 11, .func = 2 },
- { .pin = 12, .func = 2 },
- { .pin = 13, .func = 2 },
-};
-
-static const struct rza1_bidir_pin rza1l_bidir_pins_p4[] = {
- { .pin = 1, .func = 4 },
- { .pin = 2, .func = 2 },
- { .pin = 3, .func = 2 },
- { .pin = 6, .func = 2 },
- { .pin = 7, .func = 2 },
-};
-
-static const struct rza1_bidir_pin rza1l_bidir_pins_p5[] = {
- { .pin = 0, .func = 1 },
- { .pin = 1, .func = 1 },
- { .pin = 2, .func = 1 },
- { .pin = 3, .func = 1 },
- { .pin = 4, .func = 1 },
- { .pin = 5, .func = 1 },
- { .pin = 6, .func = 1 },
- { .pin = 7, .func = 1 },
- { .pin = 8, .func = 1 },
- { .pin = 9, .func = 1 },
- { .pin = 10, .func = 1 },
- { .pin = 11, .func = 1 },
- { .pin = 12, .func = 1 },
- { .pin = 13, .func = 1 },
- { .pin = 14, .func = 1 },
- { .pin = 15, .func = 1 },
- { .pin = 0, .func = 2 },
- { .pin = 1, .func = 2 },
- { .pin = 2, .func = 2 },
- { .pin = 3, .func = 2 },
-};
-
-static const struct rza1_bidir_pin rza1l_bidir_pins_p6[] = {
- { .pin = 0, .func = 1 },
- { .pin = 1, .func = 1 },
- { .pin = 2, .func = 1 },
- { .pin = 3, .func = 1 },
- { .pin = 4, .func = 1 },
- { .pin = 5, .func = 1 },
- { .pin = 6, .func = 1 },
- { .pin = 7, .func = 1 },
- { .pin = 8, .func = 1 },
- { .pin = 9, .func = 1 },
- { .pin = 10, .func = 1 },
- { .pin = 11, .func = 1 },
- { .pin = 12, .func = 1 },
- { .pin = 13, .func = 1 },
- { .pin = 14, .func = 1 },
- { .pin = 15, .func = 1 },
-};
-
-static const struct rza1_bidir_pin rza1l_bidir_pins_p7[] = {
- { .pin = 2, .func = 2 },
- { .pin = 3, .func = 2 },
- { .pin = 5, .func = 2 },
- { .pin = 6, .func = 2 },
- { .pin = 7, .func = 2 },
- { .pin = 2, .func = 3 },
- { .pin = 3, .func = 3 },
- { .pin = 5, .func = 3 },
- { .pin = 6, .func = 3 },
- { .pin = 7, .func = 3 },
-};
-
-static const struct rza1_bidir_pin rza1l_bidir_pins_p9[] = {
- { .pin = 1, .func = 2 },
- { .pin = 0, .func = 3 },
- { .pin = 1, .func = 3 },
- { .pin = 3, .func = 3 },
- { .pin = 4, .func = 3 },
- { .pin = 5, .func = 3 },
-};
-
-static const struct rza1_swio_pin rza1l_swio_pins[] = {
- { .port = 2, .pin = 8, .func = 2, .input = 0 },
- { .port = 5, .pin = 6, .func = 3, .input = 0 },
- { .port = 6, .pin = 6, .func = 3, .input = 0 },
- { .port = 6, .pin = 10, .func = 3, .input = 0 },
- { .port = 7, .pin = 10, .func = 2, .input = 0 },
- { .port = 8, .pin = 2, .func = 3, .input = 0 },
-};
-
-static const struct rza1_bidir_entry rza1l_bidir_entries[RZA1_NPORTS] = {
- [1] = { ARRAY_SIZE(rza1l_bidir_pins_p1), rza1l_bidir_pins_p1 },
- [3] = { ARRAY_SIZE(rza1l_bidir_pins_p3), rza1l_bidir_pins_p3 },
- [4] = { ARRAY_SIZE(rza1l_bidir_pins_p4), rza1l_bidir_pins_p4 },
- [5] = { ARRAY_SIZE(rza1l_bidir_pins_p4), rza1l_bidir_pins_p5 },
- [6] = { ARRAY_SIZE(rza1l_bidir_pins_p6), rza1l_bidir_pins_p6 },
- [7] = { ARRAY_SIZE(rza1l_bidir_pins_p7), rza1l_bidir_pins_p7 },
- [9] = { ARRAY_SIZE(rza1l_bidir_pins_p9), rza1l_bidir_pins_p9 },
-};
-
-static const struct rza1_swio_entry rza1l_swio_entries[] = {
- [0] = { ARRAY_SIZE(rza1l_swio_pins), rza1l_swio_pins },
-};
-
-/* RZ/A1L (r7s72102x) pinmux flags table */
-static const struct rza1_pinmux_conf rza1l_pmx_conf = {
- .bidir_entries = rza1l_bidir_entries,
- .swio_entries = rza1l_swio_entries,
-};
-
-/* ----------------------------------------------------------------------------
- * RZ/A1 types
- */
-/**
- * struct rza1_mux_conf - describes a pin multiplexing operation
- *
- * @id: the pin identifier from 0 to RZA1_NPINS
- * @port: the port where pin sits on
- * @pin: pin id
- * @mux_func: alternate function id number
- * @mux_flags: alternate function flags
- * @value: output value to set the pin to
- */
-struct rza1_mux_conf {
- u16 id;
- u8 port;
- u8 pin;
- u8 mux_func;
- u8 mux_flags;
- u8 value;
-};
-
-/**
- * struct rza1_port - describes a pin port
- *
- * This is mostly useful to lock register writes per-bank and not globally.
- *
- * @lock: protect access to HW registers
- * @id: port number
- * @base: logical address base
- * @pins: pins sitting on this port
- */
-struct rza1_port {
- spinlock_t lock;
- unsigned int id;
- void __iomem *base;
- struct pinctrl_pin_desc *pins;
-};
-
-/**
- * struct rza1_pinctrl - RZ pincontroller device
- *
- * @dev: parent device structure
- * @mutex: protect [pinctrl|pinmux]_generic functions
- * @base: logical address base
- * @nport: number of pin controller ports
- * @ports: pin controller banks
- * @pins: pin array for pinctrl core
- * @desc: pincontroller desc for pinctrl core
- * @pctl: pinctrl device
- * @data: device specific data
- */
-struct rza1_pinctrl {
- struct device *dev;
-
- struct mutex mutex;
-
- void __iomem *base;
-
- unsigned int nport;
- struct rza1_port *ports;
-
- struct pinctrl_pin_desc *pins;
- struct pinctrl_desc desc;
- struct pinctrl_dev *pctl;
-
- const void *data;
-};
-
-/* ----------------------------------------------------------------------------
- * RZ/A1 pinmux flags
- */
-static inline bool rza1_pinmux_get_bidir(unsigned int port,
- unsigned int pin,
- unsigned int func,
- const struct rza1_bidir_entry *table)
-{
- const struct rza1_bidir_entry *entry = &table[port];
- const struct rza1_bidir_pin *bidir_pin;
- unsigned int i;
-
- for (i = 0; i < entry->npins; ++i) {
- bidir_pin = &entry->pins[i];
- if (bidir_pin->pin == pin && bidir_pin->func == func)
- return true;
- }
-
- return false;
-}
-
-static inline int rza1_pinmux_get_swio(unsigned int port,
- unsigned int pin,
- unsigned int func,
- const struct rza1_swio_entry *table)
-{
- const struct rza1_swio_pin *swio_pin;
- unsigned int i;
-
-
- for (i = 0; i < table->npins; ++i) {
- swio_pin = &table->pins[i];
- if (swio_pin->port == port && swio_pin->pin == pin &&
- swio_pin->func == func)
- return swio_pin->input;
- }
-
- return -ENOENT;
-}
-
-/*
- * rza1_pinmux_get_flags() - return pinmux flags associated to a pin
- */
-static unsigned int rza1_pinmux_get_flags(unsigned int port, unsigned int pin,
- unsigned int func,
- struct rza1_pinctrl *rza1_pctl)
-
-{
- const struct rza1_pinmux_conf *pmx_conf = rza1_pctl->data;
- const struct rza1_bidir_entry *bidir_entries = pmx_conf->bidir_entries;
- const struct rza1_swio_entry *swio_entries = pmx_conf->swio_entries;
- unsigned int pmx_flags = 0;
- int ret;
-
- if (rza1_pinmux_get_bidir(port, pin, func, bidir_entries))
- pmx_flags |= MUX_FLAGS_BIDIR;
-
- ret = rza1_pinmux_get_swio(port, pin, func, swio_entries);
- if (ret == 0)
- pmx_flags |= MUX_FLAGS_SWIO_OUTPUT;
- else if (ret > 0)
- pmx_flags |= MUX_FLAGS_SWIO_INPUT;
-
- return pmx_flags;
-}
-
-/* ----------------------------------------------------------------------------
- * RZ/A1 SoC operations
- */
-
-/*
- * rza1_set_bit() - un-locked set/clear a single bit in pin configuration
- * registers
- */
-static inline void rza1_set_bit(struct rza1_port *port, unsigned int reg,
- unsigned int bit, bool set)
-{
- void __iomem *mem = RZA1_ADDR(port->base, reg, port->id);
- u16 val = ioread16(mem);
-
- if (set)
- val |= BIT(bit);
- else
- val &= ~BIT(bit);
-
- iowrite16(val, mem);
-}
-
-static inline unsigned int rza1_get_bit(struct rza1_port *port,
- unsigned int reg, unsigned int bit)
-{
- void __iomem *mem = RZA1_ADDR(port->base, reg, port->id);
-
- return ioread16(mem) & BIT(bit);
-}
-
-/**
- * rza1_pin_reset() - reset a pin to default initial state
- *
- * Reset pin state disabling input buffer and bi-directional control,
- * and configure it as input port.
- * Note that pin is now configured with direction as input but with input
- * buffer disabled. This implies the pin value cannot be read in this state.
- *
- * @port: port where pin sits on
- * @pin: pin offset
- */
-static void rza1_pin_reset(struct rza1_port *port, unsigned int pin)
-{
- unsigned long irqflags;
-
- spin_lock_irqsave(&port->lock, irqflags);
- rza1_set_bit(port, RZA1_PIBC_REG, pin, 0);
- rza1_set_bit(port, RZA1_PBDC_REG, pin, 0);
-
- rza1_set_bit(port, RZA1_PM_REG, pin, 1);
- rza1_set_bit(port, RZA1_PMC_REG, pin, 0);
- rza1_set_bit(port, RZA1_PIPC_REG, pin, 0);
- spin_unlock_irqrestore(&port->lock, irqflags);
-}
-
-/**
- * rza1_pin_set_direction() - set I/O direction on a pin in port mode
- *
- * When running in output port mode keep PBDC enabled to allow reading the
- * pin value from PPR.
- *
- * @port: port where pin sits on
- * @pin: pin offset
- * @input: input enable/disable flag
- */
-static inline void rza1_pin_set_direction(struct rza1_port *port,
- unsigned int pin, bool input)
-{
- unsigned long irqflags;
-
- spin_lock_irqsave(&port->lock, irqflags);
-
- rza1_set_bit(port, RZA1_PIBC_REG, pin, 1);
- if (input) {
- rza1_set_bit(port, RZA1_PM_REG, pin, 1);
- rza1_set_bit(port, RZA1_PBDC_REG, pin, 0);
- } else {
- rza1_set_bit(port, RZA1_PM_REG, pin, 0);
- rza1_set_bit(port, RZA1_PBDC_REG, pin, 1);
- }
-
- spin_unlock_irqrestore(&port->lock, irqflags);
-}
-
-static inline void rza1_pin_set(struct rza1_port *port, unsigned int pin,
- unsigned int value)
-{
- unsigned long irqflags;
-
- spin_lock_irqsave(&port->lock, irqflags);
- rza1_set_bit(port, RZA1_P_REG, pin, !!value);
- spin_unlock_irqrestore(&port->lock, irqflags);
-}
-
-static inline int rza1_pin_get(struct rza1_port *port, unsigned int pin)
-{
- return rza1_get_bit(port, RZA1_PPR_REG, pin);
-}
-
-/**
- * rza1_pin_mux_single() - configure pin multiplexing on a single pin
- *
- * @rza1_pctl: RZ/A1 pin controller device
- * @mux_conf: pin multiplexing descriptor
- */
-static int rza1_pin_mux_single(struct rza1_pinctrl *rza1_pctl,
- struct rza1_mux_conf *mux_conf)
-{
- struct rza1_port *port = &rza1_pctl->ports[mux_conf->port];
- unsigned int pin = mux_conf->pin;
- u8 mux_func = mux_conf->mux_func;
- u8 mux_flags = mux_conf->mux_flags;
- u8 mux_flags_from_table;
-
- rza1_pin_reset(port, pin);
-
- /* SWIO pinmux flags coming from DT are high precedence */
- mux_flags_from_table = rza1_pinmux_get_flags(port->id, pin, mux_func,
- rza1_pctl);
- if (mux_flags)
- mux_flags |= (mux_flags_from_table & MUX_FLAGS_BIDIR);
- else
- mux_flags = mux_flags_from_table;
-
- if (mux_flags & MUX_FLAGS_BIDIR)
- rza1_set_bit(port, RZA1_PBDC_REG, pin, 1);
-
- /*
- * Enable alternate function mode and select it.
- *
- * Be careful here: the pin mux sub-nodes in device tree
- * enumerate alternate functions from 1 to 8;
- * subtract 1 before using macros to match registers configuration
- * which expects numbers from 0 to 7 instead.
- *
- * ----------------------------------------------------
- * Alternate mode selection table:
- *
- * PMC PFC PFCE PFCAE (mux_func - 1)
- * 1 0 0 0 0
- * 1 1 0 0 1
- * 1 0 1 0 2
- * 1 1 1 0 3
- * 1 0 0 1 4
- * 1 1 0 1 5
- * 1 0 1 1 6
- * 1 1 1 1 7
- * ----------------------------------------------------
- */
- mux_func -= 1;
- rza1_set_bit(port, RZA1_PFC_REG, pin, mux_func & MUX_FUNC_PFC_MASK);
- rza1_set_bit(port, RZA1_PFCE_REG, pin, mux_func & MUX_FUNC_PFCE_MASK);
- rza1_set_bit(port, RZA1_PFCEA_REG, pin, mux_func & MUX_FUNC_PFCEA_MASK);
-
- /*
- * All alternate functions except a few need PIPCn = 1.
- * If PIPCn has to stay disabled (SW IO mode), configure PMn according
- * to I/O direction specified by pin configuration -after- PMC has been
- * set to one.
- */
- if (mux_flags & (MUX_FLAGS_SWIO_INPUT | MUX_FLAGS_SWIO_OUTPUT))
- rza1_set_bit(port, RZA1_PM_REG, pin,
- mux_flags & MUX_FLAGS_SWIO_INPUT);
- else
- rza1_set_bit(port, RZA1_PIPC_REG, pin, 1);
-
- rza1_set_bit(port, RZA1_PMC_REG, pin, 1);
-
- return 0;
-}
-
-/* ----------------------------------------------------------------------------
- * gpio operations
- */
-
-/**
- * rza1_gpio_request() - configure pin in port mode
- *
- * Configure a pin as gpio (port mode).
- * After reset, the pin is in input mode with input buffer disabled.
- * To use the pin as input or output, set_direction shall be called first
- *
- * @chip: gpio chip where the gpio sits on
- * @gpio: gpio offset
- */
-static int rza1_gpio_request(struct gpio_chip *chip, unsigned int gpio)
-{
- struct rza1_port *port = gpiochip_get_data(chip);
-
- rza1_pin_reset(port, gpio);
-
- return 0;
-}
-
-/**
- * rza1_gpio_disable_free() - reset a pin
- *
- * Surprisingly, disable_free a gpio, is equivalent to request it.
- * Reset pin to port mode, with input buffer disabled. This overwrites all
- * port direction settings applied with set_direction
- *
- * @chip: gpio chip where the gpio sits on
- * @gpio: gpio offset
- */
-static void rza1_gpio_free(struct gpio_chip *chip, unsigned int gpio)
-{
- struct rza1_port *port = gpiochip_get_data(chip);
-
- rza1_pin_reset(port, gpio);
-}
-
-static int rza1_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
-{
- struct rza1_port *port = gpiochip_get_data(chip);
-
- if (rza1_get_bit(port, RZA1_PM_REG, gpio))
- return GPIO_LINE_DIRECTION_IN;
-
- return GPIO_LINE_DIRECTION_OUT;
-}
-
-static int rza1_gpio_direction_input(struct gpio_chip *chip,
- unsigned int gpio)
-{
- struct rza1_port *port = gpiochip_get_data(chip);
-
- rza1_pin_set_direction(port, gpio, true);
-
- return 0;
-}
-
-static int rza1_gpio_direction_output(struct gpio_chip *chip,
- unsigned int gpio,
- int value)
-{
- struct rza1_port *port = gpiochip_get_data(chip);
-
- /* Set value before driving pin direction */
- rza1_pin_set(port, gpio, value);
- rza1_pin_set_direction(port, gpio, false);
-
- return 0;
-}
-
-/**
- * rza1_gpio_get() - read a gpio pin value
- *
- * Read gpio pin value through PPR register.
- * Requires bi-directional mode to work when reading the value of a pin
- * in output mode
- *
- * @chip: gpio chip where the gpio sits on
- * @gpio: gpio offset
- */
-static int rza1_gpio_get(struct gpio_chip *chip, unsigned int gpio)
-{
- struct rza1_port *port = gpiochip_get_data(chip);
-
- return rza1_pin_get(port, gpio);
-}
-
-static void rza1_gpio_set(struct gpio_chip *chip, unsigned int gpio,
- int value)
-{
- struct rza1_port *port = gpiochip_get_data(chip);
-
- rza1_pin_set(port, gpio, value);
-}
-
-static const struct gpio_chip rza1_gpiochip_template = {
- .request = rza1_gpio_request,
- .free = rza1_gpio_free,
- .get_direction = rza1_gpio_get_direction,
- .direction_input = rza1_gpio_direction_input,
- .direction_output = rza1_gpio_direction_output,
- .get = rza1_gpio_get,
- .set = rza1_gpio_set,
-};
-/* ----------------------------------------------------------------------------
- * pinctrl operations
- */
-
-/**
- * rza1_dt_node_pin_count() - Count number of pins in a dt node or in all its
- * children sub-nodes
- *
- * @np: device tree node to parse
- */
-static int rza1_dt_node_pin_count(struct device_node *np)
-{
- struct device_node *child;
- struct property *of_pins;
- unsigned int npins;
-
- of_pins = of_find_property(np, "pinmux", NULL);
- if (of_pins)
- return of_pins->length / sizeof(u32);
-
- npins = 0;
- for_each_child_of_node(np, child) {
- of_pins = of_find_property(child, "pinmux", NULL);
- if (!of_pins) {
- of_node_put(child);
- return -EINVAL;
- }
-
- npins += of_pins->length / sizeof(u32);
- }
-
- return npins;
-}
-
-/**
- * rza1_parse_pmx_function() - parse a pin mux sub-node
- *
- * @rza1_pctl: RZ/A1 pin controller device
- * @np: of pmx sub-node
- * @mux_confs: array of pin mux configurations to fill with parsed info
- * @grpins: array of pin ids to mux
- */
-static int rza1_parse_pinmux_node(struct rza1_pinctrl *rza1_pctl,
- struct device_node *np,
- struct rza1_mux_conf *mux_confs,
- unsigned int *grpins)
-{
- struct pinctrl_dev *pctldev = rza1_pctl->pctl;
- char const *prop_name = "pinmux";
- unsigned long *pin_configs;
- unsigned int npin_configs;
- struct property *of_pins;
- unsigned int npins;
- u8 pinmux_flags;
- unsigned int i;
- int ret;
-
- of_pins = of_find_property(np, prop_name, NULL);
- if (!of_pins) {
- dev_dbg(rza1_pctl->dev, "Missing %s property\n", prop_name);
- return -ENOENT;
- }
- npins = of_pins->length / sizeof(u32);
-
- /*
- * Collect pin configuration properties: they apply to all pins in
- * this sub-node
- */
- ret = pinconf_generic_parse_dt_config(np, pctldev, &pin_configs,
- &npin_configs);
- if (ret) {
- dev_err(rza1_pctl->dev,
- "Unable to parse pin configuration options for %pOFn\n",
- np);
- return ret;
- }
-
- /*
- * Create a mask with pinmux flags from pin configuration;
- * very few pins (TIOC[0-4][A|B|C|D] require SWIO direction
- * specified in device tree.
- */
- pinmux_flags = 0;
- for (i = 0; i < npin_configs && pinmux_flags == 0; i++)
- switch (pinconf_to_config_param(pin_configs[i])) {
- case PIN_CONFIG_INPUT_ENABLE:
- pinmux_flags |= MUX_FLAGS_SWIO_INPUT;
- break;
- case PIN_CONFIG_OUTPUT:
- pinmux_flags |= MUX_FLAGS_SWIO_OUTPUT;
- default:
- break;
-
- }
-
- kfree(pin_configs);
-
- /* Collect pin positions and their mux settings. */
- for (i = 0; i < npins; ++i) {
- u32 of_pinconf;
- struct rza1_mux_conf *mux_conf = &mux_confs[i];
-
- ret = of_property_read_u32_index(np, prop_name, i, &of_pinconf);
- if (ret)
- return ret;
-
- mux_conf->id = of_pinconf & MUX_PIN_ID_MASK;
- mux_conf->port = RZA1_PIN_ID_TO_PORT(mux_conf->id);
- mux_conf->pin = RZA1_PIN_ID_TO_PIN(mux_conf->id);
- mux_conf->mux_func = MUX_FUNC(of_pinconf);
- mux_conf->mux_flags = pinmux_flags;
-
- if (mux_conf->port >= RZA1_NPORTS ||
- mux_conf->pin >= RZA1_PINS_PER_PORT) {
- dev_err(rza1_pctl->dev,
- "Wrong port %u pin %u for %s property\n",
- mux_conf->port, mux_conf->pin, prop_name);
- return -EINVAL;
- }
-
- grpins[i] = mux_conf->id;
- }
-
- return npins;
-}
-
-/**
- * rza1_dt_node_to_map() - map a pin mux node to a function/group
- *
- * Parse and register a pin mux function.
- *
- * @pctldev: pin controller device
- * @np: device tree node to parse
- * @map: pointer to pin map (output)
- * @num_maps: number of collected maps (output)
- */
-static int rza1_dt_node_to_map(struct pinctrl_dev *pctldev,
- struct device_node *np,
- struct pinctrl_map **map,
- unsigned int *num_maps)
-{
- struct rza1_pinctrl *rza1_pctl = pinctrl_dev_get_drvdata(pctldev);
- struct rza1_mux_conf *mux_confs, *mux_conf;
- unsigned int *grpins, *grpin;
- struct device_node *child;
- const char *grpname;
- const char **fngrps;
- int ret, npins;
- int gsel, fsel;
-
- npins = rza1_dt_node_pin_count(np);
- if (npins < 0) {
- dev_err(rza1_pctl->dev, "invalid pinmux node structure\n");
- return -EINVAL;
- }
-
- /*
- * Functions are made of 1 group only;
- * in fact, functions and groups are identical for this pin controller
- * except that functions carry an array of per-pin mux configuration
- * settings.
- */
- mux_confs = devm_kcalloc(rza1_pctl->dev, npins, sizeof(*mux_confs),
- GFP_KERNEL);
- grpins = devm_kcalloc(rza1_pctl->dev, npins, sizeof(*grpins),
- GFP_KERNEL);
- fngrps = devm_kzalloc(rza1_pctl->dev, sizeof(*fngrps), GFP_KERNEL);
-
- if (!mux_confs || !grpins || !fngrps)
- return -ENOMEM;
-
- /*
- * Parse the pinmux node.
- * If the node does not contain "pinmux" property (-ENOENT)
- * that property shall be specified in all its children sub-nodes.
- */
- mux_conf = &mux_confs[0];
- grpin = &grpins[0];
-
- ret = rza1_parse_pinmux_node(rza1_pctl, np, mux_conf, grpin);
- if (ret == -ENOENT)
- for_each_child_of_node(np, child) {
- ret = rza1_parse_pinmux_node(rza1_pctl, child, mux_conf,
- grpin);
- if (ret < 0) {
- of_node_put(child);
- return ret;
- }
-
- grpin += ret;
- mux_conf += ret;
- }
- else if (ret < 0)
- return ret;
-
- /* Register pin group and function name to pinctrl_generic */
- grpname = np->name;
- fngrps[0] = grpname;
-
- mutex_lock(&rza1_pctl->mutex);
- gsel = pinctrl_generic_add_group(pctldev, grpname, grpins, npins,
- NULL);
- if (gsel < 0) {
- mutex_unlock(&rza1_pctl->mutex);
- return gsel;
- }
-
- fsel = pinmux_generic_add_function(pctldev, grpname, fngrps, 1,
- mux_confs);
- if (fsel < 0) {
- ret = fsel;
- goto remove_group;
- }
-
- dev_info(rza1_pctl->dev, "Parsed function and group %s with %d pins\n",
- grpname, npins);
-
- /* Create map where to retrieve function and mux settings from */
- *num_maps = 0;
- *map = kzalloc(sizeof(**map), GFP_KERNEL);
- if (!*map) {
- ret = -ENOMEM;
- goto remove_function;
- }
-
- (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
- (*map)->data.mux.group = np->name;
- (*map)->data.mux.function = np->name;
- *num_maps = 1;
- mutex_unlock(&rza1_pctl->mutex);
-
- return 0;
-
-remove_function:
- pinmux_generic_remove_function(pctldev, fsel);
-
-remove_group:
- pinctrl_generic_remove_group(pctldev, gsel);
- mutex_unlock(&rza1_pctl->mutex);
-
- dev_info(rza1_pctl->dev, "Unable to parse function and group %s\n",
- grpname);
-
- return ret;
-}
-
-static void rza1_dt_free_map(struct pinctrl_dev *pctldev,
- struct pinctrl_map *map, unsigned int num_maps)
-{
- kfree(map);
-}
-
-static const struct pinctrl_ops rza1_pinctrl_ops = {
- .get_groups_count = pinctrl_generic_get_group_count,
- .get_group_name = pinctrl_generic_get_group_name,
- .get_group_pins = pinctrl_generic_get_group_pins,
- .dt_node_to_map = rza1_dt_node_to_map,
- .dt_free_map = rza1_dt_free_map,
-};
-
-/* ----------------------------------------------------------------------------
- * pinmux operations
- */
-
-/**
- * rza1_set_mux() - retrieve pins from a group and apply their mux settings
- *
- * @pctldev: pin controller device
- * @selector: function selector
- * @group: group selector
- */
-static int rza1_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
- unsigned int group)
-{
- struct rza1_pinctrl *rza1_pctl = pinctrl_dev_get_drvdata(pctldev);
- struct rza1_mux_conf *mux_confs;
- struct function_desc *func;
- struct group_desc *grp;
- int i;
-
- grp = pinctrl_generic_get_group(pctldev, group);
- if (!grp)
- return -EINVAL;
-
- func = pinmux_generic_get_function(pctldev, selector);
- if (!func)
- return -EINVAL;
-
- mux_confs = (struct rza1_mux_conf *)func->data;
- for (i = 0; i < grp->num_pins; ++i) {
- int ret;
-
- ret = rza1_pin_mux_single(rza1_pctl, &mux_confs[i]);
- if (ret)
- return ret;
- }
-
- return 0;
-}
-
-static const struct pinmux_ops rza1_pinmux_ops = {
- .get_functions_count = pinmux_generic_get_function_count,
- .get_function_name = pinmux_generic_get_function_name,
- .get_function_groups = pinmux_generic_get_function_groups,
- .set_mux = rza1_set_mux,
- .strict = true,
-};
-
-/* ----------------------------------------------------------------------------
- * RZ/A1 pin controller driver operations
- */
-
-static unsigned int rza1_count_gpio_chips(struct device_node *np)
-{
- struct device_node *child;
- unsigned int count = 0;
-
- for_each_child_of_node(np, child) {
- if (!of_property_read_bool(child, "gpio-controller"))
- continue;
-
- count++;
- }
-
- return count;
-}
-
-/**
- * rza1_parse_gpiochip() - parse and register a gpio chip and pin range
- *
- * The gpio controller subnode shall provide a "gpio-ranges" list property as
- * defined by gpio device tree binding documentation.
- *
- * @rza1_pctl: RZ/A1 pin controller device
- * @np: of gpio-controller node
- * @chip: gpio chip to register to gpiolib
- * @range: pin range to register to pinctrl core
- */
-static int rza1_parse_gpiochip(struct rza1_pinctrl *rza1_pctl,
- struct device_node *np,
- struct gpio_chip *chip,
- struct pinctrl_gpio_range *range)
-{
- const char *list_name = "gpio-ranges";
- struct of_phandle_args of_args;
- unsigned int gpioport;
- u32 pinctrl_base;
- int ret;
-
- ret = of_parse_phandle_with_fixed_args(np, list_name, 3, 0, &of_args);
- if (ret) {
- dev_err(rza1_pctl->dev, "Unable to parse %s list property\n",
- list_name);
- return ret;
- }
-
- /*
- * Find out on which port this gpio-chip maps to by inspecting the
- * second argument of the "gpio-ranges" property.
- */
- pinctrl_base = of_args.args[1];
- gpioport = RZA1_PIN_ID_TO_PORT(pinctrl_base);
- if (gpioport >= RZA1_NPORTS) {
- dev_err(rza1_pctl->dev,
- "Invalid values in property %s\n", list_name);
- return -EINVAL;
- }
-
- *chip = rza1_gpiochip_template;
- chip->base = -1;
- chip->label = devm_kasprintf(rza1_pctl->dev, GFP_KERNEL, "%pOFn",
- np);
- if (!chip->label)
- return -ENOMEM;
-
- chip->ngpio = of_args.args[2];
- chip->of_node = np;
- chip->parent = rza1_pctl->dev;
-
- range->id = gpioport;
- range->name = chip->label;
- range->pin_base = range->base = pinctrl_base;
- range->npins = of_args.args[2];
- range->gc = chip;
-
- ret = devm_gpiochip_add_data(rza1_pctl->dev, chip,
- &rza1_pctl->ports[gpioport]);
- if (ret)
- return ret;
-
- pinctrl_add_gpio_range(rza1_pctl->pctl, range);
-
- dev_dbg(rza1_pctl->dev, "Parsed gpiochip %s with %d pins\n",
- chip->label, chip->ngpio);
-
- return 0;
-}
-
-/**
- * rza1_gpio_register() - parse DT to collect gpio-chips and gpio-ranges
- *
- * @rza1_pctl: RZ/A1 pin controller device
- */
-static int rza1_gpio_register(struct rza1_pinctrl *rza1_pctl)
-{
- struct device_node *np = rza1_pctl->dev->of_node;
- struct pinctrl_gpio_range *gpio_ranges;
- struct gpio_chip *gpio_chips;
- struct device_node *child;
- unsigned int ngpiochips;
- unsigned int i;
- int ret;
-
- ngpiochips = rza1_count_gpio_chips(np);
- if (ngpiochips == 0) {
- dev_dbg(rza1_pctl->dev, "No gpiochip registered\n");
- return 0;
- }
-
- gpio_chips = devm_kcalloc(rza1_pctl->dev, ngpiochips,
- sizeof(*gpio_chips), GFP_KERNEL);
- gpio_ranges = devm_kcalloc(rza1_pctl->dev, ngpiochips,
- sizeof(*gpio_ranges), GFP_KERNEL);
- if (!gpio_chips || !gpio_ranges)
- return -ENOMEM;
-
- i = 0;
- for_each_child_of_node(np, child) {
- if (!of_property_read_bool(child, "gpio-controller"))
- continue;
-
- ret = rza1_parse_gpiochip(rza1_pctl, child, &gpio_chips[i],
- &gpio_ranges[i]);
- if (ret) {
- of_node_put(child);
- return ret;
- }
-
- ++i;
- }
-
- dev_info(rza1_pctl->dev, "Registered %u gpio controllers\n", i);
-
- return 0;
-}
-
-/**
- * rza1_pinctrl_register() - Enumerate pins, ports and gpiochips; register
- * them to pinctrl and gpio cores.
- *
- * @rza1_pctl: RZ/A1 pin controller device
- */
-static int rza1_pinctrl_register(struct rza1_pinctrl *rza1_pctl)
-{
- struct pinctrl_pin_desc *pins;
- struct rza1_port *ports;
- unsigned int i;
- int ret;
-
- pins = devm_kcalloc(rza1_pctl->dev, RZA1_NPINS, sizeof(*pins),
- GFP_KERNEL);
- ports = devm_kcalloc(rza1_pctl->dev, RZA1_NPORTS, sizeof(*ports),
- GFP_KERNEL);
- if (!pins || !ports)
- return -ENOMEM;
-
- rza1_pctl->pins = pins;
- rza1_pctl->desc.pins = pins;
- rza1_pctl->desc.npins = RZA1_NPINS;
- rza1_pctl->ports = ports;
-
- for (i = 0; i < RZA1_NPINS; ++i) {
- unsigned int pin = RZA1_PIN_ID_TO_PIN(i);
- unsigned int port = RZA1_PIN_ID_TO_PORT(i);
-
- pins[i].number = i;
- pins[i].name = devm_kasprintf(rza1_pctl->dev, GFP_KERNEL,
- "P%u-%u", port, pin);
- if (!pins[i].name)
- return -ENOMEM;
-
- if (i % RZA1_PINS_PER_PORT == 0) {
- /*
- * Setup ports;
- * they provide per-port lock and logical base address.
- */
- unsigned int port_id = RZA1_PIN_ID_TO_PORT(i);
-
- ports[port_id].id = port_id;
- ports[port_id].base = rza1_pctl->base;
- ports[port_id].pins = &pins[i];
- spin_lock_init(&ports[port_id].lock);
- }
- }
-
- ret = devm_pinctrl_register_and_init(rza1_pctl->dev, &rza1_pctl->desc,
- rza1_pctl, &rza1_pctl->pctl);
- if (ret) {
- dev_err(rza1_pctl->dev,
- "RZ/A1 pin controller registration failed\n");
- return ret;
- }
-
- ret = pinctrl_enable(rza1_pctl->pctl);
- if (ret) {
- dev_err(rza1_pctl->dev,
- "RZ/A1 pin controller failed to start\n");
- return ret;
- }
-
- ret = rza1_gpio_register(rza1_pctl);
- if (ret) {
- dev_err(rza1_pctl->dev, "RZ/A1 GPIO registration failed\n");
- return ret;
- }
-
- return 0;
-}
-
-static int rza1_pinctrl_probe(struct platform_device *pdev)
-{
- struct rza1_pinctrl *rza1_pctl;
- int ret;
-
- rza1_pctl = devm_kzalloc(&pdev->dev, sizeof(*rza1_pctl), GFP_KERNEL);
- if (!rza1_pctl)
- return -ENOMEM;
-
- rza1_pctl->dev = &pdev->dev;
-
- rza1_pctl->base = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(rza1_pctl->base))
- return PTR_ERR(rza1_pctl->base);
-
- mutex_init(&rza1_pctl->mutex);
-
- platform_set_drvdata(pdev, rza1_pctl);
-
- rza1_pctl->desc.name = DRIVER_NAME;
- rza1_pctl->desc.pctlops = &rza1_pinctrl_ops;
- rza1_pctl->desc.pmxops = &rza1_pinmux_ops;
- rza1_pctl->desc.owner = THIS_MODULE;
- rza1_pctl->data = of_device_get_match_data(&pdev->dev);
-
- ret = rza1_pinctrl_register(rza1_pctl);
- if (ret)
- return ret;
-
- dev_info(&pdev->dev,
- "RZ/A1 pin controller and gpio successfully registered\n");
-
- return 0;
-}
-
-static const struct of_device_id rza1_pinctrl_of_match[] = {
- {
- /* RZ/A1H, RZ/A1M */
- .compatible = "renesas,r7s72100-ports",
- .data = &rza1h_pmx_conf,
- },
- {
- /* RZ/A1L */
- .compatible = "renesas,r7s72102-ports",
- .data = &rza1l_pmx_conf,
- },
- { }
-};
-
-static struct platform_driver rza1_pinctrl_driver = {
- .driver = {
- .name = DRIVER_NAME,
- .of_match_table = rza1_pinctrl_of_match,
- },
- .probe = rza1_pinctrl_probe,
-};
-
-static int __init rza1_pinctrl_init(void)
-{
- return platform_driver_register(&rza1_pinctrl_driver);
-}
-core_initcall(rza1_pinctrl_init);
-
-MODULE_AUTHOR("Jacopo Mondi <jacopo+renesas@jmondi.org");
-MODULE_DESCRIPTION("Pin and gpio controller driver for Reneas RZ/A1 SoC");
-MODULE_LICENSE("GPL v2");
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Combined GPIO and pin controller support for Renesas RZ/A2 (R7S9210) SoC
- *
- * Copyright (C) 2018 Chris Brandt
- */
-
-/*
- * This pin controller/gpio combined driver supports Renesas devices of RZ/A2
- * family.
- */
-
-#include <linux/bitops.h>
-#include <linux/gpio/driver.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/of_device.h>
-#include <linux/pinctrl/pinmux.h>
-
-#include "core.h"
-#include "pinmux.h"
-
-#define DRIVER_NAME "pinctrl-rza2"
-
-#define RZA2_PINS_PER_PORT 8
-#define RZA2_PIN_ID_TO_PORT(id) ((id) / RZA2_PINS_PER_PORT)
-#define RZA2_PIN_ID_TO_PIN(id) ((id) % RZA2_PINS_PER_PORT)
-
-/*
- * Use 16 lower bits [15:0] for pin identifier
- * Use 16 higher bits [31:16] for pin mux function
- */
-#define MUX_PIN_ID_MASK GENMASK(15, 0)
-#define MUX_FUNC_MASK GENMASK(31, 16)
-#define MUX_FUNC_OFFS 16
-#define MUX_FUNC(pinconf) ((pinconf & MUX_FUNC_MASK) >> MUX_FUNC_OFFS)
-
-static const char port_names[] = "0123456789ABCDEFGHJKLM";
-
-struct rza2_pinctrl_priv {
- struct device *dev;
- void __iomem *base;
-
- struct pinctrl_pin_desc *pins;
- struct pinctrl_desc desc;
- struct pinctrl_dev *pctl;
- struct pinctrl_gpio_range gpio_range;
- int npins;
-};
-
-#define RZA2_PDR(port) (0x0000 + (port) * 2) /* Direction 16-bit */
-#define RZA2_PODR(port) (0x0040 + (port)) /* Output Data 8-bit */
-#define RZA2_PIDR(port) (0x0060 + (port)) /* Input Data 8-bit */
-#define RZA2_PMR(port) (0x0080 + (port)) /* Mode 8-bit */
-#define RZA2_DSCR(port) (0x0140 + (port) * 2) /* Drive 16-bit */
-#define RZA2_PFS(port, pin) (0x0200 + ((port) * 8) + (pin)) /* Fnct 8-bit */
-
-#define RZA2_PWPR 0x02ff /* Write Protect 8-bit */
-#define RZA2_PFENET 0x0820 /* Ethernet Pins 8-bit */
-#define RZA2_PPOC 0x0900 /* Dedicated Pins 32-bit */
-#define RZA2_PHMOMO 0x0980 /* Peripheral Pins 32-bit */
-#define RZA2_PCKIO 0x09d0 /* CKIO Drive 8-bit */
-
-#define RZA2_PDR_INPUT 0x02
-#define RZA2_PDR_OUTPUT 0x03
-#define RZA2_PDR_MASK 0x03
-
-#define PWPR_B0WI BIT(7) /* Bit Write Disable */
-#define PWPR_PFSWE BIT(6) /* PFS Register Write Enable */
-#define PFS_ISEL BIT(6) /* Interrupt Select */
-
-static void rza2_set_pin_function(void __iomem *pfc_base, u8 port, u8 pin,
- u8 func)
-{
- u16 mask16;
- u16 reg16;
- u8 reg8;
-
- /* Set pin to 'Non-use (Hi-z input protection)' */
- reg16 = readw(pfc_base + RZA2_PDR(port));
- mask16 = RZA2_PDR_MASK << (pin * 2);
- reg16 &= ~mask16;
- writew(reg16, pfc_base + RZA2_PDR(port));
-
- /* Temporarily switch to GPIO */
- reg8 = readb(pfc_base + RZA2_PMR(port));
- reg8 &= ~BIT(pin);
- writeb(reg8, pfc_base + RZA2_PMR(port));
-
- /* PFS Register Write Protect : OFF */
- writeb(0x00, pfc_base + RZA2_PWPR); /* B0WI=0, PFSWE=0 */
- writeb(PWPR_PFSWE, pfc_base + RZA2_PWPR); /* B0WI=0, PFSWE=1 */
-
- /* Set Pin function (interrupt disabled, ISEL=0) */
- writeb(func, pfc_base + RZA2_PFS(port, pin));
-
- /* PFS Register Write Protect : ON */
- writeb(0x00, pfc_base + RZA2_PWPR); /* B0WI=0, PFSWE=0 */
- writeb(0x80, pfc_base + RZA2_PWPR); /* B0WI=1, PFSWE=0 */
-
- /* Port Mode : Peripheral module pin functions */
- reg8 = readb(pfc_base + RZA2_PMR(port));
- reg8 |= BIT(pin);
- writeb(reg8, pfc_base + RZA2_PMR(port));
-}
-
-static void rza2_pin_to_gpio(void __iomem *pfc_base, unsigned int offset,
- u8 dir)
-{
- u8 port = RZA2_PIN_ID_TO_PORT(offset);
- u8 pin = RZA2_PIN_ID_TO_PIN(offset);
- u16 mask16;
- u16 reg16;
-
- reg16 = readw(pfc_base + RZA2_PDR(port));
- mask16 = RZA2_PDR_MASK << (pin * 2);
- reg16 &= ~mask16;
-
- if (dir)
- reg16 |= RZA2_PDR_INPUT << (pin * 2); /* pin as input */
- else
- reg16 |= RZA2_PDR_OUTPUT << (pin * 2); /* pin as output */
-
- writew(reg16, pfc_base + RZA2_PDR(port));
-}
-
-static int rza2_chip_get_direction(struct gpio_chip *chip, unsigned int offset)
-{
- struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
- u8 port = RZA2_PIN_ID_TO_PORT(offset);
- u8 pin = RZA2_PIN_ID_TO_PIN(offset);
- u16 reg16;
-
- reg16 = readw(priv->base + RZA2_PDR(port));
- reg16 = (reg16 >> (pin * 2)) & RZA2_PDR_MASK;
-
- if (reg16 == RZA2_PDR_OUTPUT)
- return GPIO_LINE_DIRECTION_OUT;
-
- if (reg16 == RZA2_PDR_INPUT)
- return GPIO_LINE_DIRECTION_IN;
-
- /*
- * This GPIO controller has a default Hi-Z state that is not input or
- * output, so force the pin to input now.
- */
- rza2_pin_to_gpio(priv->base, offset, 1);
-
- return GPIO_LINE_DIRECTION_IN;
-}
-
-static int rza2_chip_direction_input(struct gpio_chip *chip,
- unsigned int offset)
-{
- struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
-
- rza2_pin_to_gpio(priv->base, offset, 1);
-
- return 0;
-}
-
-static int rza2_chip_get(struct gpio_chip *chip, unsigned int offset)
-{
- struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
- u8 port = RZA2_PIN_ID_TO_PORT(offset);
- u8 pin = RZA2_PIN_ID_TO_PIN(offset);
-
- return !!(readb(priv->base + RZA2_PIDR(port)) & BIT(pin));
-}
-
-static void rza2_chip_set(struct gpio_chip *chip, unsigned int offset,
- int value)
-{
- struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
- u8 port = RZA2_PIN_ID_TO_PORT(offset);
- u8 pin = RZA2_PIN_ID_TO_PIN(offset);
- u8 new_value;
-
- new_value = readb(priv->base + RZA2_PODR(port));
-
- if (value)
- new_value |= BIT(pin);
- else
- new_value &= ~BIT(pin);
-
- writeb(new_value, priv->base + RZA2_PODR(port));
-}
-
-static int rza2_chip_direction_output(struct gpio_chip *chip,
- unsigned int offset, int val)
-{
- struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
-
- rza2_chip_set(chip, offset, val);
- rza2_pin_to_gpio(priv->base, offset, 0);
-
- return 0;
-}
-
-static const char * const rza2_gpio_names[] = {
- "P0_0", "P0_1", "P0_2", "P0_3", "P0_4", "P0_5", "P0_6", "P0_7",
- "P1_0", "P1_1", "P1_2", "P1_3", "P1_4", "P1_5", "P1_6", "P1_7",
- "P2_0", "P2_1", "P2_2", "P2_3", "P2_4", "P2_5", "P2_6", "P2_7",
- "P3_0", "P3_1", "P3_2", "P3_3", "P3_4", "P3_5", "P3_6", "P3_7",
- "P4_0", "P4_1", "P4_2", "P4_3", "P4_4", "P4_5", "P4_6", "P4_7",
- "P5_0", "P5_1", "P5_2", "P5_3", "P5_4", "P5_5", "P5_6", "P5_7",
- "P6_0", "P6_1", "P6_2", "P6_3", "P6_4", "P6_5", "P6_6", "P6_7",
- "P7_0", "P7_1", "P7_2", "P7_3", "P7_4", "P7_5", "P7_6", "P7_7",
- "P8_0", "P8_1", "P8_2", "P8_3", "P8_4", "P8_5", "P8_6", "P8_7",
- "P9_0", "P9_1", "P9_2", "P9_3", "P9_4", "P9_5", "P9_6", "P9_7",
- "PA_0", "PA_1", "PA_2", "PA_3", "PA_4", "PA_5", "PA_6", "PA_7",
- "PB_0", "PB_1", "PB_2", "PB_3", "PB_4", "PB_5", "PB_6", "PB_7",
- "PC_0", "PC_1", "PC_2", "PC_3", "PC_4", "PC_5", "PC_6", "PC_7",
- "PD_0", "PD_1", "PD_2", "PD_3", "PD_4", "PD_5", "PD_6", "PD_7",
- "PE_0", "PE_1", "PE_2", "PE_3", "PE_4", "PE_5", "PE_6", "PE_7",
- "PF_0", "PF_1", "PF_2", "PF_3", "PF_4", "PF_5", "PF_6", "PF_7",
- "PG_0", "PG_1", "PG_2", "PG_3", "PG_4", "PG_5", "PG_6", "PG_7",
- "PH_0", "PH_1", "PH_2", "PH_3", "PH_4", "PH_5", "PH_6", "PH_7",
- /* port I does not exist */
- "PJ_0", "PJ_1", "PJ_2", "PJ_3", "PJ_4", "PJ_5", "PJ_6", "PJ_7",
- "PK_0", "PK_1", "PK_2", "PK_3", "PK_4", "PK_5", "PK_6", "PK_7",
- "PL_0", "PL_1", "PL_2", "PL_3", "PL_4", "PL_5", "PL_6", "PL_7",
- "PM_0", "PM_1", "PM_2", "PM_3", "PM_4", "PM_5", "PM_6", "PM_7",
-};
-
-static struct gpio_chip chip = {
- .names = rza2_gpio_names,
- .base = -1,
- .get_direction = rza2_chip_get_direction,
- .direction_input = rza2_chip_direction_input,
- .direction_output = rza2_chip_direction_output,
- .get = rza2_chip_get,
- .set = rza2_chip_set,
-};
-
-static int rza2_gpio_register(struct rza2_pinctrl_priv *priv)
-{
- struct device_node *np = priv->dev->of_node;
- struct of_phandle_args of_args;
- int ret;
-
- chip.label = devm_kasprintf(priv->dev, GFP_KERNEL, "%pOFn", np);
- chip.of_node = np;
- chip.parent = priv->dev;
- chip.ngpio = priv->npins;
-
- ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0,
- &of_args);
- if (ret) {
- dev_err(priv->dev, "Unable to parse gpio-ranges\n");
- return ret;
- }
-
- if ((of_args.args[0] != 0) ||
- (of_args.args[1] != 0) ||
- (of_args.args[2] != priv->npins)) {
- dev_err(priv->dev, "gpio-ranges does not match selected SOC\n");
- return -EINVAL;
- }
- priv->gpio_range.id = 0;
- priv->gpio_range.pin_base = priv->gpio_range.base = 0;
- priv->gpio_range.npins = priv->npins;
- priv->gpio_range.name = chip.label;
- priv->gpio_range.gc = &chip;
-
- /* Register our gpio chip with gpiolib */
- ret = devm_gpiochip_add_data(priv->dev, &chip, priv);
- if (ret)
- return ret;
-
- /* Register pin range with pinctrl core */
- pinctrl_add_gpio_range(priv->pctl, &priv->gpio_range);
-
- dev_dbg(priv->dev, "Registered gpio controller\n");
-
- return 0;
-}
-
-static int rza2_pinctrl_register(struct rza2_pinctrl_priv *priv)
-{
- struct pinctrl_pin_desc *pins;
- unsigned int i;
- int ret;
-
- pins = devm_kcalloc(priv->dev, priv->npins, sizeof(*pins), GFP_KERNEL);
- if (!pins)
- return -ENOMEM;
-
- priv->pins = pins;
- priv->desc.pins = pins;
- priv->desc.npins = priv->npins;
-
- for (i = 0; i < priv->npins; i++) {
- pins[i].number = i;
- pins[i].name = rza2_gpio_names[i];
- }
-
- ret = devm_pinctrl_register_and_init(priv->dev, &priv->desc, priv,
- &priv->pctl);
- if (ret) {
- dev_err(priv->dev, "pinctrl registration failed\n");
- return ret;
- }
-
- ret = pinctrl_enable(priv->pctl);
- if (ret) {
- dev_err(priv->dev, "pinctrl enable failed\n");
- return ret;
- }
-
- ret = rza2_gpio_register(priv);
- if (ret) {
- dev_err(priv->dev, "GPIO registration failed\n");
- return ret;
- }
-
- return 0;
-}
-
-/*
- * For each DT node, create a single pin mapping. That pin mapping will only
- * contain a single group of pins, and that group of pins will only have a
- * single function that can be selected.
- */
-static int rza2_dt_node_to_map(struct pinctrl_dev *pctldev,
- struct device_node *np,
- struct pinctrl_map **map,
- unsigned int *num_maps)
-{
- struct rza2_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
- unsigned int *pins, *psel_val;
- int i, ret, npins, gsel, fsel;
- struct property *of_pins;
- const char **pin_fn;
-
- /* Find out how many pins to map */
- of_pins = of_find_property(np, "pinmux", NULL);
- if (!of_pins) {
- dev_info(priv->dev, "Missing pinmux property\n");
- return -ENOENT;
- }
- npins = of_pins->length / sizeof(u32);
-
- pins = devm_kcalloc(priv->dev, npins, sizeof(*pins), GFP_KERNEL);
- psel_val = devm_kcalloc(priv->dev, npins, sizeof(*psel_val),
- GFP_KERNEL);
- pin_fn = devm_kzalloc(priv->dev, sizeof(*pin_fn), GFP_KERNEL);
- if (!pins || !psel_val || !pin_fn)
- return -ENOMEM;
-
- /* Collect pin locations and mux settings from DT properties */
- for (i = 0; i < npins; ++i) {
- u32 value;
-
- ret = of_property_read_u32_index(np, "pinmux", i, &value);
- if (ret)
- return ret;
- pins[i] = value & MUX_PIN_ID_MASK;
- psel_val[i] = MUX_FUNC(value);
- }
-
- /* Register a single pin group listing all the pins we read from DT */
- gsel = pinctrl_generic_add_group(pctldev, np->name, pins, npins, NULL);
- if (gsel < 0)
- return gsel;
-
- /*
- * Register a single group function where the 'data' is an array PSEL
- * register values read from DT.
- */
- pin_fn[0] = np->name;
- fsel = pinmux_generic_add_function(pctldev, np->name, pin_fn, 1,
- psel_val);
- if (fsel < 0) {
- ret = fsel;
- goto remove_group;
- }
-
- dev_dbg(priv->dev, "Parsed %pOF with %d pins\n", np, npins);
-
- /* Create map where to retrieve function and mux settings from */
- *num_maps = 0;
- *map = kzalloc(sizeof(**map), GFP_KERNEL);
- if (!*map) {
- ret = -ENOMEM;
- goto remove_function;
- }
-
- (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
- (*map)->data.mux.group = np->name;
- (*map)->data.mux.function = np->name;
- *num_maps = 1;
-
- return 0;
-
-remove_function:
- pinmux_generic_remove_function(pctldev, fsel);
-
-remove_group:
- pinctrl_generic_remove_group(pctldev, gsel);
-
- dev_err(priv->dev, "Unable to parse DT node %s\n", np->name);
-
- return ret;
-}
-
-static void rza2_dt_free_map(struct pinctrl_dev *pctldev,
- struct pinctrl_map *map, unsigned int num_maps)
-{
- kfree(map);
-}
-
-static const struct pinctrl_ops rza2_pinctrl_ops = {
- .get_groups_count = pinctrl_generic_get_group_count,
- .get_group_name = pinctrl_generic_get_group_name,
- .get_group_pins = pinctrl_generic_get_group_pins,
- .dt_node_to_map = rza2_dt_node_to_map,
- .dt_free_map = rza2_dt_free_map,
-};
-
-static int rza2_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
- unsigned int group)
-{
- struct rza2_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
- struct function_desc *func;
- unsigned int i, *psel_val;
- struct group_desc *grp;
-
- grp = pinctrl_generic_get_group(pctldev, group);
- if (!grp)
- return -EINVAL;
-
- func = pinmux_generic_get_function(pctldev, selector);
- if (!func)
- return -EINVAL;
-
- psel_val = func->data;
-
- for (i = 0; i < grp->num_pins; ++i) {
- dev_dbg(priv->dev, "Setting P%c_%d to PSEL=%d\n",
- port_names[RZA2_PIN_ID_TO_PORT(grp->pins[i])],
- RZA2_PIN_ID_TO_PIN(grp->pins[i]),
- psel_val[i]);
- rza2_set_pin_function(
- priv->base,
- RZA2_PIN_ID_TO_PORT(grp->pins[i]),
- RZA2_PIN_ID_TO_PIN(grp->pins[i]),
- psel_val[i]);
- }
-
- return 0;
-}
-
-static const struct pinmux_ops rza2_pinmux_ops = {
- .get_functions_count = pinmux_generic_get_function_count,
- .get_function_name = pinmux_generic_get_function_name,
- .get_function_groups = pinmux_generic_get_function_groups,
- .set_mux = rza2_set_mux,
- .strict = true,
-};
-
-static int rza2_pinctrl_probe(struct platform_device *pdev)
-{
- struct rza2_pinctrl_priv *priv;
- int ret;
-
- priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
- if (!priv)
- return -ENOMEM;
-
- priv->dev = &pdev->dev;
-
- priv->base = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(priv->base))
- return PTR_ERR(priv->base);
-
- platform_set_drvdata(pdev, priv);
-
- priv->npins = (int)(uintptr_t)of_device_get_match_data(&pdev->dev) *
- RZA2_PINS_PER_PORT;
-
- priv->desc.name = DRIVER_NAME;
- priv->desc.pctlops = &rza2_pinctrl_ops;
- priv->desc.pmxops = &rza2_pinmux_ops;
- priv->desc.owner = THIS_MODULE;
-
- ret = rza2_pinctrl_register(priv);
- if (ret)
- return ret;
-
- dev_info(&pdev->dev, "Registered ports P0 - P%c\n",
- port_names[priv->desc.npins / RZA2_PINS_PER_PORT - 1]);
-
- return 0;
-}
-
-static const struct of_device_id rza2_pinctrl_of_match[] = {
- { .compatible = "renesas,r7s9210-pinctrl", .data = (void *)22, },
- { /* sentinel */ }
-};
-
-static struct platform_driver rza2_pinctrl_driver = {
- .driver = {
- .name = DRIVER_NAME,
- .of_match_table = rza2_pinctrl_of_match,
- },
- .probe = rza2_pinctrl_probe,
-};
-
-static int __init rza2_pinctrl_init(void)
-{
- return platform_driver_register(&rza2_pinctrl_driver);
-}
-core_initcall(rza2_pinctrl_init);
-
-MODULE_AUTHOR("Chris Brandt <chris.brandt@renesas.com>");
-MODULE_DESCRIPTION("Pin and gpio controller driver for RZ/A2 SoC");
-MODULE_LICENSE("GPL v2");
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2014-2018 Renesas Electronics Europe Limited
- *
- * Phil Edworthy <phil.edworthy@renesas.com>
- * Based on a driver originally written by Michel Pollet at Renesas.
- */
-
-#include <dt-bindings/pinctrl/rzn1-pinctrl.h>
-#include <linux/clk.h>
-#include <linux/device.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/pinctrl/pinconf-generic.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/pinctrl/pinmux.h>
-#include <linux/platform_device.h>
-#include <linux/slab.h>
-#include "core.h"
-#include "pinconf.h"
-#include "pinctrl-utils.h"
-
-/* Field positions and masks in the pinmux registers */
-#define RZN1_L1_PIN_DRIVE_STRENGTH 10
-#define RZN1_L1_PIN_DRIVE_STRENGTH_4MA 0
-#define RZN1_L1_PIN_DRIVE_STRENGTH_6MA 1
-#define RZN1_L1_PIN_DRIVE_STRENGTH_8MA 2
-#define RZN1_L1_PIN_DRIVE_STRENGTH_12MA 3
-#define RZN1_L1_PIN_PULL 8
-#define RZN1_L1_PIN_PULL_NONE 0
-#define RZN1_L1_PIN_PULL_UP 1
-#define RZN1_L1_PIN_PULL_DOWN 3
-#define RZN1_L1_FUNCTION 0
-#define RZN1_L1_FUNC_MASK 0xf
-#define RZN1_L1_FUNCTION_L2 0xf
-
-/*
- * The hardware manual describes two levels of multiplexing, but it's more
- * logical to think of the hardware as three levels, with level 3 consisting of
- * the multiplexing for Ethernet MDIO signals.
- *
- * Level 1 functions go from 0 to 9, with level 1 function '15' (0xf) specifying
- * that level 2 functions are used instead. Level 2 has a lot more options,
- * going from 0 to 61. Level 3 allows selection of MDIO functions which can be
- * floating, or one of seven internal peripherals. Unfortunately, there are two
- * level 2 functions that can select MDIO, and two MDIO channels so we have four
- * sets of level 3 functions.
- *
- * For this driver, we've compounded the numbers together, so:
- * 0 to 9 is level 1
- * 10 to 71 is 10 + level 2 number
- * 72 to 79 is 72 + MDIO0 source for level 2 MDIO function.
- * 80 to 87 is 80 + MDIO0 source for level 2 MDIO_E1 function.
- * 88 to 95 is 88 + MDIO1 source for level 2 MDIO function.
- * 96 to 103 is 96 + MDIO1 source for level 2 MDIO_E1 function.
- * Examples:
- * Function 28 corresponds UART0
- * Function 73 corresponds to MDIO0 to GMAC0
- *
- * There are 170 configurable pins (called PL_GPIO in the datasheet).
- */
-
-/*
- * Structure detailing the HW registers on the RZ/N1 devices.
- * Both the Level 1 mux registers and Level 2 mux registers have the same
- * structure. The only difference is that Level 2 has additional MDIO registers
- * at the end.
- */
-struct rzn1_pinctrl_regs {
- u32 conf[170];
- u32 pad0[86];
- u32 status_protect; /* 0x400 */
- /* MDIO mux registers, level2 only */
- u32 l2_mdio[2];
-};
-
-/**
- * struct rzn1_pmx_func - describes rzn1 pinmux functions
- * @name: the name of this specific function
- * @groups: corresponding pin groups
- * @num_groups: the number of groups
- */
-struct rzn1_pmx_func {
- const char *name;
- const char **groups;
- unsigned int num_groups;
-};
-
-/**
- * struct rzn1_pin_group - describes an rzn1 pin group
- * @name: the name of this specific pin group
- * @func: the name of the function selected by this group
- * @npins: the number of pins in this group array, i.e. the number of
- * elements in .pins so we can iterate over that array
- * @pins: array of pins. Needed due to pinctrl_ops.get_group_pins()
- * @pin_ids: array of pin_ids, i.e. the value used to select the mux
- */
-struct rzn1_pin_group {
- const char *name;
- const char *func;
- unsigned int npins;
- unsigned int *pins;
- u8 *pin_ids;
-};
-
-struct rzn1_pinctrl {
- struct device *dev;
- struct clk *clk;
- struct pinctrl_dev *pctl;
- struct rzn1_pinctrl_regs __iomem *lev1;
- struct rzn1_pinctrl_regs __iomem *lev2;
- u32 lev1_protect_phys;
- u32 lev2_protect_phys;
- int mdio_func[2];
-
- struct rzn1_pin_group *groups;
- unsigned int ngroups;
-
- struct rzn1_pmx_func *functions;
- unsigned int nfunctions;
-};
-
-#define RZN1_PINS_PROP "pinmux"
-
-#define RZN1_PIN(pin) PINCTRL_PIN(pin, "pl_gpio"#pin)
-
-static const struct pinctrl_pin_desc rzn1_pins[] = {
- RZN1_PIN(0), RZN1_PIN(1), RZN1_PIN(2), RZN1_PIN(3), RZN1_PIN(4),
- RZN1_PIN(5), RZN1_PIN(6), RZN1_PIN(7), RZN1_PIN(8), RZN1_PIN(9),
- RZN1_PIN(10), RZN1_PIN(11), RZN1_PIN(12), RZN1_PIN(13), RZN1_PIN(14),
- RZN1_PIN(15), RZN1_PIN(16), RZN1_PIN(17), RZN1_PIN(18), RZN1_PIN(19),
- RZN1_PIN(20), RZN1_PIN(21), RZN1_PIN(22), RZN1_PIN(23), RZN1_PIN(24),
- RZN1_PIN(25), RZN1_PIN(26), RZN1_PIN(27), RZN1_PIN(28), RZN1_PIN(29),
- RZN1_PIN(30), RZN1_PIN(31), RZN1_PIN(32), RZN1_PIN(33), RZN1_PIN(34),
- RZN1_PIN(35), RZN1_PIN(36), RZN1_PIN(37), RZN1_PIN(38), RZN1_PIN(39),
- RZN1_PIN(40), RZN1_PIN(41), RZN1_PIN(42), RZN1_PIN(43), RZN1_PIN(44),
- RZN1_PIN(45), RZN1_PIN(46), RZN1_PIN(47), RZN1_PIN(48), RZN1_PIN(49),
- RZN1_PIN(50), RZN1_PIN(51), RZN1_PIN(52), RZN1_PIN(53), RZN1_PIN(54),
- RZN1_PIN(55), RZN1_PIN(56), RZN1_PIN(57), RZN1_PIN(58), RZN1_PIN(59),
- RZN1_PIN(60), RZN1_PIN(61), RZN1_PIN(62), RZN1_PIN(63), RZN1_PIN(64),
- RZN1_PIN(65), RZN1_PIN(66), RZN1_PIN(67), RZN1_PIN(68), RZN1_PIN(69),
- RZN1_PIN(70), RZN1_PIN(71), RZN1_PIN(72), RZN1_PIN(73), RZN1_PIN(74),
- RZN1_PIN(75), RZN1_PIN(76), RZN1_PIN(77), RZN1_PIN(78), RZN1_PIN(79),
- RZN1_PIN(80), RZN1_PIN(81), RZN1_PIN(82), RZN1_PIN(83), RZN1_PIN(84),
- RZN1_PIN(85), RZN1_PIN(86), RZN1_PIN(87), RZN1_PIN(88), RZN1_PIN(89),
- RZN1_PIN(90), RZN1_PIN(91), RZN1_PIN(92), RZN1_PIN(93), RZN1_PIN(94),
- RZN1_PIN(95), RZN1_PIN(96), RZN1_PIN(97), RZN1_PIN(98), RZN1_PIN(99),
- RZN1_PIN(100), RZN1_PIN(101), RZN1_PIN(102), RZN1_PIN(103),
- RZN1_PIN(104), RZN1_PIN(105), RZN1_PIN(106), RZN1_PIN(107),
- RZN1_PIN(108), RZN1_PIN(109), RZN1_PIN(110), RZN1_PIN(111),
- RZN1_PIN(112), RZN1_PIN(113), RZN1_PIN(114), RZN1_PIN(115),
- RZN1_PIN(116), RZN1_PIN(117), RZN1_PIN(118), RZN1_PIN(119),
- RZN1_PIN(120), RZN1_PIN(121), RZN1_PIN(122), RZN1_PIN(123),
- RZN1_PIN(124), RZN1_PIN(125), RZN1_PIN(126), RZN1_PIN(127),
- RZN1_PIN(128), RZN1_PIN(129), RZN1_PIN(130), RZN1_PIN(131),
- RZN1_PIN(132), RZN1_PIN(133), RZN1_PIN(134), RZN1_PIN(135),
- RZN1_PIN(136), RZN1_PIN(137), RZN1_PIN(138), RZN1_PIN(139),
- RZN1_PIN(140), RZN1_PIN(141), RZN1_PIN(142), RZN1_PIN(143),
- RZN1_PIN(144), RZN1_PIN(145), RZN1_PIN(146), RZN1_PIN(147),
- RZN1_PIN(148), RZN1_PIN(149), RZN1_PIN(150), RZN1_PIN(151),
- RZN1_PIN(152), RZN1_PIN(153), RZN1_PIN(154), RZN1_PIN(155),
- RZN1_PIN(156), RZN1_PIN(157), RZN1_PIN(158), RZN1_PIN(159),
- RZN1_PIN(160), RZN1_PIN(161), RZN1_PIN(162), RZN1_PIN(163),
- RZN1_PIN(164), RZN1_PIN(165), RZN1_PIN(166), RZN1_PIN(167),
- RZN1_PIN(168), RZN1_PIN(169),
-};
-
-enum {
- LOCK_LEVEL1 = 0x1,
- LOCK_LEVEL2 = 0x2,
- LOCK_ALL = LOCK_LEVEL1 | LOCK_LEVEL2,
-};
-
-static void rzn1_hw_set_lock(struct rzn1_pinctrl *ipctl, u8 lock, u8 value)
-{
- /*
- * The pinmux configuration is locked by writing the physical address of
- * the status_protect register to itself. It is unlocked by writing the
- * address | 1.
- */
- if (lock & LOCK_LEVEL1) {
- u32 val = ipctl->lev1_protect_phys | !(value & LOCK_LEVEL1);
-
- writel(val, &ipctl->lev1->status_protect);
- }
-
- if (lock & LOCK_LEVEL2) {
- u32 val = ipctl->lev2_protect_phys | !(value & LOCK_LEVEL2);
-
- writel(val, &ipctl->lev2->status_protect);
- }
-}
-
-static void rzn1_pinctrl_mdio_select(struct rzn1_pinctrl *ipctl, int mdio,
- u32 func)
-{
- if (ipctl->mdio_func[mdio] >= 0 && ipctl->mdio_func[mdio] != func)
- dev_warn(ipctl->dev, "conflicting setting for mdio%d!\n", mdio);
- ipctl->mdio_func[mdio] = func;
-
- dev_dbg(ipctl->dev, "setting mdio%d to %u\n", mdio, func);
-
- writel(func, &ipctl->lev2->l2_mdio[mdio]);
-}
-
-/*
- * Using a composite pin description, set the hardware pinmux registers
- * with the corresponding values.
- * Make sure to unlock write protection and reset it afterward.
- *
- * NOTE: There is no protection for potential concurrency, it is assumed these
- * calls are serialized already.
- */
-static int rzn1_set_hw_pin_func(struct rzn1_pinctrl *ipctl, unsigned int pin,
- u32 pin_config, u8 use_locks)
-{
- u32 l1_cache;
- u32 l2_cache;
- u32 l1;
- u32 l2;
-
- /* Level 3 MDIO multiplexing */
- if (pin_config >= RZN1_FUNC_MDIO0_HIGHZ &&
- pin_config <= RZN1_FUNC_MDIO1_E1_SWITCH) {
- int mdio_channel;
- u32 mdio_func;
-
- if (pin_config <= RZN1_FUNC_MDIO1_HIGHZ)
- mdio_channel = 0;
- else
- mdio_channel = 1;
-
- /* Get MDIO func, and convert the func to the level 2 number */
- if (pin_config <= RZN1_FUNC_MDIO0_SWITCH) {
- mdio_func = pin_config - RZN1_FUNC_MDIO0_HIGHZ;
- pin_config = RZN1_FUNC_ETH_MDIO;
- } else if (pin_config <= RZN1_FUNC_MDIO0_E1_SWITCH) {
- mdio_func = pin_config - RZN1_FUNC_MDIO0_E1_HIGHZ;
- pin_config = RZN1_FUNC_ETH_MDIO_E1;
- } else if (pin_config <= RZN1_FUNC_MDIO1_SWITCH) {
- mdio_func = pin_config - RZN1_FUNC_MDIO1_HIGHZ;
- pin_config = RZN1_FUNC_ETH_MDIO;
- } else {
- mdio_func = pin_config - RZN1_FUNC_MDIO1_E1_HIGHZ;
- pin_config = RZN1_FUNC_ETH_MDIO_E1;
- }
- rzn1_pinctrl_mdio_select(ipctl, mdio_channel, mdio_func);
- }
-
- /* Note here, we do not allow anything past the MDIO Mux values */
- if (pin >= ARRAY_SIZE(ipctl->lev1->conf) ||
- pin_config >= RZN1_FUNC_MDIO0_HIGHZ)
- return -EINVAL;
-
- l1 = readl(&ipctl->lev1->conf[pin]);
- l1_cache = l1;
- l2 = readl(&ipctl->lev2->conf[pin]);
- l2_cache = l2;
-
- dev_dbg(ipctl->dev, "setting func for pin %u to %u\n", pin, pin_config);
-
- l1 &= ~(RZN1_L1_FUNC_MASK << RZN1_L1_FUNCTION);
-
- if (pin_config < RZN1_FUNC_L2_OFFSET) {
- l1 |= (pin_config << RZN1_L1_FUNCTION);
- } else {
- l1 |= (RZN1_L1_FUNCTION_L2 << RZN1_L1_FUNCTION);
-
- l2 = pin_config - RZN1_FUNC_L2_OFFSET;
- }
-
- /* If either configuration changes, we update both anyway */
- if (l1 != l1_cache || l2 != l2_cache) {
- writel(l1, &ipctl->lev1->conf[pin]);
- writel(l2, &ipctl->lev2->conf[pin]);
- }
-
- return 0;
-}
-
-static const struct rzn1_pin_group *rzn1_pinctrl_find_group_by_name(
- const struct rzn1_pinctrl *ipctl, const char *name)
-{
- unsigned int i;
-
- for (i = 0; i < ipctl->ngroups; i++) {
- if (!strcmp(ipctl->groups[i].name, name))
- return &ipctl->groups[i];
- }
-
- return NULL;
-}
-
-static int rzn1_get_groups_count(struct pinctrl_dev *pctldev)
-{
- struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
-
- return ipctl->ngroups;
-}
-
-static const char *rzn1_get_group_name(struct pinctrl_dev *pctldev,
- unsigned int selector)
-{
- struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
-
- return ipctl->groups[selector].name;
-}
-
-static int rzn1_get_group_pins(struct pinctrl_dev *pctldev,
- unsigned int selector, const unsigned int **pins,
- unsigned int *npins)
-{
- struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
-
- if (selector >= ipctl->ngroups)
- return -EINVAL;
-
- *pins = ipctl->groups[selector].pins;
- *npins = ipctl->groups[selector].npins;
-
- return 0;
-}
-
-/*
- * This function is called for each pinctl 'Function' node.
- * Sub-nodes can be used to describe multiple 'Groups' for the 'Function'
- * If there aren't any sub-nodes, the 'Group' is essentially the 'Function'.
- * Each 'Group' uses pinmux = <...> to detail the pins and data used to select
- * the functionality. Each 'Group' has optional pin configurations that apply
- * to all pins in the 'Group'.
- */
-static int rzn1_dt_node_to_map_one(struct pinctrl_dev *pctldev,
- struct device_node *np,
- struct pinctrl_map **map,
- unsigned int *num_maps)
-{
- struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
- const struct rzn1_pin_group *grp;
- unsigned long *configs = NULL;
- unsigned int reserved_maps = *num_maps;
- unsigned int num_configs = 0;
- unsigned int reserve = 1;
- int ret;
-
- dev_dbg(ipctl->dev, "processing node %pOF\n", np);
-
- grp = rzn1_pinctrl_find_group_by_name(ipctl, np->name);
- if (!grp) {
- dev_err(ipctl->dev, "unable to find group for node %pOF\n", np);
-
- return -EINVAL;
- }
-
- /* Get the group's pin configuration */
- ret = pinconf_generic_parse_dt_config(np, pctldev, &configs,
- &num_configs);
- if (ret < 0) {
- dev_err(ipctl->dev, "%pOF: could not parse property\n", np);
-
- return ret;
- }
-
- if (num_configs)
- reserve++;
-
- /* Increase the number of maps to cover this group */
- ret = pinctrl_utils_reserve_map(pctldev, map, &reserved_maps, num_maps,
- reserve);
- if (ret < 0)
- goto out;
-
- /* Associate the group with the function */
- ret = pinctrl_utils_add_map_mux(pctldev, map, &reserved_maps, num_maps,
- grp->name, grp->func);
- if (ret < 0)
- goto out;
-
- if (num_configs) {
- /* Associate the group's pin configuration with the group */
- ret = pinctrl_utils_add_map_configs(pctldev, map,
- &reserved_maps, num_maps, grp->name,
- configs, num_configs,
- PIN_MAP_TYPE_CONFIGS_GROUP);
- if (ret < 0)
- goto out;
- }
-
- dev_dbg(pctldev->dev, "maps: function %s group %s (%d pins)\n",
- grp->func, grp->name, grp->npins);
-
-out:
- kfree(configs);
-
- return ret;
-}
-
-static int rzn1_dt_node_to_map(struct pinctrl_dev *pctldev,
- struct device_node *np,
- struct pinctrl_map **map,
- unsigned int *num_maps)
-{
- struct device_node *child;
- int ret;
-
- *map = NULL;
- *num_maps = 0;
-
- ret = rzn1_dt_node_to_map_one(pctldev, np, map, num_maps);
- if (ret < 0)
- return ret;
-
- for_each_child_of_node(np, child) {
- ret = rzn1_dt_node_to_map_one(pctldev, child, map, num_maps);
- if (ret < 0) {
- of_node_put(child);
- return ret;
- }
- }
-
- return 0;
-}
-
-static const struct pinctrl_ops rzn1_pctrl_ops = {
- .get_groups_count = rzn1_get_groups_count,
- .get_group_name = rzn1_get_group_name,
- .get_group_pins = rzn1_get_group_pins,
- .dt_node_to_map = rzn1_dt_node_to_map,
- .dt_free_map = pinctrl_utils_free_map,
-};
-
-static int rzn1_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
-{
- struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
-
- return ipctl->nfunctions;
-}
-
-static const char *rzn1_pmx_get_func_name(struct pinctrl_dev *pctldev,
- unsigned int selector)
-{
- struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
-
- return ipctl->functions[selector].name;
-}
-
-static int rzn1_pmx_get_groups(struct pinctrl_dev *pctldev,
- unsigned int selector,
- const char * const **groups,
- unsigned int * const num_groups)
-{
- struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
-
- *groups = ipctl->functions[selector].groups;
- *num_groups = ipctl->functions[selector].num_groups;
-
- return 0;
-}
-
-static int rzn1_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
- unsigned int group)
-{
- struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
- struct rzn1_pin_group *grp = &ipctl->groups[group];
- unsigned int i, grp_pins = grp->npins;
-
- dev_dbg(ipctl->dev, "set mux %s(%d) group %s(%d)\n",
- ipctl->functions[selector].name, selector, grp->name, group);
-
- rzn1_hw_set_lock(ipctl, LOCK_ALL, LOCK_ALL);
- for (i = 0; i < grp_pins; i++)
- rzn1_set_hw_pin_func(ipctl, grp->pins[i], grp->pin_ids[i], 0);
- rzn1_hw_set_lock(ipctl, LOCK_ALL, 0);
-
- return 0;
-}
-
-static const struct pinmux_ops rzn1_pmx_ops = {
- .get_functions_count = rzn1_pmx_get_funcs_count,
- .get_function_name = rzn1_pmx_get_func_name,
- .get_function_groups = rzn1_pmx_get_groups,
- .set_mux = rzn1_set_mux,
-};
-
-static int rzn1_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
- unsigned long *config)
-{
- struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
- enum pin_config_param param = pinconf_to_config_param(*config);
- static const u32 reg_drive[4] = { 4, 6, 8, 12 };
- u32 pull, drive, l1mux;
- u32 l1, l2, arg = 0;
-
- if (pin >= ARRAY_SIZE(ipctl->lev1->conf))
- return -EINVAL;
-
- l1 = readl(&ipctl->lev1->conf[pin]);
-
- l1mux = l1 & RZN1_L1_FUNC_MASK;
- pull = (l1 >> RZN1_L1_PIN_PULL) & 0x3;
- drive = (l1 >> RZN1_L1_PIN_DRIVE_STRENGTH) & 0x3;
-
- switch (param) {
- case PIN_CONFIG_BIAS_PULL_UP:
- if (pull != RZN1_L1_PIN_PULL_UP)
- return -EINVAL;
- break;
- case PIN_CONFIG_BIAS_PULL_DOWN:
- if (pull != RZN1_L1_PIN_PULL_DOWN)
- return -EINVAL;
- break;
- case PIN_CONFIG_BIAS_DISABLE:
- if (pull != RZN1_L1_PIN_PULL_NONE)
- return -EINVAL;
- break;
- case PIN_CONFIG_DRIVE_STRENGTH:
- arg = reg_drive[drive];
- break;
- case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
- l2 = readl(&ipctl->lev2->conf[pin]);
- if (l1mux == RZN1_L1_FUNCTION_L2) {
- if (l2 != 0)
- return -EINVAL;
- } else if (l1mux != RZN1_FUNC_HIGHZ) {
- return -EINVAL;
- }
- break;
- default:
- return -ENOTSUPP;
- }
-
- *config = pinconf_to_config_packed(param, arg);
-
- return 0;
-}
-
-static int rzn1_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
- unsigned long *configs, unsigned int num_configs)
-{
- struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
- enum pin_config_param param;
- unsigned int i;
- u32 l1, l1_cache;
- u32 drv;
- u32 arg;
-
- if (pin >= ARRAY_SIZE(ipctl->lev1->conf))
- return -EINVAL;
-
- l1 = readl(&ipctl->lev1->conf[pin]);
- l1_cache = l1;
-
- for (i = 0; i < num_configs; i++) {
- param = pinconf_to_config_param(configs[i]);
- arg = pinconf_to_config_argument(configs[i]);
-
- switch (param) {
- case PIN_CONFIG_BIAS_PULL_UP:
- dev_dbg(ipctl->dev, "set pin %d pull up\n", pin);
- l1 &= ~(0x3 << RZN1_L1_PIN_PULL);
- l1 |= (RZN1_L1_PIN_PULL_UP << RZN1_L1_PIN_PULL);
- break;
- case PIN_CONFIG_BIAS_PULL_DOWN:
- dev_dbg(ipctl->dev, "set pin %d pull down\n", pin);
- l1 &= ~(0x3 << RZN1_L1_PIN_PULL);
- l1 |= (RZN1_L1_PIN_PULL_DOWN << RZN1_L1_PIN_PULL);
- break;
- case PIN_CONFIG_BIAS_DISABLE:
- dev_dbg(ipctl->dev, "set pin %d bias off\n", pin);
- l1 &= ~(0x3 << RZN1_L1_PIN_PULL);
- l1 |= (RZN1_L1_PIN_PULL_NONE << RZN1_L1_PIN_PULL);
- break;
- case PIN_CONFIG_DRIVE_STRENGTH:
- dev_dbg(ipctl->dev, "set pin %d drv %umA\n", pin, arg);
- switch (arg) {
- case 4:
- drv = RZN1_L1_PIN_DRIVE_STRENGTH_4MA;
- break;
- case 6:
- drv = RZN1_L1_PIN_DRIVE_STRENGTH_6MA;
- break;
- case 8:
- drv = RZN1_L1_PIN_DRIVE_STRENGTH_8MA;
- break;
- case 12:
- drv = RZN1_L1_PIN_DRIVE_STRENGTH_12MA;
- break;
- default:
- dev_err(ipctl->dev,
- "Drive strength %umA not supported\n",
- arg);
-
- return -EINVAL;
- }
-
- l1 &= ~(0x3 << RZN1_L1_PIN_DRIVE_STRENGTH);
- l1 |= (drv << RZN1_L1_PIN_DRIVE_STRENGTH);
- break;
-
- case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
- dev_dbg(ipctl->dev, "set pin %d High-Z\n", pin);
- l1 &= ~RZN1_L1_FUNC_MASK;
- l1 |= RZN1_FUNC_HIGHZ;
- break;
- default:
- return -ENOTSUPP;
- }
- }
-
- if (l1 != l1_cache) {
- rzn1_hw_set_lock(ipctl, LOCK_LEVEL1, LOCK_LEVEL1);
- writel(l1, &ipctl->lev1->conf[pin]);
- rzn1_hw_set_lock(ipctl, LOCK_LEVEL1, 0);
- }
-
- return 0;
-}
-
-static int rzn1_pinconf_group_get(struct pinctrl_dev *pctldev,
- unsigned int selector,
- unsigned long *config)
-{
- struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
- struct rzn1_pin_group *grp = &ipctl->groups[selector];
- unsigned long old = 0;
- unsigned int i;
-
- dev_dbg(ipctl->dev, "group get %s selector:%u\n", grp->name, selector);
-
- for (i = 0; i < grp->npins; i++) {
- if (rzn1_pinconf_get(pctldev, grp->pins[i], config))
- return -ENOTSUPP;
-
- /* configs do not match between two pins */
- if (i && (old != *config))
- return -ENOTSUPP;
-
- old = *config;
- }
-
- return 0;
-}
-
-static int rzn1_pinconf_group_set(struct pinctrl_dev *pctldev,
- unsigned int selector,
- unsigned long *configs,
- unsigned int num_configs)
-{
- struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
- struct rzn1_pin_group *grp = &ipctl->groups[selector];
- unsigned int i;
- int ret;
-
- dev_dbg(ipctl->dev, "group set %s selector:%u configs:%p/%d\n",
- grp->name, selector, configs, num_configs);
-
- for (i = 0; i < grp->npins; i++) {
- unsigned int pin = grp->pins[i];
-
- ret = rzn1_pinconf_set(pctldev, pin, configs, num_configs);
- if (ret)
- return ret;
- }
-
- return 0;
-}
-
-static const struct pinconf_ops rzn1_pinconf_ops = {
- .is_generic = true,
- .pin_config_get = rzn1_pinconf_get,
- .pin_config_set = rzn1_pinconf_set,
- .pin_config_group_get = rzn1_pinconf_group_get,
- .pin_config_group_set = rzn1_pinconf_group_set,
- .pin_config_config_dbg_show = pinconf_generic_dump_config,
-};
-
-static struct pinctrl_desc rzn1_pinctrl_desc = {
- .pctlops = &rzn1_pctrl_ops,
- .pmxops = &rzn1_pmx_ops,
- .confops = &rzn1_pinconf_ops,
- .owner = THIS_MODULE,
-};
-
-static int rzn1_pinctrl_parse_groups(struct device_node *np,
- struct rzn1_pin_group *grp,
- struct rzn1_pinctrl *ipctl)
-{
- const __be32 *list;
- unsigned int i;
- int size;
-
- dev_dbg(ipctl->dev, "%s: %s\n", __func__, np->name);
-
- /* Initialise group */
- grp->name = np->name;
-
- /*
- * The binding format is
- * pinmux = <PIN_FUNC_ID CONFIG ...>,
- * do sanity check and calculate pins number
- */
- list = of_get_property(np, RZN1_PINS_PROP, &size);
- if (!list) {
- dev_err(ipctl->dev,
- "no " RZN1_PINS_PROP " property in node %pOF\n", np);
-
- return -EINVAL;
- }
-
- if (!size) {
- dev_err(ipctl->dev, "Invalid " RZN1_PINS_PROP " in node %pOF\n",
- np);
-
- return -EINVAL;
- }
-
- grp->npins = size / sizeof(list[0]);
- grp->pin_ids = devm_kmalloc_array(ipctl->dev,
- grp->npins, sizeof(grp->pin_ids[0]),
- GFP_KERNEL);
- grp->pins = devm_kmalloc_array(ipctl->dev,
- grp->npins, sizeof(grp->pins[0]),
- GFP_KERNEL);
- if (!grp->pin_ids || !grp->pins)
- return -ENOMEM;
-
- for (i = 0; i < grp->npins; i++) {
- u32 pin_id = be32_to_cpu(*list++);
-
- grp->pins[i] = pin_id & 0xff;
- grp->pin_ids[i] = (pin_id >> 8) & 0x7f;
- }
-
- return grp->npins;
-}
-
-static int rzn1_pinctrl_count_function_groups(struct device_node *np)
-{
- struct device_node *child;
- int count = 0;
-
- if (of_property_count_u32_elems(np, RZN1_PINS_PROP) > 0)
- count++;
-
- for_each_child_of_node(np, child) {
- if (of_property_count_u32_elems(child, RZN1_PINS_PROP) > 0)
- count++;
- }
-
- return count;
-}
-
-static int rzn1_pinctrl_parse_functions(struct device_node *np,
- struct rzn1_pinctrl *ipctl,
- unsigned int index)
-{
- struct rzn1_pmx_func *func;
- struct rzn1_pin_group *grp;
- struct device_node *child;
- unsigned int i = 0;
- int ret;
-
- func = &ipctl->functions[index];
-
- /* Initialise function */
- func->name = np->name;
- func->num_groups = rzn1_pinctrl_count_function_groups(np);
- if (func->num_groups == 0) {
- dev_err(ipctl->dev, "no groups defined in %pOF\n", np);
- return -EINVAL;
- }
- dev_dbg(ipctl->dev, "function %s has %d groups\n",
- np->name, func->num_groups);
-
- func->groups = devm_kmalloc_array(ipctl->dev,
- func->num_groups, sizeof(char *),
- GFP_KERNEL);
- if (!func->groups)
- return -ENOMEM;
-
- if (of_property_count_u32_elems(np, RZN1_PINS_PROP) > 0) {
- func->groups[i] = np->name;
- grp = &ipctl->groups[ipctl->ngroups];
- grp->func = func->name;
- ret = rzn1_pinctrl_parse_groups(np, grp, ipctl);
- if (ret < 0)
- return ret;
- i++;
- ipctl->ngroups++;
- }
-
- for_each_child_of_node(np, child) {
- func->groups[i] = child->name;
- grp = &ipctl->groups[ipctl->ngroups];
- grp->func = func->name;
- ret = rzn1_pinctrl_parse_groups(child, grp, ipctl);
- if (ret < 0) {
- of_node_put(child);
- return ret;
- }
- i++;
- ipctl->ngroups++;
- }
-
- dev_dbg(ipctl->dev, "function %s parsed %u/%u groups\n",
- np->name, i, func->num_groups);
-
- return 0;
-}
-
-static int rzn1_pinctrl_probe_dt(struct platform_device *pdev,
- struct rzn1_pinctrl *ipctl)
-{
- struct device_node *np = pdev->dev.of_node;
- struct device_node *child;
- unsigned int maxgroups = 0;
- unsigned int i = 0;
- int nfuncs = 0;
- int ret;
-
- nfuncs = of_get_child_count(np);
- if (nfuncs <= 0)
- return 0;
-
- ipctl->nfunctions = nfuncs;
- ipctl->functions = devm_kmalloc_array(&pdev->dev, nfuncs,
- sizeof(*ipctl->functions),
- GFP_KERNEL);
- if (!ipctl->functions)
- return -ENOMEM;
-
- ipctl->ngroups = 0;
- for_each_child_of_node(np, child)
- maxgroups += rzn1_pinctrl_count_function_groups(child);
-
- ipctl->groups = devm_kmalloc_array(&pdev->dev,
- maxgroups,
- sizeof(*ipctl->groups),
- GFP_KERNEL);
- if (!ipctl->groups)
- return -ENOMEM;
-
- for_each_child_of_node(np, child) {
- ret = rzn1_pinctrl_parse_functions(child, ipctl, i++);
- if (ret < 0) {
- of_node_put(child);
- return ret;
- }
- }
-
- return 0;
-}
-
-static int rzn1_pinctrl_probe(struct platform_device *pdev)
-{
- struct rzn1_pinctrl *ipctl;
- struct resource *res;
- int ret;
-
- /* Create state holders etc for this driver */
- ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
- if (!ipctl)
- return -ENOMEM;
-
- ipctl->mdio_func[0] = -1;
- ipctl->mdio_func[1] = -1;
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- ipctl->lev1_protect_phys = (u32)res->start + 0x400;
- ipctl->lev1 = devm_ioremap_resource(&pdev->dev, res);
- if (IS_ERR(ipctl->lev1))
- return PTR_ERR(ipctl->lev1);
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
- ipctl->lev2_protect_phys = (u32)res->start + 0x400;
- ipctl->lev2 = devm_ioremap_resource(&pdev->dev, res);
- if (IS_ERR(ipctl->lev2))
- return PTR_ERR(ipctl->lev2);
-
- ipctl->clk = devm_clk_get(&pdev->dev, NULL);
- if (IS_ERR(ipctl->clk))
- return PTR_ERR(ipctl->clk);
- ret = clk_prepare_enable(ipctl->clk);
- if (ret)
- return ret;
-
- ipctl->dev = &pdev->dev;
- rzn1_pinctrl_desc.name = dev_name(&pdev->dev);
- rzn1_pinctrl_desc.pins = rzn1_pins;
- rzn1_pinctrl_desc.npins = ARRAY_SIZE(rzn1_pins);
-
- ret = rzn1_pinctrl_probe_dt(pdev, ipctl);
- if (ret) {
- dev_err(&pdev->dev, "fail to probe dt properties\n");
- goto err_clk;
- }
-
- platform_set_drvdata(pdev, ipctl);
-
- ret = devm_pinctrl_register_and_init(&pdev->dev, &rzn1_pinctrl_desc,
- ipctl, &ipctl->pctl);
- if (ret) {
- dev_err(&pdev->dev, "could not register rzn1 pinctrl driver\n");
- goto err_clk;
- }
-
- ret = pinctrl_enable(ipctl->pctl);
- if (ret)
- goto err_clk;
-
- dev_info(&pdev->dev, "probed\n");
-
- return 0;
-
-err_clk:
- clk_disable_unprepare(ipctl->clk);
-
- return ret;
-}
-
-static int rzn1_pinctrl_remove(struct platform_device *pdev)
-{
- struct rzn1_pinctrl *ipctl = platform_get_drvdata(pdev);
-
- clk_disable_unprepare(ipctl->clk);
-
- return 0;
-}
-
-static const struct of_device_id rzn1_pinctrl_match[] = {
- { .compatible = "renesas,rzn1-pinctrl", },
- {}
-};
-MODULE_DEVICE_TABLE(of, rzn1_pinctrl_match);
-
-static struct platform_driver rzn1_pinctrl_driver = {
- .probe = rzn1_pinctrl_probe,
- .remove = rzn1_pinctrl_remove,
- .driver = {
- .name = "rzn1-pinctrl",
- .of_match_table = rzn1_pinctrl_match,
- },
-};
-
-static int __init _pinctrl_drv_register(void)
-{
- return platform_driver_register(&rzn1_pinctrl_driver);
-}
-subsys_initcall(_pinctrl_drv_register);
-
-MODULE_AUTHOR("Phil Edworthy <phil.edworthy@renesas.com>");
-MODULE_DESCRIPTION("Renesas RZ/N1 pinctrl driver");
-MODULE_LICENSE("GPL v2");
# Renesas SH and SH Mobile PINCTRL drivers
#
+menu "Renesas pinctrl drivers"
+
config PINCTRL_SH_PFC
bool "Renesas SoC pin control support" if COMPILE_TEST && !(ARCH_RENESAS || SUPERH)
default y if ARCH_RENESAS || SUPERH
help
This enables pin control drivers for Renesas SuperH and ARM platforms
+config PINCTRL_RZA1
+ bool "RZ/A1 gpio and pinctrl driver"
+ depends on OF
+ depends on ARCH_R7S72100 || COMPILE_TEST
+ select GPIOLIB
+ select GENERIC_PINCTRL_GROUPS
+ select GENERIC_PINMUX_FUNCTIONS
+ select GENERIC_PINCONF
+ help
+ This selects pinctrl driver for Renesas RZ/A1 platforms.
+
+config PINCTRL_RZA2
+ bool "RZ/A2 gpio and pinctrl driver"
+ depends on OF
+ depends on ARCH_R7S9210 || COMPILE_TEST
+ select GPIOLIB
+ select GENERIC_PINCTRL_GROUPS
+ select GENERIC_PINMUX_FUNCTIONS
+ select GENERIC_PINCONF
+ help
+ This selects GPIO and pinctrl driver for Renesas RZ/A2 platforms.
+
+config PINCTRL_RZN1
+ bool "RZ/N1 pinctrl driver"
+ depends on OF
+ depends on ARCH_RZN1 || COMPILE_TEST
+ select GENERIC_PINCTRL_GROUPS
+ select GENERIC_PINMUX_FUNCTIONS
+ select GENERIC_PINCONF
+ help
+ This selects pinctrl driver for Renesas RZ/N1 devices.
+
config PINCTRL_SH_PFC_GPIO
select GPIOLIB
bool
config PINCTRL_PFC_SHX3
bool "SH-X3 pin control support" if COMPILE_TEST
select PINCTRL_SH_FUNC_GPIO
+
+endmenu
obj-$(CONFIG_PINCTRL_PFC_SH7786) += pfc-sh7786.o
obj-$(CONFIG_PINCTRL_PFC_SHX3) += pfc-shx3.o
+obj-$(CONFIG_PINCTRL_RZA1) += pinctrl-rza1.o
+obj-$(CONFIG_PINCTRL_RZA2) += pinctrl-rza2.o
+obj-$(CONFIG_PINCTRL_RZN1) += pinctrl-rzn1.o
+
ifeq ($(CONFIG_COMPILE_TEST),y)
CFLAGS_pfc-sh7203.o += -I$(srctree)/arch/sh/include/cpu-sh2a
CFLAGS_pfc-sh7264.o += -I$(srctree)/arch/sh/include/cpu-sh2a
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Combined GPIO and pin controller support for Renesas RZ/A1 (r7s72100) SoC
+ *
+ * Copyright (C) 2017 Jacopo Mondi
+ */
+
+/*
+ * This pin controller/gpio combined driver supports Renesas devices of RZ/A1
+ * family.
+ * This includes SoCs which are sub- or super- sets of this particular line,
+ * as RZ/A1H (r7s721000), RZ/A1M (r7s721010) and RZ/A1L (r7s721020).
+ */
+
+#include <linux/bitops.h>
+#include <linux/err.h>
+#include <linux/gpio/driver.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/slab.h>
+
+#include "../core.h"
+#include "../devicetree.h"
+#include "../pinconf.h"
+#include "../pinmux.h"
+
+#define DRIVER_NAME "pinctrl-rza1"
+
+#define RZA1_P_REG 0x0000
+#define RZA1_PPR_REG 0x0200
+#define RZA1_PM_REG 0x0300
+#define RZA1_PMC_REG 0x0400
+#define RZA1_PFC_REG 0x0500
+#define RZA1_PFCE_REG 0x0600
+#define RZA1_PFCEA_REG 0x0a00
+#define RZA1_PIBC_REG 0x4000
+#define RZA1_PBDC_REG 0x4100
+#define RZA1_PIPC_REG 0x4200
+
+#define RZA1_ADDR(mem, reg, port) ((mem) + (reg) + ((port) * 4))
+
+#define RZA1_NPORTS 12
+#define RZA1_PINS_PER_PORT 16
+#define RZA1_NPINS (RZA1_PINS_PER_PORT * RZA1_NPORTS)
+#define RZA1_PIN_ID_TO_PORT(id) ((id) / RZA1_PINS_PER_PORT)
+#define RZA1_PIN_ID_TO_PIN(id) ((id) % RZA1_PINS_PER_PORT)
+
+/*
+ * Use 16 lower bits [15:0] for pin identifier
+ * Use 16 higher bits [31:16] for pin mux function
+ */
+#define MUX_PIN_ID_MASK GENMASK(15, 0)
+#define MUX_FUNC_MASK GENMASK(31, 16)
+
+#define MUX_FUNC_OFFS 16
+#define MUX_FUNC(pinconf) \
+ ((pinconf & MUX_FUNC_MASK) >> MUX_FUNC_OFFS)
+#define MUX_FUNC_PFC_MASK BIT(0)
+#define MUX_FUNC_PFCE_MASK BIT(1)
+#define MUX_FUNC_PFCEA_MASK BIT(2)
+
+/* Pin mux flags */
+#define MUX_FLAGS_BIDIR BIT(0)
+#define MUX_FLAGS_SWIO_INPUT BIT(1)
+#define MUX_FLAGS_SWIO_OUTPUT BIT(2)
+
+/* ----------------------------------------------------------------------------
+ * RZ/A1 pinmux flags
+ */
+
+/*
+ * rza1_bidir_pin - describe a single pin that needs bidir flag applied.
+ */
+struct rza1_bidir_pin {
+ u8 pin: 4;
+ u8 func: 4;
+};
+
+/*
+ * rza1_bidir_entry - describe a list of pins that needs bidir flag applied.
+ * Each struct rza1_bidir_entry describes a port.
+ */
+struct rza1_bidir_entry {
+ const unsigned int npins;
+ const struct rza1_bidir_pin *pins;
+};
+
+/*
+ * rza1_swio_pin - describe a single pin that needs swio flag applied.
+ */
+struct rza1_swio_pin {
+ u16 pin: 4;
+ u16 port: 4;
+ u16 func: 4;
+ u16 input: 1;
+};
+
+/*
+ * rza1_swio_entry - describe a list of pins that needs swio flag applied
+ */
+struct rza1_swio_entry {
+ const unsigned int npins;
+ const struct rza1_swio_pin *pins;
+};
+
+/*
+ * rza1_pinmux_conf - group together bidir and swio pinmux flag tables
+ */
+struct rza1_pinmux_conf {
+ const struct rza1_bidir_entry *bidir_entries;
+ const struct rza1_swio_entry *swio_entries;
+};
+
+/* ----------------------------------------------------------------------------
+ * RZ/A1H (r7s72100) pinmux flags
+ */
+
+static const struct rza1_bidir_pin rza1h_bidir_pins_p1[] = {
+ { .pin = 0, .func = 1 },
+ { .pin = 1, .func = 1 },
+ { .pin = 2, .func = 1 },
+ { .pin = 3, .func = 1 },
+ { .pin = 4, .func = 1 },
+ { .pin = 5, .func = 1 },
+ { .pin = 6, .func = 1 },
+ { .pin = 7, .func = 1 },
+};
+
+static const struct rza1_bidir_pin rza1h_bidir_pins_p2[] = {
+ { .pin = 0, .func = 1 },
+ { .pin = 1, .func = 1 },
+ { .pin = 2, .func = 1 },
+ { .pin = 3, .func = 1 },
+ { .pin = 4, .func = 1 },
+ { .pin = 0, .func = 4 },
+ { .pin = 1, .func = 4 },
+ { .pin = 2, .func = 4 },
+ { .pin = 3, .func = 4 },
+ { .pin = 5, .func = 1 },
+ { .pin = 6, .func = 1 },
+ { .pin = 7, .func = 1 },
+ { .pin = 8, .func = 1 },
+ { .pin = 9, .func = 1 },
+ { .pin = 10, .func = 1 },
+ { .pin = 11, .func = 1 },
+ { .pin = 12, .func = 1 },
+ { .pin = 13, .func = 1 },
+ { .pin = 14, .func = 1 },
+ { .pin = 15, .func = 1 },
+ { .pin = 12, .func = 4 },
+ { .pin = 13, .func = 4 },
+ { .pin = 14, .func = 4 },
+ { .pin = 15, .func = 4 },
+};
+
+static const struct rza1_bidir_pin rza1h_bidir_pins_p3[] = {
+ { .pin = 3, .func = 2 },
+ { .pin = 10, .func = 7 },
+ { .pin = 11, .func = 7 },
+ { .pin = 13, .func = 7 },
+ { .pin = 14, .func = 7 },
+ { .pin = 15, .func = 7 },
+ { .pin = 10, .func = 8 },
+ { .pin = 11, .func = 8 },
+ { .pin = 13, .func = 8 },
+ { .pin = 14, .func = 8 },
+ { .pin = 15, .func = 8 },
+};
+
+static const struct rza1_bidir_pin rza1h_bidir_pins_p4[] = {
+ { .pin = 0, .func = 8 },
+ { .pin = 1, .func = 8 },
+ { .pin = 2, .func = 8 },
+ { .pin = 3, .func = 8 },
+ { .pin = 10, .func = 3 },
+ { .pin = 11, .func = 3 },
+ { .pin = 13, .func = 3 },
+ { .pin = 14, .func = 3 },
+ { .pin = 15, .func = 3 },
+ { .pin = 10, .func = 4 },
+ { .pin = 11, .func = 4 },
+ { .pin = 13, .func = 4 },
+ { .pin = 14, .func = 4 },
+ { .pin = 15, .func = 4 },
+ { .pin = 12, .func = 5 },
+ { .pin = 13, .func = 5 },
+ { .pin = 14, .func = 5 },
+ { .pin = 15, .func = 5 },
+};
+
+static const struct rza1_bidir_pin rza1h_bidir_pins_p6[] = {
+ { .pin = 0, .func = 1 },
+ { .pin = 1, .func = 1 },
+ { .pin = 2, .func = 1 },
+ { .pin = 3, .func = 1 },
+ { .pin = 4, .func = 1 },
+ { .pin = 5, .func = 1 },
+ { .pin = 6, .func = 1 },
+ { .pin = 7, .func = 1 },
+ { .pin = 8, .func = 1 },
+ { .pin = 9, .func = 1 },
+ { .pin = 10, .func = 1 },
+ { .pin = 11, .func = 1 },
+ { .pin = 12, .func = 1 },
+ { .pin = 13, .func = 1 },
+ { .pin = 14, .func = 1 },
+ { .pin = 15, .func = 1 },
+};
+
+static const struct rza1_bidir_pin rza1h_bidir_pins_p7[] = {
+ { .pin = 13, .func = 3 },
+};
+
+static const struct rza1_bidir_pin rza1h_bidir_pins_p8[] = {
+ { .pin = 8, .func = 3 },
+ { .pin = 9, .func = 3 },
+ { .pin = 10, .func = 3 },
+ { .pin = 11, .func = 3 },
+ { .pin = 14, .func = 2 },
+ { .pin = 15, .func = 2 },
+ { .pin = 14, .func = 3 },
+ { .pin = 15, .func = 3 },
+};
+
+static const struct rza1_bidir_pin rza1h_bidir_pins_p9[] = {
+ { .pin = 0, .func = 2 },
+ { .pin = 1, .func = 2 },
+ { .pin = 4, .func = 2 },
+ { .pin = 5, .func = 2 },
+ { .pin = 6, .func = 2 },
+ { .pin = 7, .func = 2 },
+};
+
+static const struct rza1_bidir_pin rza1h_bidir_pins_p11[] = {
+ { .pin = 6, .func = 2 },
+ { .pin = 7, .func = 2 },
+ { .pin = 9, .func = 2 },
+ { .pin = 6, .func = 4 },
+ { .pin = 7, .func = 4 },
+ { .pin = 9, .func = 4 },
+ { .pin = 10, .func = 2 },
+ { .pin = 11, .func = 2 },
+ { .pin = 10, .func = 4 },
+ { .pin = 11, .func = 4 },
+ { .pin = 12, .func = 4 },
+ { .pin = 13, .func = 4 },
+ { .pin = 14, .func = 4 },
+ { .pin = 15, .func = 4 },
+};
+
+static const struct rza1_swio_pin rza1h_swio_pins[] = {
+ { .port = 2, .pin = 7, .func = 4, .input = 0 },
+ { .port = 2, .pin = 11, .func = 4, .input = 0 },
+ { .port = 3, .pin = 7, .func = 3, .input = 0 },
+ { .port = 3, .pin = 7, .func = 8, .input = 0 },
+ { .port = 4, .pin = 7, .func = 5, .input = 0 },
+ { .port = 4, .pin = 7, .func = 11, .input = 0 },
+ { .port = 4, .pin = 15, .func = 6, .input = 0 },
+ { .port = 5, .pin = 0, .func = 1, .input = 1 },
+ { .port = 5, .pin = 1, .func = 1, .input = 1 },
+ { .port = 5, .pin = 2, .func = 1, .input = 1 },
+ { .port = 5, .pin = 3, .func = 1, .input = 1 },
+ { .port = 5, .pin = 4, .func = 1, .input = 1 },
+ { .port = 5, .pin = 5, .func = 1, .input = 1 },
+ { .port = 5, .pin = 6, .func = 1, .input = 1 },
+ { .port = 5, .pin = 7, .func = 1, .input = 1 },
+ { .port = 7, .pin = 4, .func = 6, .input = 0 },
+ { .port = 7, .pin = 11, .func = 2, .input = 0 },
+ { .port = 8, .pin = 10, .func = 8, .input = 0 },
+ { .port = 10, .pin = 15, .func = 2, .input = 0 },
+};
+
+static const struct rza1_bidir_entry rza1h_bidir_entries[RZA1_NPORTS] = {
+ [1] = { ARRAY_SIZE(rza1h_bidir_pins_p1), rza1h_bidir_pins_p1 },
+ [2] = { ARRAY_SIZE(rza1h_bidir_pins_p2), rza1h_bidir_pins_p2 },
+ [3] = { ARRAY_SIZE(rza1h_bidir_pins_p3), rza1h_bidir_pins_p3 },
+ [4] = { ARRAY_SIZE(rza1h_bidir_pins_p4), rza1h_bidir_pins_p4 },
+ [6] = { ARRAY_SIZE(rza1h_bidir_pins_p6), rza1h_bidir_pins_p6 },
+ [7] = { ARRAY_SIZE(rza1h_bidir_pins_p7), rza1h_bidir_pins_p7 },
+ [8] = { ARRAY_SIZE(rza1h_bidir_pins_p8), rza1h_bidir_pins_p8 },
+ [9] = { ARRAY_SIZE(rza1h_bidir_pins_p9), rza1h_bidir_pins_p9 },
+ [11] = { ARRAY_SIZE(rza1h_bidir_pins_p11), rza1h_bidir_pins_p11 },
+};
+
+static const struct rza1_swio_entry rza1h_swio_entries[] = {
+ [0] = { ARRAY_SIZE(rza1h_swio_pins), rza1h_swio_pins },
+};
+
+/* RZ/A1H (r7s72100x) pinmux flags table */
+static const struct rza1_pinmux_conf rza1h_pmx_conf = {
+ .bidir_entries = rza1h_bidir_entries,
+ .swio_entries = rza1h_swio_entries,
+};
+
+/* ----------------------------------------------------------------------------
+ * RZ/A1L (r7s72102) pinmux flags
+ */
+
+static const struct rza1_bidir_pin rza1l_bidir_pins_p1[] = {
+ { .pin = 0, .func = 1 },
+ { .pin = 1, .func = 1 },
+ { .pin = 2, .func = 1 },
+ { .pin = 3, .func = 1 },
+ { .pin = 4, .func = 1 },
+ { .pin = 5, .func = 1 },
+ { .pin = 6, .func = 1 },
+ { .pin = 7, .func = 1 },
+};
+
+static const struct rza1_bidir_pin rza1l_bidir_pins_p3[] = {
+ { .pin = 0, .func = 2 },
+ { .pin = 1, .func = 2 },
+ { .pin = 2, .func = 2 },
+ { .pin = 4, .func = 2 },
+ { .pin = 5, .func = 2 },
+ { .pin = 10, .func = 2 },
+ { .pin = 11, .func = 2 },
+ { .pin = 12, .func = 2 },
+ { .pin = 13, .func = 2 },
+};
+
+static const struct rza1_bidir_pin rza1l_bidir_pins_p4[] = {
+ { .pin = 1, .func = 4 },
+ { .pin = 2, .func = 2 },
+ { .pin = 3, .func = 2 },
+ { .pin = 6, .func = 2 },
+ { .pin = 7, .func = 2 },
+};
+
+static const struct rza1_bidir_pin rza1l_bidir_pins_p5[] = {
+ { .pin = 0, .func = 1 },
+ { .pin = 1, .func = 1 },
+ { .pin = 2, .func = 1 },
+ { .pin = 3, .func = 1 },
+ { .pin = 4, .func = 1 },
+ { .pin = 5, .func = 1 },
+ { .pin = 6, .func = 1 },
+ { .pin = 7, .func = 1 },
+ { .pin = 8, .func = 1 },
+ { .pin = 9, .func = 1 },
+ { .pin = 10, .func = 1 },
+ { .pin = 11, .func = 1 },
+ { .pin = 12, .func = 1 },
+ { .pin = 13, .func = 1 },
+ { .pin = 14, .func = 1 },
+ { .pin = 15, .func = 1 },
+ { .pin = 0, .func = 2 },
+ { .pin = 1, .func = 2 },
+ { .pin = 2, .func = 2 },
+ { .pin = 3, .func = 2 },
+};
+
+static const struct rza1_bidir_pin rza1l_bidir_pins_p6[] = {
+ { .pin = 0, .func = 1 },
+ { .pin = 1, .func = 1 },
+ { .pin = 2, .func = 1 },
+ { .pin = 3, .func = 1 },
+ { .pin = 4, .func = 1 },
+ { .pin = 5, .func = 1 },
+ { .pin = 6, .func = 1 },
+ { .pin = 7, .func = 1 },
+ { .pin = 8, .func = 1 },
+ { .pin = 9, .func = 1 },
+ { .pin = 10, .func = 1 },
+ { .pin = 11, .func = 1 },
+ { .pin = 12, .func = 1 },
+ { .pin = 13, .func = 1 },
+ { .pin = 14, .func = 1 },
+ { .pin = 15, .func = 1 },
+};
+
+static const struct rza1_bidir_pin rza1l_bidir_pins_p7[] = {
+ { .pin = 2, .func = 2 },
+ { .pin = 3, .func = 2 },
+ { .pin = 5, .func = 2 },
+ { .pin = 6, .func = 2 },
+ { .pin = 7, .func = 2 },
+ { .pin = 2, .func = 3 },
+ { .pin = 3, .func = 3 },
+ { .pin = 5, .func = 3 },
+ { .pin = 6, .func = 3 },
+ { .pin = 7, .func = 3 },
+};
+
+static const struct rza1_bidir_pin rza1l_bidir_pins_p9[] = {
+ { .pin = 1, .func = 2 },
+ { .pin = 0, .func = 3 },
+ { .pin = 1, .func = 3 },
+ { .pin = 3, .func = 3 },
+ { .pin = 4, .func = 3 },
+ { .pin = 5, .func = 3 },
+};
+
+static const struct rza1_swio_pin rza1l_swio_pins[] = {
+ { .port = 2, .pin = 8, .func = 2, .input = 0 },
+ { .port = 5, .pin = 6, .func = 3, .input = 0 },
+ { .port = 6, .pin = 6, .func = 3, .input = 0 },
+ { .port = 6, .pin = 10, .func = 3, .input = 0 },
+ { .port = 7, .pin = 10, .func = 2, .input = 0 },
+ { .port = 8, .pin = 2, .func = 3, .input = 0 },
+};
+
+static const struct rza1_bidir_entry rza1l_bidir_entries[RZA1_NPORTS] = {
+ [1] = { ARRAY_SIZE(rza1l_bidir_pins_p1), rza1l_bidir_pins_p1 },
+ [3] = { ARRAY_SIZE(rza1l_bidir_pins_p3), rza1l_bidir_pins_p3 },
+ [4] = { ARRAY_SIZE(rza1l_bidir_pins_p4), rza1l_bidir_pins_p4 },
+ [5] = { ARRAY_SIZE(rza1l_bidir_pins_p4), rza1l_bidir_pins_p5 },
+ [6] = { ARRAY_SIZE(rza1l_bidir_pins_p6), rza1l_bidir_pins_p6 },
+ [7] = { ARRAY_SIZE(rza1l_bidir_pins_p7), rza1l_bidir_pins_p7 },
+ [9] = { ARRAY_SIZE(rza1l_bidir_pins_p9), rza1l_bidir_pins_p9 },
+};
+
+static const struct rza1_swio_entry rza1l_swio_entries[] = {
+ [0] = { ARRAY_SIZE(rza1l_swio_pins), rza1l_swio_pins },
+};
+
+/* RZ/A1L (r7s72102x) pinmux flags table */
+static const struct rza1_pinmux_conf rza1l_pmx_conf = {
+ .bidir_entries = rza1l_bidir_entries,
+ .swio_entries = rza1l_swio_entries,
+};
+
+/* ----------------------------------------------------------------------------
+ * RZ/A1 types
+ */
+/**
+ * struct rza1_mux_conf - describes a pin multiplexing operation
+ *
+ * @id: the pin identifier from 0 to RZA1_NPINS
+ * @port: the port where pin sits on
+ * @pin: pin id
+ * @mux_func: alternate function id number
+ * @mux_flags: alternate function flags
+ * @value: output value to set the pin to
+ */
+struct rza1_mux_conf {
+ u16 id;
+ u8 port;
+ u8 pin;
+ u8 mux_func;
+ u8 mux_flags;
+ u8 value;
+};
+
+/**
+ * struct rza1_port - describes a pin port
+ *
+ * This is mostly useful to lock register writes per-bank and not globally.
+ *
+ * @lock: protect access to HW registers
+ * @id: port number
+ * @base: logical address base
+ * @pins: pins sitting on this port
+ */
+struct rza1_port {
+ spinlock_t lock;
+ unsigned int id;
+ void __iomem *base;
+ struct pinctrl_pin_desc *pins;
+};
+
+/**
+ * struct rza1_pinctrl - RZ pincontroller device
+ *
+ * @dev: parent device structure
+ * @mutex: protect [pinctrl|pinmux]_generic functions
+ * @base: logical address base
+ * @nport: number of pin controller ports
+ * @ports: pin controller banks
+ * @pins: pin array for pinctrl core
+ * @desc: pincontroller desc for pinctrl core
+ * @pctl: pinctrl device
+ * @data: device specific data
+ */
+struct rza1_pinctrl {
+ struct device *dev;
+
+ struct mutex mutex;
+
+ void __iomem *base;
+
+ unsigned int nport;
+ struct rza1_port *ports;
+
+ struct pinctrl_pin_desc *pins;
+ struct pinctrl_desc desc;
+ struct pinctrl_dev *pctl;
+
+ const void *data;
+};
+
+/* ----------------------------------------------------------------------------
+ * RZ/A1 pinmux flags
+ */
+static inline bool rza1_pinmux_get_bidir(unsigned int port,
+ unsigned int pin,
+ unsigned int func,
+ const struct rza1_bidir_entry *table)
+{
+ const struct rza1_bidir_entry *entry = &table[port];
+ const struct rza1_bidir_pin *bidir_pin;
+ unsigned int i;
+
+ for (i = 0; i < entry->npins; ++i) {
+ bidir_pin = &entry->pins[i];
+ if (bidir_pin->pin == pin && bidir_pin->func == func)
+ return true;
+ }
+
+ return false;
+}
+
+static inline int rza1_pinmux_get_swio(unsigned int port,
+ unsigned int pin,
+ unsigned int func,
+ const struct rza1_swio_entry *table)
+{
+ const struct rza1_swio_pin *swio_pin;
+ unsigned int i;
+
+
+ for (i = 0; i < table->npins; ++i) {
+ swio_pin = &table->pins[i];
+ if (swio_pin->port == port && swio_pin->pin == pin &&
+ swio_pin->func == func)
+ return swio_pin->input;
+ }
+
+ return -ENOENT;
+}
+
+/*
+ * rza1_pinmux_get_flags() - return pinmux flags associated to a pin
+ */
+static unsigned int rza1_pinmux_get_flags(unsigned int port, unsigned int pin,
+ unsigned int func,
+ struct rza1_pinctrl *rza1_pctl)
+
+{
+ const struct rza1_pinmux_conf *pmx_conf = rza1_pctl->data;
+ const struct rza1_bidir_entry *bidir_entries = pmx_conf->bidir_entries;
+ const struct rza1_swio_entry *swio_entries = pmx_conf->swio_entries;
+ unsigned int pmx_flags = 0;
+ int ret;
+
+ if (rza1_pinmux_get_bidir(port, pin, func, bidir_entries))
+ pmx_flags |= MUX_FLAGS_BIDIR;
+
+ ret = rza1_pinmux_get_swio(port, pin, func, swio_entries);
+ if (ret == 0)
+ pmx_flags |= MUX_FLAGS_SWIO_OUTPUT;
+ else if (ret > 0)
+ pmx_flags |= MUX_FLAGS_SWIO_INPUT;
+
+ return pmx_flags;
+}
+
+/* ----------------------------------------------------------------------------
+ * RZ/A1 SoC operations
+ */
+
+/*
+ * rza1_set_bit() - un-locked set/clear a single bit in pin configuration
+ * registers
+ */
+static inline void rza1_set_bit(struct rza1_port *port, unsigned int reg,
+ unsigned int bit, bool set)
+{
+ void __iomem *mem = RZA1_ADDR(port->base, reg, port->id);
+ u16 val = ioread16(mem);
+
+ if (set)
+ val |= BIT(bit);
+ else
+ val &= ~BIT(bit);
+
+ iowrite16(val, mem);
+}
+
+static inline unsigned int rza1_get_bit(struct rza1_port *port,
+ unsigned int reg, unsigned int bit)
+{
+ void __iomem *mem = RZA1_ADDR(port->base, reg, port->id);
+
+ return ioread16(mem) & BIT(bit);
+}
+
+/**
+ * rza1_pin_reset() - reset a pin to default initial state
+ *
+ * Reset pin state disabling input buffer and bi-directional control,
+ * and configure it as input port.
+ * Note that pin is now configured with direction as input but with input
+ * buffer disabled. This implies the pin value cannot be read in this state.
+ *
+ * @port: port where pin sits on
+ * @pin: pin offset
+ */
+static void rza1_pin_reset(struct rza1_port *port, unsigned int pin)
+{
+ unsigned long irqflags;
+
+ spin_lock_irqsave(&port->lock, irqflags);
+ rza1_set_bit(port, RZA1_PIBC_REG, pin, 0);
+ rza1_set_bit(port, RZA1_PBDC_REG, pin, 0);
+
+ rza1_set_bit(port, RZA1_PM_REG, pin, 1);
+ rza1_set_bit(port, RZA1_PMC_REG, pin, 0);
+ rza1_set_bit(port, RZA1_PIPC_REG, pin, 0);
+ spin_unlock_irqrestore(&port->lock, irqflags);
+}
+
+/**
+ * rza1_pin_set_direction() - set I/O direction on a pin in port mode
+ *
+ * When running in output port mode keep PBDC enabled to allow reading the
+ * pin value from PPR.
+ *
+ * @port: port where pin sits on
+ * @pin: pin offset
+ * @input: input enable/disable flag
+ */
+static inline void rza1_pin_set_direction(struct rza1_port *port,
+ unsigned int pin, bool input)
+{
+ unsigned long irqflags;
+
+ spin_lock_irqsave(&port->lock, irqflags);
+
+ rza1_set_bit(port, RZA1_PIBC_REG, pin, 1);
+ if (input) {
+ rza1_set_bit(port, RZA1_PM_REG, pin, 1);
+ rza1_set_bit(port, RZA1_PBDC_REG, pin, 0);
+ } else {
+ rza1_set_bit(port, RZA1_PM_REG, pin, 0);
+ rza1_set_bit(port, RZA1_PBDC_REG, pin, 1);
+ }
+
+ spin_unlock_irqrestore(&port->lock, irqflags);
+}
+
+static inline void rza1_pin_set(struct rza1_port *port, unsigned int pin,
+ unsigned int value)
+{
+ unsigned long irqflags;
+
+ spin_lock_irqsave(&port->lock, irqflags);
+ rza1_set_bit(port, RZA1_P_REG, pin, !!value);
+ spin_unlock_irqrestore(&port->lock, irqflags);
+}
+
+static inline int rza1_pin_get(struct rza1_port *port, unsigned int pin)
+{
+ return rza1_get_bit(port, RZA1_PPR_REG, pin);
+}
+
+/**
+ * rza1_pin_mux_single() - configure pin multiplexing on a single pin
+ *
+ * @rza1_pctl: RZ/A1 pin controller device
+ * @mux_conf: pin multiplexing descriptor
+ */
+static int rza1_pin_mux_single(struct rza1_pinctrl *rza1_pctl,
+ struct rza1_mux_conf *mux_conf)
+{
+ struct rza1_port *port = &rza1_pctl->ports[mux_conf->port];
+ unsigned int pin = mux_conf->pin;
+ u8 mux_func = mux_conf->mux_func;
+ u8 mux_flags = mux_conf->mux_flags;
+ u8 mux_flags_from_table;
+
+ rza1_pin_reset(port, pin);
+
+ /* SWIO pinmux flags coming from DT are high precedence */
+ mux_flags_from_table = rza1_pinmux_get_flags(port->id, pin, mux_func,
+ rza1_pctl);
+ if (mux_flags)
+ mux_flags |= (mux_flags_from_table & MUX_FLAGS_BIDIR);
+ else
+ mux_flags = mux_flags_from_table;
+
+ if (mux_flags & MUX_FLAGS_BIDIR)
+ rza1_set_bit(port, RZA1_PBDC_REG, pin, 1);
+
+ /*
+ * Enable alternate function mode and select it.
+ *
+ * Be careful here: the pin mux sub-nodes in device tree
+ * enumerate alternate functions from 1 to 8;
+ * subtract 1 before using macros to match registers configuration
+ * which expects numbers from 0 to 7 instead.
+ *
+ * ----------------------------------------------------
+ * Alternate mode selection table:
+ *
+ * PMC PFC PFCE PFCAE (mux_func - 1)
+ * 1 0 0 0 0
+ * 1 1 0 0 1
+ * 1 0 1 0 2
+ * 1 1 1 0 3
+ * 1 0 0 1 4
+ * 1 1 0 1 5
+ * 1 0 1 1 6
+ * 1 1 1 1 7
+ * ----------------------------------------------------
+ */
+ mux_func -= 1;
+ rza1_set_bit(port, RZA1_PFC_REG, pin, mux_func & MUX_FUNC_PFC_MASK);
+ rza1_set_bit(port, RZA1_PFCE_REG, pin, mux_func & MUX_FUNC_PFCE_MASK);
+ rza1_set_bit(port, RZA1_PFCEA_REG, pin, mux_func & MUX_FUNC_PFCEA_MASK);
+
+ /*
+ * All alternate functions except a few need PIPCn = 1.
+ * If PIPCn has to stay disabled (SW IO mode), configure PMn according
+ * to I/O direction specified by pin configuration -after- PMC has been
+ * set to one.
+ */
+ if (mux_flags & (MUX_FLAGS_SWIO_INPUT | MUX_FLAGS_SWIO_OUTPUT))
+ rza1_set_bit(port, RZA1_PM_REG, pin,
+ mux_flags & MUX_FLAGS_SWIO_INPUT);
+ else
+ rza1_set_bit(port, RZA1_PIPC_REG, pin, 1);
+
+ rza1_set_bit(port, RZA1_PMC_REG, pin, 1);
+
+ return 0;
+}
+
+/* ----------------------------------------------------------------------------
+ * gpio operations
+ */
+
+/**
+ * rza1_gpio_request() - configure pin in port mode
+ *
+ * Configure a pin as gpio (port mode).
+ * After reset, the pin is in input mode with input buffer disabled.
+ * To use the pin as input or output, set_direction shall be called first
+ *
+ * @chip: gpio chip where the gpio sits on
+ * @gpio: gpio offset
+ */
+static int rza1_gpio_request(struct gpio_chip *chip, unsigned int gpio)
+{
+ struct rza1_port *port = gpiochip_get_data(chip);
+
+ rza1_pin_reset(port, gpio);
+
+ return 0;
+}
+
+/**
+ * rza1_gpio_disable_free() - reset a pin
+ *
+ * Surprisingly, disable_free a gpio, is equivalent to request it.
+ * Reset pin to port mode, with input buffer disabled. This overwrites all
+ * port direction settings applied with set_direction
+ *
+ * @chip: gpio chip where the gpio sits on
+ * @gpio: gpio offset
+ */
+static void rza1_gpio_free(struct gpio_chip *chip, unsigned int gpio)
+{
+ struct rza1_port *port = gpiochip_get_data(chip);
+
+ rza1_pin_reset(port, gpio);
+}
+
+static int rza1_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
+{
+ struct rza1_port *port = gpiochip_get_data(chip);
+
+ if (rza1_get_bit(port, RZA1_PM_REG, gpio))
+ return GPIO_LINE_DIRECTION_IN;
+
+ return GPIO_LINE_DIRECTION_OUT;
+}
+
+static int rza1_gpio_direction_input(struct gpio_chip *chip,
+ unsigned int gpio)
+{
+ struct rza1_port *port = gpiochip_get_data(chip);
+
+ rza1_pin_set_direction(port, gpio, true);
+
+ return 0;
+}
+
+static int rza1_gpio_direction_output(struct gpio_chip *chip,
+ unsigned int gpio,
+ int value)
+{
+ struct rza1_port *port = gpiochip_get_data(chip);
+
+ /* Set value before driving pin direction */
+ rza1_pin_set(port, gpio, value);
+ rza1_pin_set_direction(port, gpio, false);
+
+ return 0;
+}
+
+/**
+ * rza1_gpio_get() - read a gpio pin value
+ *
+ * Read gpio pin value through PPR register.
+ * Requires bi-directional mode to work when reading the value of a pin
+ * in output mode
+ *
+ * @chip: gpio chip where the gpio sits on
+ * @gpio: gpio offset
+ */
+static int rza1_gpio_get(struct gpio_chip *chip, unsigned int gpio)
+{
+ struct rza1_port *port = gpiochip_get_data(chip);
+
+ return rza1_pin_get(port, gpio);
+}
+
+static void rza1_gpio_set(struct gpio_chip *chip, unsigned int gpio,
+ int value)
+{
+ struct rza1_port *port = gpiochip_get_data(chip);
+
+ rza1_pin_set(port, gpio, value);
+}
+
+static const struct gpio_chip rza1_gpiochip_template = {
+ .request = rza1_gpio_request,
+ .free = rza1_gpio_free,
+ .get_direction = rza1_gpio_get_direction,
+ .direction_input = rza1_gpio_direction_input,
+ .direction_output = rza1_gpio_direction_output,
+ .get = rza1_gpio_get,
+ .set = rza1_gpio_set,
+};
+/* ----------------------------------------------------------------------------
+ * pinctrl operations
+ */
+
+/**
+ * rza1_dt_node_pin_count() - Count number of pins in a dt node or in all its
+ * children sub-nodes
+ *
+ * @np: device tree node to parse
+ */
+static int rza1_dt_node_pin_count(struct device_node *np)
+{
+ struct device_node *child;
+ struct property *of_pins;
+ unsigned int npins;
+
+ of_pins = of_find_property(np, "pinmux", NULL);
+ if (of_pins)
+ return of_pins->length / sizeof(u32);
+
+ npins = 0;
+ for_each_child_of_node(np, child) {
+ of_pins = of_find_property(child, "pinmux", NULL);
+ if (!of_pins) {
+ of_node_put(child);
+ return -EINVAL;
+ }
+
+ npins += of_pins->length / sizeof(u32);
+ }
+
+ return npins;
+}
+
+/**
+ * rza1_parse_pmx_function() - parse a pin mux sub-node
+ *
+ * @rza1_pctl: RZ/A1 pin controller device
+ * @np: of pmx sub-node
+ * @mux_confs: array of pin mux configurations to fill with parsed info
+ * @grpins: array of pin ids to mux
+ */
+static int rza1_parse_pinmux_node(struct rza1_pinctrl *rza1_pctl,
+ struct device_node *np,
+ struct rza1_mux_conf *mux_confs,
+ unsigned int *grpins)
+{
+ struct pinctrl_dev *pctldev = rza1_pctl->pctl;
+ char const *prop_name = "pinmux";
+ unsigned long *pin_configs;
+ unsigned int npin_configs;
+ struct property *of_pins;
+ unsigned int npins;
+ u8 pinmux_flags;
+ unsigned int i;
+ int ret;
+
+ of_pins = of_find_property(np, prop_name, NULL);
+ if (!of_pins) {
+ dev_dbg(rza1_pctl->dev, "Missing %s property\n", prop_name);
+ return -ENOENT;
+ }
+ npins = of_pins->length / sizeof(u32);
+
+ /*
+ * Collect pin configuration properties: they apply to all pins in
+ * this sub-node
+ */
+ ret = pinconf_generic_parse_dt_config(np, pctldev, &pin_configs,
+ &npin_configs);
+ if (ret) {
+ dev_err(rza1_pctl->dev,
+ "Unable to parse pin configuration options for %pOFn\n",
+ np);
+ return ret;
+ }
+
+ /*
+ * Create a mask with pinmux flags from pin configuration;
+ * very few pins (TIOC[0-4][A|B|C|D] require SWIO direction
+ * specified in device tree.
+ */
+ pinmux_flags = 0;
+ for (i = 0; i < npin_configs && pinmux_flags == 0; i++)
+ switch (pinconf_to_config_param(pin_configs[i])) {
+ case PIN_CONFIG_INPUT_ENABLE:
+ pinmux_flags |= MUX_FLAGS_SWIO_INPUT;
+ break;
+ case PIN_CONFIG_OUTPUT:
+ pinmux_flags |= MUX_FLAGS_SWIO_OUTPUT;
+ default:
+ break;
+
+ }
+
+ kfree(pin_configs);
+
+ /* Collect pin positions and their mux settings. */
+ for (i = 0; i < npins; ++i) {
+ u32 of_pinconf;
+ struct rza1_mux_conf *mux_conf = &mux_confs[i];
+
+ ret = of_property_read_u32_index(np, prop_name, i, &of_pinconf);
+ if (ret)
+ return ret;
+
+ mux_conf->id = of_pinconf & MUX_PIN_ID_MASK;
+ mux_conf->port = RZA1_PIN_ID_TO_PORT(mux_conf->id);
+ mux_conf->pin = RZA1_PIN_ID_TO_PIN(mux_conf->id);
+ mux_conf->mux_func = MUX_FUNC(of_pinconf);
+ mux_conf->mux_flags = pinmux_flags;
+
+ if (mux_conf->port >= RZA1_NPORTS ||
+ mux_conf->pin >= RZA1_PINS_PER_PORT) {
+ dev_err(rza1_pctl->dev,
+ "Wrong port %u pin %u for %s property\n",
+ mux_conf->port, mux_conf->pin, prop_name);
+ return -EINVAL;
+ }
+
+ grpins[i] = mux_conf->id;
+ }
+
+ return npins;
+}
+
+/**
+ * rza1_dt_node_to_map() - map a pin mux node to a function/group
+ *
+ * Parse and register a pin mux function.
+ *
+ * @pctldev: pin controller device
+ * @np: device tree node to parse
+ * @map: pointer to pin map (output)
+ * @num_maps: number of collected maps (output)
+ */
+static int rza1_dt_node_to_map(struct pinctrl_dev *pctldev,
+ struct device_node *np,
+ struct pinctrl_map **map,
+ unsigned int *num_maps)
+{
+ struct rza1_pinctrl *rza1_pctl = pinctrl_dev_get_drvdata(pctldev);
+ struct rza1_mux_conf *mux_confs, *mux_conf;
+ unsigned int *grpins, *grpin;
+ struct device_node *child;
+ const char *grpname;
+ const char **fngrps;
+ int ret, npins;
+ int gsel, fsel;
+
+ npins = rza1_dt_node_pin_count(np);
+ if (npins < 0) {
+ dev_err(rza1_pctl->dev, "invalid pinmux node structure\n");
+ return -EINVAL;
+ }
+
+ /*
+ * Functions are made of 1 group only;
+ * in fact, functions and groups are identical for this pin controller
+ * except that functions carry an array of per-pin mux configuration
+ * settings.
+ */
+ mux_confs = devm_kcalloc(rza1_pctl->dev, npins, sizeof(*mux_confs),
+ GFP_KERNEL);
+ grpins = devm_kcalloc(rza1_pctl->dev, npins, sizeof(*grpins),
+ GFP_KERNEL);
+ fngrps = devm_kzalloc(rza1_pctl->dev, sizeof(*fngrps), GFP_KERNEL);
+
+ if (!mux_confs || !grpins || !fngrps)
+ return -ENOMEM;
+
+ /*
+ * Parse the pinmux node.
+ * If the node does not contain "pinmux" property (-ENOENT)
+ * that property shall be specified in all its children sub-nodes.
+ */
+ mux_conf = &mux_confs[0];
+ grpin = &grpins[0];
+
+ ret = rza1_parse_pinmux_node(rza1_pctl, np, mux_conf, grpin);
+ if (ret == -ENOENT)
+ for_each_child_of_node(np, child) {
+ ret = rza1_parse_pinmux_node(rza1_pctl, child, mux_conf,
+ grpin);
+ if (ret < 0) {
+ of_node_put(child);
+ return ret;
+ }
+
+ grpin += ret;
+ mux_conf += ret;
+ }
+ else if (ret < 0)
+ return ret;
+
+ /* Register pin group and function name to pinctrl_generic */
+ grpname = np->name;
+ fngrps[0] = grpname;
+
+ mutex_lock(&rza1_pctl->mutex);
+ gsel = pinctrl_generic_add_group(pctldev, grpname, grpins, npins,
+ NULL);
+ if (gsel < 0) {
+ mutex_unlock(&rza1_pctl->mutex);
+ return gsel;
+ }
+
+ fsel = pinmux_generic_add_function(pctldev, grpname, fngrps, 1,
+ mux_confs);
+ if (fsel < 0) {
+ ret = fsel;
+ goto remove_group;
+ }
+
+ dev_info(rza1_pctl->dev, "Parsed function and group %s with %d pins\n",
+ grpname, npins);
+
+ /* Create map where to retrieve function and mux settings from */
+ *num_maps = 0;
+ *map = kzalloc(sizeof(**map), GFP_KERNEL);
+ if (!*map) {
+ ret = -ENOMEM;
+ goto remove_function;
+ }
+
+ (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
+ (*map)->data.mux.group = np->name;
+ (*map)->data.mux.function = np->name;
+ *num_maps = 1;
+ mutex_unlock(&rza1_pctl->mutex);
+
+ return 0;
+
+remove_function:
+ pinmux_generic_remove_function(pctldev, fsel);
+
+remove_group:
+ pinctrl_generic_remove_group(pctldev, gsel);
+ mutex_unlock(&rza1_pctl->mutex);
+
+ dev_info(rza1_pctl->dev, "Unable to parse function and group %s\n",
+ grpname);
+
+ return ret;
+}
+
+static void rza1_dt_free_map(struct pinctrl_dev *pctldev,
+ struct pinctrl_map *map, unsigned int num_maps)
+{
+ kfree(map);
+}
+
+static const struct pinctrl_ops rza1_pinctrl_ops = {
+ .get_groups_count = pinctrl_generic_get_group_count,
+ .get_group_name = pinctrl_generic_get_group_name,
+ .get_group_pins = pinctrl_generic_get_group_pins,
+ .dt_node_to_map = rza1_dt_node_to_map,
+ .dt_free_map = rza1_dt_free_map,
+};
+
+/* ----------------------------------------------------------------------------
+ * pinmux operations
+ */
+
+/**
+ * rza1_set_mux() - retrieve pins from a group and apply their mux settings
+ *
+ * @pctldev: pin controller device
+ * @selector: function selector
+ * @group: group selector
+ */
+static int rza1_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
+ unsigned int group)
+{
+ struct rza1_pinctrl *rza1_pctl = pinctrl_dev_get_drvdata(pctldev);
+ struct rza1_mux_conf *mux_confs;
+ struct function_desc *func;
+ struct group_desc *grp;
+ int i;
+
+ grp = pinctrl_generic_get_group(pctldev, group);
+ if (!grp)
+ return -EINVAL;
+
+ func = pinmux_generic_get_function(pctldev, selector);
+ if (!func)
+ return -EINVAL;
+
+ mux_confs = (struct rza1_mux_conf *)func->data;
+ for (i = 0; i < grp->num_pins; ++i) {
+ int ret;
+
+ ret = rza1_pin_mux_single(rza1_pctl, &mux_confs[i]);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct pinmux_ops rza1_pinmux_ops = {
+ .get_functions_count = pinmux_generic_get_function_count,
+ .get_function_name = pinmux_generic_get_function_name,
+ .get_function_groups = pinmux_generic_get_function_groups,
+ .set_mux = rza1_set_mux,
+ .strict = true,
+};
+
+/* ----------------------------------------------------------------------------
+ * RZ/A1 pin controller driver operations
+ */
+
+static unsigned int rza1_count_gpio_chips(struct device_node *np)
+{
+ struct device_node *child;
+ unsigned int count = 0;
+
+ for_each_child_of_node(np, child) {
+ if (!of_property_read_bool(child, "gpio-controller"))
+ continue;
+
+ count++;
+ }
+
+ return count;
+}
+
+/**
+ * rza1_parse_gpiochip() - parse and register a gpio chip and pin range
+ *
+ * The gpio controller subnode shall provide a "gpio-ranges" list property as
+ * defined by gpio device tree binding documentation.
+ *
+ * @rza1_pctl: RZ/A1 pin controller device
+ * @np: of gpio-controller node
+ * @chip: gpio chip to register to gpiolib
+ * @range: pin range to register to pinctrl core
+ */
+static int rza1_parse_gpiochip(struct rza1_pinctrl *rza1_pctl,
+ struct device_node *np,
+ struct gpio_chip *chip,
+ struct pinctrl_gpio_range *range)
+{
+ const char *list_name = "gpio-ranges";
+ struct of_phandle_args of_args;
+ unsigned int gpioport;
+ u32 pinctrl_base;
+ int ret;
+
+ ret = of_parse_phandle_with_fixed_args(np, list_name, 3, 0, &of_args);
+ if (ret) {
+ dev_err(rza1_pctl->dev, "Unable to parse %s list property\n",
+ list_name);
+ return ret;
+ }
+
+ /*
+ * Find out on which port this gpio-chip maps to by inspecting the
+ * second argument of the "gpio-ranges" property.
+ */
+ pinctrl_base = of_args.args[1];
+ gpioport = RZA1_PIN_ID_TO_PORT(pinctrl_base);
+ if (gpioport >= RZA1_NPORTS) {
+ dev_err(rza1_pctl->dev,
+ "Invalid values in property %s\n", list_name);
+ return -EINVAL;
+ }
+
+ *chip = rza1_gpiochip_template;
+ chip->base = -1;
+ chip->label = devm_kasprintf(rza1_pctl->dev, GFP_KERNEL, "%pOFn",
+ np);
+ if (!chip->label)
+ return -ENOMEM;
+
+ chip->ngpio = of_args.args[2];
+ chip->of_node = np;
+ chip->parent = rza1_pctl->dev;
+
+ range->id = gpioport;
+ range->name = chip->label;
+ range->pin_base = range->base = pinctrl_base;
+ range->npins = of_args.args[2];
+ range->gc = chip;
+
+ ret = devm_gpiochip_add_data(rza1_pctl->dev, chip,
+ &rza1_pctl->ports[gpioport]);
+ if (ret)
+ return ret;
+
+ pinctrl_add_gpio_range(rza1_pctl->pctl, range);
+
+ dev_dbg(rza1_pctl->dev, "Parsed gpiochip %s with %d pins\n",
+ chip->label, chip->ngpio);
+
+ return 0;
+}
+
+/**
+ * rza1_gpio_register() - parse DT to collect gpio-chips and gpio-ranges
+ *
+ * @rza1_pctl: RZ/A1 pin controller device
+ */
+static int rza1_gpio_register(struct rza1_pinctrl *rza1_pctl)
+{
+ struct device_node *np = rza1_pctl->dev->of_node;
+ struct pinctrl_gpio_range *gpio_ranges;
+ struct gpio_chip *gpio_chips;
+ struct device_node *child;
+ unsigned int ngpiochips;
+ unsigned int i;
+ int ret;
+
+ ngpiochips = rza1_count_gpio_chips(np);
+ if (ngpiochips == 0) {
+ dev_dbg(rza1_pctl->dev, "No gpiochip registered\n");
+ return 0;
+ }
+
+ gpio_chips = devm_kcalloc(rza1_pctl->dev, ngpiochips,
+ sizeof(*gpio_chips), GFP_KERNEL);
+ gpio_ranges = devm_kcalloc(rza1_pctl->dev, ngpiochips,
+ sizeof(*gpio_ranges), GFP_KERNEL);
+ if (!gpio_chips || !gpio_ranges)
+ return -ENOMEM;
+
+ i = 0;
+ for_each_child_of_node(np, child) {
+ if (!of_property_read_bool(child, "gpio-controller"))
+ continue;
+
+ ret = rza1_parse_gpiochip(rza1_pctl, child, &gpio_chips[i],
+ &gpio_ranges[i]);
+ if (ret) {
+ of_node_put(child);
+ return ret;
+ }
+
+ ++i;
+ }
+
+ dev_info(rza1_pctl->dev, "Registered %u gpio controllers\n", i);
+
+ return 0;
+}
+
+/**
+ * rza1_pinctrl_register() - Enumerate pins, ports and gpiochips; register
+ * them to pinctrl and gpio cores.
+ *
+ * @rza1_pctl: RZ/A1 pin controller device
+ */
+static int rza1_pinctrl_register(struct rza1_pinctrl *rza1_pctl)
+{
+ struct pinctrl_pin_desc *pins;
+ struct rza1_port *ports;
+ unsigned int i;
+ int ret;
+
+ pins = devm_kcalloc(rza1_pctl->dev, RZA1_NPINS, sizeof(*pins),
+ GFP_KERNEL);
+ ports = devm_kcalloc(rza1_pctl->dev, RZA1_NPORTS, sizeof(*ports),
+ GFP_KERNEL);
+ if (!pins || !ports)
+ return -ENOMEM;
+
+ rza1_pctl->pins = pins;
+ rza1_pctl->desc.pins = pins;
+ rza1_pctl->desc.npins = RZA1_NPINS;
+ rza1_pctl->ports = ports;
+
+ for (i = 0; i < RZA1_NPINS; ++i) {
+ unsigned int pin = RZA1_PIN_ID_TO_PIN(i);
+ unsigned int port = RZA1_PIN_ID_TO_PORT(i);
+
+ pins[i].number = i;
+ pins[i].name = devm_kasprintf(rza1_pctl->dev, GFP_KERNEL,
+ "P%u-%u", port, pin);
+ if (!pins[i].name)
+ return -ENOMEM;
+
+ if (i % RZA1_PINS_PER_PORT == 0) {
+ /*
+ * Setup ports;
+ * they provide per-port lock and logical base address.
+ */
+ unsigned int port_id = RZA1_PIN_ID_TO_PORT(i);
+
+ ports[port_id].id = port_id;
+ ports[port_id].base = rza1_pctl->base;
+ ports[port_id].pins = &pins[i];
+ spin_lock_init(&ports[port_id].lock);
+ }
+ }
+
+ ret = devm_pinctrl_register_and_init(rza1_pctl->dev, &rza1_pctl->desc,
+ rza1_pctl, &rza1_pctl->pctl);
+ if (ret) {
+ dev_err(rza1_pctl->dev,
+ "RZ/A1 pin controller registration failed\n");
+ return ret;
+ }
+
+ ret = pinctrl_enable(rza1_pctl->pctl);
+ if (ret) {
+ dev_err(rza1_pctl->dev,
+ "RZ/A1 pin controller failed to start\n");
+ return ret;
+ }
+
+ ret = rza1_gpio_register(rza1_pctl);
+ if (ret) {
+ dev_err(rza1_pctl->dev, "RZ/A1 GPIO registration failed\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int rza1_pinctrl_probe(struct platform_device *pdev)
+{
+ struct rza1_pinctrl *rza1_pctl;
+ int ret;
+
+ rza1_pctl = devm_kzalloc(&pdev->dev, sizeof(*rza1_pctl), GFP_KERNEL);
+ if (!rza1_pctl)
+ return -ENOMEM;
+
+ rza1_pctl->dev = &pdev->dev;
+
+ rza1_pctl->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(rza1_pctl->base))
+ return PTR_ERR(rza1_pctl->base);
+
+ mutex_init(&rza1_pctl->mutex);
+
+ platform_set_drvdata(pdev, rza1_pctl);
+
+ rza1_pctl->desc.name = DRIVER_NAME;
+ rza1_pctl->desc.pctlops = &rza1_pinctrl_ops;
+ rza1_pctl->desc.pmxops = &rza1_pinmux_ops;
+ rza1_pctl->desc.owner = THIS_MODULE;
+ rza1_pctl->data = of_device_get_match_data(&pdev->dev);
+
+ ret = rza1_pinctrl_register(rza1_pctl);
+ if (ret)
+ return ret;
+
+ dev_info(&pdev->dev,
+ "RZ/A1 pin controller and gpio successfully registered\n");
+
+ return 0;
+}
+
+static const struct of_device_id rza1_pinctrl_of_match[] = {
+ {
+ /* RZ/A1H, RZ/A1M */
+ .compatible = "renesas,r7s72100-ports",
+ .data = &rza1h_pmx_conf,
+ },
+ {
+ /* RZ/A1L */
+ .compatible = "renesas,r7s72102-ports",
+ .data = &rza1l_pmx_conf,
+ },
+ { }
+};
+
+static struct platform_driver rza1_pinctrl_driver = {
+ .driver = {
+ .name = DRIVER_NAME,
+ .of_match_table = rza1_pinctrl_of_match,
+ },
+ .probe = rza1_pinctrl_probe,
+};
+
+static int __init rza1_pinctrl_init(void)
+{
+ return platform_driver_register(&rza1_pinctrl_driver);
+}
+core_initcall(rza1_pinctrl_init);
+
+MODULE_AUTHOR("Jacopo Mondi <jacopo+renesas@jmondi.org");
+MODULE_DESCRIPTION("Pin and gpio controller driver for Reneas RZ/A1 SoC");
+MODULE_LICENSE("GPL v2");
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Combined GPIO and pin controller support for Renesas RZ/A2 (R7S9210) SoC
+ *
+ * Copyright (C) 2018 Chris Brandt
+ */
+
+/*
+ * This pin controller/gpio combined driver supports Renesas devices of RZ/A2
+ * family.
+ */
+
+#include <linux/bitops.h>
+#include <linux/gpio/driver.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinmux.h>
+
+#include "../core.h"
+#include "../pinmux.h"
+
+#define DRIVER_NAME "pinctrl-rza2"
+
+#define RZA2_PINS_PER_PORT 8
+#define RZA2_PIN_ID_TO_PORT(id) ((id) / RZA2_PINS_PER_PORT)
+#define RZA2_PIN_ID_TO_PIN(id) ((id) % RZA2_PINS_PER_PORT)
+
+/*
+ * Use 16 lower bits [15:0] for pin identifier
+ * Use 16 higher bits [31:16] for pin mux function
+ */
+#define MUX_PIN_ID_MASK GENMASK(15, 0)
+#define MUX_FUNC_MASK GENMASK(31, 16)
+#define MUX_FUNC_OFFS 16
+#define MUX_FUNC(pinconf) ((pinconf & MUX_FUNC_MASK) >> MUX_FUNC_OFFS)
+
+static const char port_names[] = "0123456789ABCDEFGHJKLM";
+
+struct rza2_pinctrl_priv {
+ struct device *dev;
+ void __iomem *base;
+
+ struct pinctrl_pin_desc *pins;
+ struct pinctrl_desc desc;
+ struct pinctrl_dev *pctl;
+ struct pinctrl_gpio_range gpio_range;
+ int npins;
+};
+
+#define RZA2_PDR(port) (0x0000 + (port) * 2) /* Direction 16-bit */
+#define RZA2_PODR(port) (0x0040 + (port)) /* Output Data 8-bit */
+#define RZA2_PIDR(port) (0x0060 + (port)) /* Input Data 8-bit */
+#define RZA2_PMR(port) (0x0080 + (port)) /* Mode 8-bit */
+#define RZA2_DSCR(port) (0x0140 + (port) * 2) /* Drive 16-bit */
+#define RZA2_PFS(port, pin) (0x0200 + ((port) * 8) + (pin)) /* Fnct 8-bit */
+
+#define RZA2_PWPR 0x02ff /* Write Protect 8-bit */
+#define RZA2_PFENET 0x0820 /* Ethernet Pins 8-bit */
+#define RZA2_PPOC 0x0900 /* Dedicated Pins 32-bit */
+#define RZA2_PHMOMO 0x0980 /* Peripheral Pins 32-bit */
+#define RZA2_PCKIO 0x09d0 /* CKIO Drive 8-bit */
+
+#define RZA2_PDR_INPUT 0x02
+#define RZA2_PDR_OUTPUT 0x03
+#define RZA2_PDR_MASK 0x03
+
+#define PWPR_B0WI BIT(7) /* Bit Write Disable */
+#define PWPR_PFSWE BIT(6) /* PFS Register Write Enable */
+#define PFS_ISEL BIT(6) /* Interrupt Select */
+
+static void rza2_set_pin_function(void __iomem *pfc_base, u8 port, u8 pin,
+ u8 func)
+{
+ u16 mask16;
+ u16 reg16;
+ u8 reg8;
+
+ /* Set pin to 'Non-use (Hi-z input protection)' */
+ reg16 = readw(pfc_base + RZA2_PDR(port));
+ mask16 = RZA2_PDR_MASK << (pin * 2);
+ reg16 &= ~mask16;
+ writew(reg16, pfc_base + RZA2_PDR(port));
+
+ /* Temporarily switch to GPIO */
+ reg8 = readb(pfc_base + RZA2_PMR(port));
+ reg8 &= ~BIT(pin);
+ writeb(reg8, pfc_base + RZA2_PMR(port));
+
+ /* PFS Register Write Protect : OFF */
+ writeb(0x00, pfc_base + RZA2_PWPR); /* B0WI=0, PFSWE=0 */
+ writeb(PWPR_PFSWE, pfc_base + RZA2_PWPR); /* B0WI=0, PFSWE=1 */
+
+ /* Set Pin function (interrupt disabled, ISEL=0) */
+ writeb(func, pfc_base + RZA2_PFS(port, pin));
+
+ /* PFS Register Write Protect : ON */
+ writeb(0x00, pfc_base + RZA2_PWPR); /* B0WI=0, PFSWE=0 */
+ writeb(0x80, pfc_base + RZA2_PWPR); /* B0WI=1, PFSWE=0 */
+
+ /* Port Mode : Peripheral module pin functions */
+ reg8 = readb(pfc_base + RZA2_PMR(port));
+ reg8 |= BIT(pin);
+ writeb(reg8, pfc_base + RZA2_PMR(port));
+}
+
+static void rza2_pin_to_gpio(void __iomem *pfc_base, unsigned int offset,
+ u8 dir)
+{
+ u8 port = RZA2_PIN_ID_TO_PORT(offset);
+ u8 pin = RZA2_PIN_ID_TO_PIN(offset);
+ u16 mask16;
+ u16 reg16;
+
+ reg16 = readw(pfc_base + RZA2_PDR(port));
+ mask16 = RZA2_PDR_MASK << (pin * 2);
+ reg16 &= ~mask16;
+
+ if (dir)
+ reg16 |= RZA2_PDR_INPUT << (pin * 2); /* pin as input */
+ else
+ reg16 |= RZA2_PDR_OUTPUT << (pin * 2); /* pin as output */
+
+ writew(reg16, pfc_base + RZA2_PDR(port));
+}
+
+static int rza2_chip_get_direction(struct gpio_chip *chip, unsigned int offset)
+{
+ struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
+ u8 port = RZA2_PIN_ID_TO_PORT(offset);
+ u8 pin = RZA2_PIN_ID_TO_PIN(offset);
+ u16 reg16;
+
+ reg16 = readw(priv->base + RZA2_PDR(port));
+ reg16 = (reg16 >> (pin * 2)) & RZA2_PDR_MASK;
+
+ if (reg16 == RZA2_PDR_OUTPUT)
+ return GPIO_LINE_DIRECTION_OUT;
+
+ if (reg16 == RZA2_PDR_INPUT)
+ return GPIO_LINE_DIRECTION_IN;
+
+ /*
+ * This GPIO controller has a default Hi-Z state that is not input or
+ * output, so force the pin to input now.
+ */
+ rza2_pin_to_gpio(priv->base, offset, 1);
+
+ return GPIO_LINE_DIRECTION_IN;
+}
+
+static int rza2_chip_direction_input(struct gpio_chip *chip,
+ unsigned int offset)
+{
+ struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
+
+ rza2_pin_to_gpio(priv->base, offset, 1);
+
+ return 0;
+}
+
+static int rza2_chip_get(struct gpio_chip *chip, unsigned int offset)
+{
+ struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
+ u8 port = RZA2_PIN_ID_TO_PORT(offset);
+ u8 pin = RZA2_PIN_ID_TO_PIN(offset);
+
+ return !!(readb(priv->base + RZA2_PIDR(port)) & BIT(pin));
+}
+
+static void rza2_chip_set(struct gpio_chip *chip, unsigned int offset,
+ int value)
+{
+ struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
+ u8 port = RZA2_PIN_ID_TO_PORT(offset);
+ u8 pin = RZA2_PIN_ID_TO_PIN(offset);
+ u8 new_value;
+
+ new_value = readb(priv->base + RZA2_PODR(port));
+
+ if (value)
+ new_value |= BIT(pin);
+ else
+ new_value &= ~BIT(pin);
+
+ writeb(new_value, priv->base + RZA2_PODR(port));
+}
+
+static int rza2_chip_direction_output(struct gpio_chip *chip,
+ unsigned int offset, int val)
+{
+ struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
+
+ rza2_chip_set(chip, offset, val);
+ rza2_pin_to_gpio(priv->base, offset, 0);
+
+ return 0;
+}
+
+static const char * const rza2_gpio_names[] = {
+ "P0_0", "P0_1", "P0_2", "P0_3", "P0_4", "P0_5", "P0_6", "P0_7",
+ "P1_0", "P1_1", "P1_2", "P1_3", "P1_4", "P1_5", "P1_6", "P1_7",
+ "P2_0", "P2_1", "P2_2", "P2_3", "P2_4", "P2_5", "P2_6", "P2_7",
+ "P3_0", "P3_1", "P3_2", "P3_3", "P3_4", "P3_5", "P3_6", "P3_7",
+ "P4_0", "P4_1", "P4_2", "P4_3", "P4_4", "P4_5", "P4_6", "P4_7",
+ "P5_0", "P5_1", "P5_2", "P5_3", "P5_4", "P5_5", "P5_6", "P5_7",
+ "P6_0", "P6_1", "P6_2", "P6_3", "P6_4", "P6_5", "P6_6", "P6_7",
+ "P7_0", "P7_1", "P7_2", "P7_3", "P7_4", "P7_5", "P7_6", "P7_7",
+ "P8_0", "P8_1", "P8_2", "P8_3", "P8_4", "P8_5", "P8_6", "P8_7",
+ "P9_0", "P9_1", "P9_2", "P9_3", "P9_4", "P9_5", "P9_6", "P9_7",
+ "PA_0", "PA_1", "PA_2", "PA_3", "PA_4", "PA_5", "PA_6", "PA_7",
+ "PB_0", "PB_1", "PB_2", "PB_3", "PB_4", "PB_5", "PB_6", "PB_7",
+ "PC_0", "PC_1", "PC_2", "PC_3", "PC_4", "PC_5", "PC_6", "PC_7",
+ "PD_0", "PD_1", "PD_2", "PD_3", "PD_4", "PD_5", "PD_6", "PD_7",
+ "PE_0", "PE_1", "PE_2", "PE_3", "PE_4", "PE_5", "PE_6", "PE_7",
+ "PF_0", "PF_1", "PF_2", "PF_3", "PF_4", "PF_5", "PF_6", "PF_7",
+ "PG_0", "PG_1", "PG_2", "PG_3", "PG_4", "PG_5", "PG_6", "PG_7",
+ "PH_0", "PH_1", "PH_2", "PH_3", "PH_4", "PH_5", "PH_6", "PH_7",
+ /* port I does not exist */
+ "PJ_0", "PJ_1", "PJ_2", "PJ_3", "PJ_4", "PJ_5", "PJ_6", "PJ_7",
+ "PK_0", "PK_1", "PK_2", "PK_3", "PK_4", "PK_5", "PK_6", "PK_7",
+ "PL_0", "PL_1", "PL_2", "PL_3", "PL_4", "PL_5", "PL_6", "PL_7",
+ "PM_0", "PM_1", "PM_2", "PM_3", "PM_4", "PM_5", "PM_6", "PM_7",
+};
+
+static struct gpio_chip chip = {
+ .names = rza2_gpio_names,
+ .base = -1,
+ .get_direction = rza2_chip_get_direction,
+ .direction_input = rza2_chip_direction_input,
+ .direction_output = rza2_chip_direction_output,
+ .get = rza2_chip_get,
+ .set = rza2_chip_set,
+};
+
+static int rza2_gpio_register(struct rza2_pinctrl_priv *priv)
+{
+ struct device_node *np = priv->dev->of_node;
+ struct of_phandle_args of_args;
+ int ret;
+
+ chip.label = devm_kasprintf(priv->dev, GFP_KERNEL, "%pOFn", np);
+ chip.of_node = np;
+ chip.parent = priv->dev;
+ chip.ngpio = priv->npins;
+
+ ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0,
+ &of_args);
+ if (ret) {
+ dev_err(priv->dev, "Unable to parse gpio-ranges\n");
+ return ret;
+ }
+
+ if ((of_args.args[0] != 0) ||
+ (of_args.args[1] != 0) ||
+ (of_args.args[2] != priv->npins)) {
+ dev_err(priv->dev, "gpio-ranges does not match selected SOC\n");
+ return -EINVAL;
+ }
+ priv->gpio_range.id = 0;
+ priv->gpio_range.pin_base = priv->gpio_range.base = 0;
+ priv->gpio_range.npins = priv->npins;
+ priv->gpio_range.name = chip.label;
+ priv->gpio_range.gc = &chip;
+
+ /* Register our gpio chip with gpiolib */
+ ret = devm_gpiochip_add_data(priv->dev, &chip, priv);
+ if (ret)
+ return ret;
+
+ /* Register pin range with pinctrl core */
+ pinctrl_add_gpio_range(priv->pctl, &priv->gpio_range);
+
+ dev_dbg(priv->dev, "Registered gpio controller\n");
+
+ return 0;
+}
+
+static int rza2_pinctrl_register(struct rza2_pinctrl_priv *priv)
+{
+ struct pinctrl_pin_desc *pins;
+ unsigned int i;
+ int ret;
+
+ pins = devm_kcalloc(priv->dev, priv->npins, sizeof(*pins), GFP_KERNEL);
+ if (!pins)
+ return -ENOMEM;
+
+ priv->pins = pins;
+ priv->desc.pins = pins;
+ priv->desc.npins = priv->npins;
+
+ for (i = 0; i < priv->npins; i++) {
+ pins[i].number = i;
+ pins[i].name = rza2_gpio_names[i];
+ }
+
+ ret = devm_pinctrl_register_and_init(priv->dev, &priv->desc, priv,
+ &priv->pctl);
+ if (ret) {
+ dev_err(priv->dev, "pinctrl registration failed\n");
+ return ret;
+ }
+
+ ret = pinctrl_enable(priv->pctl);
+ if (ret) {
+ dev_err(priv->dev, "pinctrl enable failed\n");
+ return ret;
+ }
+
+ ret = rza2_gpio_register(priv);
+ if (ret) {
+ dev_err(priv->dev, "GPIO registration failed\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+/*
+ * For each DT node, create a single pin mapping. That pin mapping will only
+ * contain a single group of pins, and that group of pins will only have a
+ * single function that can be selected.
+ */
+static int rza2_dt_node_to_map(struct pinctrl_dev *pctldev,
+ struct device_node *np,
+ struct pinctrl_map **map,
+ unsigned int *num_maps)
+{
+ struct rza2_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
+ unsigned int *pins, *psel_val;
+ int i, ret, npins, gsel, fsel;
+ struct property *of_pins;
+ const char **pin_fn;
+
+ /* Find out how many pins to map */
+ of_pins = of_find_property(np, "pinmux", NULL);
+ if (!of_pins) {
+ dev_info(priv->dev, "Missing pinmux property\n");
+ return -ENOENT;
+ }
+ npins = of_pins->length / sizeof(u32);
+
+ pins = devm_kcalloc(priv->dev, npins, sizeof(*pins), GFP_KERNEL);
+ psel_val = devm_kcalloc(priv->dev, npins, sizeof(*psel_val),
+ GFP_KERNEL);
+ pin_fn = devm_kzalloc(priv->dev, sizeof(*pin_fn), GFP_KERNEL);
+ if (!pins || !psel_val || !pin_fn)
+ return -ENOMEM;
+
+ /* Collect pin locations and mux settings from DT properties */
+ for (i = 0; i < npins; ++i) {
+ u32 value;
+
+ ret = of_property_read_u32_index(np, "pinmux", i, &value);
+ if (ret)
+ return ret;
+ pins[i] = value & MUX_PIN_ID_MASK;
+ psel_val[i] = MUX_FUNC(value);
+ }
+
+ /* Register a single pin group listing all the pins we read from DT */
+ gsel = pinctrl_generic_add_group(pctldev, np->name, pins, npins, NULL);
+ if (gsel < 0)
+ return gsel;
+
+ /*
+ * Register a single group function where the 'data' is an array PSEL
+ * register values read from DT.
+ */
+ pin_fn[0] = np->name;
+ fsel = pinmux_generic_add_function(pctldev, np->name, pin_fn, 1,
+ psel_val);
+ if (fsel < 0) {
+ ret = fsel;
+ goto remove_group;
+ }
+
+ dev_dbg(priv->dev, "Parsed %pOF with %d pins\n", np, npins);
+
+ /* Create map where to retrieve function and mux settings from */
+ *num_maps = 0;
+ *map = kzalloc(sizeof(**map), GFP_KERNEL);
+ if (!*map) {
+ ret = -ENOMEM;
+ goto remove_function;
+ }
+
+ (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
+ (*map)->data.mux.group = np->name;
+ (*map)->data.mux.function = np->name;
+ *num_maps = 1;
+
+ return 0;
+
+remove_function:
+ pinmux_generic_remove_function(pctldev, fsel);
+
+remove_group:
+ pinctrl_generic_remove_group(pctldev, gsel);
+
+ dev_err(priv->dev, "Unable to parse DT node %s\n", np->name);
+
+ return ret;
+}
+
+static void rza2_dt_free_map(struct pinctrl_dev *pctldev,
+ struct pinctrl_map *map, unsigned int num_maps)
+{
+ kfree(map);
+}
+
+static const struct pinctrl_ops rza2_pinctrl_ops = {
+ .get_groups_count = pinctrl_generic_get_group_count,
+ .get_group_name = pinctrl_generic_get_group_name,
+ .get_group_pins = pinctrl_generic_get_group_pins,
+ .dt_node_to_map = rza2_dt_node_to_map,
+ .dt_free_map = rza2_dt_free_map,
+};
+
+static int rza2_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
+ unsigned int group)
+{
+ struct rza2_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
+ struct function_desc *func;
+ unsigned int i, *psel_val;
+ struct group_desc *grp;
+
+ grp = pinctrl_generic_get_group(pctldev, group);
+ if (!grp)
+ return -EINVAL;
+
+ func = pinmux_generic_get_function(pctldev, selector);
+ if (!func)
+ return -EINVAL;
+
+ psel_val = func->data;
+
+ for (i = 0; i < grp->num_pins; ++i) {
+ dev_dbg(priv->dev, "Setting P%c_%d to PSEL=%d\n",
+ port_names[RZA2_PIN_ID_TO_PORT(grp->pins[i])],
+ RZA2_PIN_ID_TO_PIN(grp->pins[i]),
+ psel_val[i]);
+ rza2_set_pin_function(
+ priv->base,
+ RZA2_PIN_ID_TO_PORT(grp->pins[i]),
+ RZA2_PIN_ID_TO_PIN(grp->pins[i]),
+ psel_val[i]);
+ }
+
+ return 0;
+}
+
+static const struct pinmux_ops rza2_pinmux_ops = {
+ .get_functions_count = pinmux_generic_get_function_count,
+ .get_function_name = pinmux_generic_get_function_name,
+ .get_function_groups = pinmux_generic_get_function_groups,
+ .set_mux = rza2_set_mux,
+ .strict = true,
+};
+
+static int rza2_pinctrl_probe(struct platform_device *pdev)
+{
+ struct rza2_pinctrl_priv *priv;
+ int ret;
+
+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->dev = &pdev->dev;
+
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ platform_set_drvdata(pdev, priv);
+
+ priv->npins = (int)(uintptr_t)of_device_get_match_data(&pdev->dev) *
+ RZA2_PINS_PER_PORT;
+
+ priv->desc.name = DRIVER_NAME;
+ priv->desc.pctlops = &rza2_pinctrl_ops;
+ priv->desc.pmxops = &rza2_pinmux_ops;
+ priv->desc.owner = THIS_MODULE;
+
+ ret = rza2_pinctrl_register(priv);
+ if (ret)
+ return ret;
+
+ dev_info(&pdev->dev, "Registered ports P0 - P%c\n",
+ port_names[priv->desc.npins / RZA2_PINS_PER_PORT - 1]);
+
+ return 0;
+}
+
+static const struct of_device_id rza2_pinctrl_of_match[] = {
+ { .compatible = "renesas,r7s9210-pinctrl", .data = (void *)22, },
+ { /* sentinel */ }
+};
+
+static struct platform_driver rza2_pinctrl_driver = {
+ .driver = {
+ .name = DRIVER_NAME,
+ .of_match_table = rza2_pinctrl_of_match,
+ },
+ .probe = rza2_pinctrl_probe,
+};
+
+static int __init rza2_pinctrl_init(void)
+{
+ return platform_driver_register(&rza2_pinctrl_driver);
+}
+core_initcall(rza2_pinctrl_init);
+
+MODULE_AUTHOR("Chris Brandt <chris.brandt@renesas.com>");
+MODULE_DESCRIPTION("Pin and gpio controller driver for RZ/A2 SoC");
+MODULE_LICENSE("GPL v2");
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2014-2018 Renesas Electronics Europe Limited
+ *
+ * Phil Edworthy <phil.edworthy@renesas.com>
+ * Based on a driver originally written by Michel Pollet at Renesas.
+ */
+
+#include <dt-bindings/pinctrl/rzn1-pinctrl.h>
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include "../core.h"
+#include "../pinconf.h"
+#include "../pinctrl-utils.h"
+
+/* Field positions and masks in the pinmux registers */
+#define RZN1_L1_PIN_DRIVE_STRENGTH 10
+#define RZN1_L1_PIN_DRIVE_STRENGTH_4MA 0
+#define RZN1_L1_PIN_DRIVE_STRENGTH_6MA 1
+#define RZN1_L1_PIN_DRIVE_STRENGTH_8MA 2
+#define RZN1_L1_PIN_DRIVE_STRENGTH_12MA 3
+#define RZN1_L1_PIN_PULL 8
+#define RZN1_L1_PIN_PULL_NONE 0
+#define RZN1_L1_PIN_PULL_UP 1
+#define RZN1_L1_PIN_PULL_DOWN 3
+#define RZN1_L1_FUNCTION 0
+#define RZN1_L1_FUNC_MASK 0xf
+#define RZN1_L1_FUNCTION_L2 0xf
+
+/*
+ * The hardware manual describes two levels of multiplexing, but it's more
+ * logical to think of the hardware as three levels, with level 3 consisting of
+ * the multiplexing for Ethernet MDIO signals.
+ *
+ * Level 1 functions go from 0 to 9, with level 1 function '15' (0xf) specifying
+ * that level 2 functions are used instead. Level 2 has a lot more options,
+ * going from 0 to 61. Level 3 allows selection of MDIO functions which can be
+ * floating, or one of seven internal peripherals. Unfortunately, there are two
+ * level 2 functions that can select MDIO, and two MDIO channels so we have four
+ * sets of level 3 functions.
+ *
+ * For this driver, we've compounded the numbers together, so:
+ * 0 to 9 is level 1
+ * 10 to 71 is 10 + level 2 number
+ * 72 to 79 is 72 + MDIO0 source for level 2 MDIO function.
+ * 80 to 87 is 80 + MDIO0 source for level 2 MDIO_E1 function.
+ * 88 to 95 is 88 + MDIO1 source for level 2 MDIO function.
+ * 96 to 103 is 96 + MDIO1 source for level 2 MDIO_E1 function.
+ * Examples:
+ * Function 28 corresponds UART0
+ * Function 73 corresponds to MDIO0 to GMAC0
+ *
+ * There are 170 configurable pins (called PL_GPIO in the datasheet).
+ */
+
+/*
+ * Structure detailing the HW registers on the RZ/N1 devices.
+ * Both the Level 1 mux registers and Level 2 mux registers have the same
+ * structure. The only difference is that Level 2 has additional MDIO registers
+ * at the end.
+ */
+struct rzn1_pinctrl_regs {
+ u32 conf[170];
+ u32 pad0[86];
+ u32 status_protect; /* 0x400 */
+ /* MDIO mux registers, level2 only */
+ u32 l2_mdio[2];
+};
+
+/**
+ * struct rzn1_pmx_func - describes rzn1 pinmux functions
+ * @name: the name of this specific function
+ * @groups: corresponding pin groups
+ * @num_groups: the number of groups
+ */
+struct rzn1_pmx_func {
+ const char *name;
+ const char **groups;
+ unsigned int num_groups;
+};
+
+/**
+ * struct rzn1_pin_group - describes an rzn1 pin group
+ * @name: the name of this specific pin group
+ * @func: the name of the function selected by this group
+ * @npins: the number of pins in this group array, i.e. the number of
+ * elements in .pins so we can iterate over that array
+ * @pins: array of pins. Needed due to pinctrl_ops.get_group_pins()
+ * @pin_ids: array of pin_ids, i.e. the value used to select the mux
+ */
+struct rzn1_pin_group {
+ const char *name;
+ const char *func;
+ unsigned int npins;
+ unsigned int *pins;
+ u8 *pin_ids;
+};
+
+struct rzn1_pinctrl {
+ struct device *dev;
+ struct clk *clk;
+ struct pinctrl_dev *pctl;
+ struct rzn1_pinctrl_regs __iomem *lev1;
+ struct rzn1_pinctrl_regs __iomem *lev2;
+ u32 lev1_protect_phys;
+ u32 lev2_protect_phys;
+ int mdio_func[2];
+
+ struct rzn1_pin_group *groups;
+ unsigned int ngroups;
+
+ struct rzn1_pmx_func *functions;
+ unsigned int nfunctions;
+};
+
+#define RZN1_PINS_PROP "pinmux"
+
+#define RZN1_PIN(pin) PINCTRL_PIN(pin, "pl_gpio"#pin)
+
+static const struct pinctrl_pin_desc rzn1_pins[] = {
+ RZN1_PIN(0), RZN1_PIN(1), RZN1_PIN(2), RZN1_PIN(3), RZN1_PIN(4),
+ RZN1_PIN(5), RZN1_PIN(6), RZN1_PIN(7), RZN1_PIN(8), RZN1_PIN(9),
+ RZN1_PIN(10), RZN1_PIN(11), RZN1_PIN(12), RZN1_PIN(13), RZN1_PIN(14),
+ RZN1_PIN(15), RZN1_PIN(16), RZN1_PIN(17), RZN1_PIN(18), RZN1_PIN(19),
+ RZN1_PIN(20), RZN1_PIN(21), RZN1_PIN(22), RZN1_PIN(23), RZN1_PIN(24),
+ RZN1_PIN(25), RZN1_PIN(26), RZN1_PIN(27), RZN1_PIN(28), RZN1_PIN(29),
+ RZN1_PIN(30), RZN1_PIN(31), RZN1_PIN(32), RZN1_PIN(33), RZN1_PIN(34),
+ RZN1_PIN(35), RZN1_PIN(36), RZN1_PIN(37), RZN1_PIN(38), RZN1_PIN(39),
+ RZN1_PIN(40), RZN1_PIN(41), RZN1_PIN(42), RZN1_PIN(43), RZN1_PIN(44),
+ RZN1_PIN(45), RZN1_PIN(46), RZN1_PIN(47), RZN1_PIN(48), RZN1_PIN(49),
+ RZN1_PIN(50), RZN1_PIN(51), RZN1_PIN(52), RZN1_PIN(53), RZN1_PIN(54),
+ RZN1_PIN(55), RZN1_PIN(56), RZN1_PIN(57), RZN1_PIN(58), RZN1_PIN(59),
+ RZN1_PIN(60), RZN1_PIN(61), RZN1_PIN(62), RZN1_PIN(63), RZN1_PIN(64),
+ RZN1_PIN(65), RZN1_PIN(66), RZN1_PIN(67), RZN1_PIN(68), RZN1_PIN(69),
+ RZN1_PIN(70), RZN1_PIN(71), RZN1_PIN(72), RZN1_PIN(73), RZN1_PIN(74),
+ RZN1_PIN(75), RZN1_PIN(76), RZN1_PIN(77), RZN1_PIN(78), RZN1_PIN(79),
+ RZN1_PIN(80), RZN1_PIN(81), RZN1_PIN(82), RZN1_PIN(83), RZN1_PIN(84),
+ RZN1_PIN(85), RZN1_PIN(86), RZN1_PIN(87), RZN1_PIN(88), RZN1_PIN(89),
+ RZN1_PIN(90), RZN1_PIN(91), RZN1_PIN(92), RZN1_PIN(93), RZN1_PIN(94),
+ RZN1_PIN(95), RZN1_PIN(96), RZN1_PIN(97), RZN1_PIN(98), RZN1_PIN(99),
+ RZN1_PIN(100), RZN1_PIN(101), RZN1_PIN(102), RZN1_PIN(103),
+ RZN1_PIN(104), RZN1_PIN(105), RZN1_PIN(106), RZN1_PIN(107),
+ RZN1_PIN(108), RZN1_PIN(109), RZN1_PIN(110), RZN1_PIN(111),
+ RZN1_PIN(112), RZN1_PIN(113), RZN1_PIN(114), RZN1_PIN(115),
+ RZN1_PIN(116), RZN1_PIN(117), RZN1_PIN(118), RZN1_PIN(119),
+ RZN1_PIN(120), RZN1_PIN(121), RZN1_PIN(122), RZN1_PIN(123),
+ RZN1_PIN(124), RZN1_PIN(125), RZN1_PIN(126), RZN1_PIN(127),
+ RZN1_PIN(128), RZN1_PIN(129), RZN1_PIN(130), RZN1_PIN(131),
+ RZN1_PIN(132), RZN1_PIN(133), RZN1_PIN(134), RZN1_PIN(135),
+ RZN1_PIN(136), RZN1_PIN(137), RZN1_PIN(138), RZN1_PIN(139),
+ RZN1_PIN(140), RZN1_PIN(141), RZN1_PIN(142), RZN1_PIN(143),
+ RZN1_PIN(144), RZN1_PIN(145), RZN1_PIN(146), RZN1_PIN(147),
+ RZN1_PIN(148), RZN1_PIN(149), RZN1_PIN(150), RZN1_PIN(151),
+ RZN1_PIN(152), RZN1_PIN(153), RZN1_PIN(154), RZN1_PIN(155),
+ RZN1_PIN(156), RZN1_PIN(157), RZN1_PIN(158), RZN1_PIN(159),
+ RZN1_PIN(160), RZN1_PIN(161), RZN1_PIN(162), RZN1_PIN(163),
+ RZN1_PIN(164), RZN1_PIN(165), RZN1_PIN(166), RZN1_PIN(167),
+ RZN1_PIN(168), RZN1_PIN(169),
+};
+
+enum {
+ LOCK_LEVEL1 = 0x1,
+ LOCK_LEVEL2 = 0x2,
+ LOCK_ALL = LOCK_LEVEL1 | LOCK_LEVEL2,
+};
+
+static void rzn1_hw_set_lock(struct rzn1_pinctrl *ipctl, u8 lock, u8 value)
+{
+ /*
+ * The pinmux configuration is locked by writing the physical address of
+ * the status_protect register to itself. It is unlocked by writing the
+ * address | 1.
+ */
+ if (lock & LOCK_LEVEL1) {
+ u32 val = ipctl->lev1_protect_phys | !(value & LOCK_LEVEL1);
+
+ writel(val, &ipctl->lev1->status_protect);
+ }
+
+ if (lock & LOCK_LEVEL2) {
+ u32 val = ipctl->lev2_protect_phys | !(value & LOCK_LEVEL2);
+
+ writel(val, &ipctl->lev2->status_protect);
+ }
+}
+
+static void rzn1_pinctrl_mdio_select(struct rzn1_pinctrl *ipctl, int mdio,
+ u32 func)
+{
+ if (ipctl->mdio_func[mdio] >= 0 && ipctl->mdio_func[mdio] != func)
+ dev_warn(ipctl->dev, "conflicting setting for mdio%d!\n", mdio);
+ ipctl->mdio_func[mdio] = func;
+
+ dev_dbg(ipctl->dev, "setting mdio%d to %u\n", mdio, func);
+
+ writel(func, &ipctl->lev2->l2_mdio[mdio]);
+}
+
+/*
+ * Using a composite pin description, set the hardware pinmux registers
+ * with the corresponding values.
+ * Make sure to unlock write protection and reset it afterward.
+ *
+ * NOTE: There is no protection for potential concurrency, it is assumed these
+ * calls are serialized already.
+ */
+static int rzn1_set_hw_pin_func(struct rzn1_pinctrl *ipctl, unsigned int pin,
+ u32 pin_config, u8 use_locks)
+{
+ u32 l1_cache;
+ u32 l2_cache;
+ u32 l1;
+ u32 l2;
+
+ /* Level 3 MDIO multiplexing */
+ if (pin_config >= RZN1_FUNC_MDIO0_HIGHZ &&
+ pin_config <= RZN1_FUNC_MDIO1_E1_SWITCH) {
+ int mdio_channel;
+ u32 mdio_func;
+
+ if (pin_config <= RZN1_FUNC_MDIO1_HIGHZ)
+ mdio_channel = 0;
+ else
+ mdio_channel = 1;
+
+ /* Get MDIO func, and convert the func to the level 2 number */
+ if (pin_config <= RZN1_FUNC_MDIO0_SWITCH) {
+ mdio_func = pin_config - RZN1_FUNC_MDIO0_HIGHZ;
+ pin_config = RZN1_FUNC_ETH_MDIO;
+ } else if (pin_config <= RZN1_FUNC_MDIO0_E1_SWITCH) {
+ mdio_func = pin_config - RZN1_FUNC_MDIO0_E1_HIGHZ;
+ pin_config = RZN1_FUNC_ETH_MDIO_E1;
+ } else if (pin_config <= RZN1_FUNC_MDIO1_SWITCH) {
+ mdio_func = pin_config - RZN1_FUNC_MDIO1_HIGHZ;
+ pin_config = RZN1_FUNC_ETH_MDIO;
+ } else {
+ mdio_func = pin_config - RZN1_FUNC_MDIO1_E1_HIGHZ;
+ pin_config = RZN1_FUNC_ETH_MDIO_E1;
+ }
+ rzn1_pinctrl_mdio_select(ipctl, mdio_channel, mdio_func);
+ }
+
+ /* Note here, we do not allow anything past the MDIO Mux values */
+ if (pin >= ARRAY_SIZE(ipctl->lev1->conf) ||
+ pin_config >= RZN1_FUNC_MDIO0_HIGHZ)
+ return -EINVAL;
+
+ l1 = readl(&ipctl->lev1->conf[pin]);
+ l1_cache = l1;
+ l2 = readl(&ipctl->lev2->conf[pin]);
+ l2_cache = l2;
+
+ dev_dbg(ipctl->dev, "setting func for pin %u to %u\n", pin, pin_config);
+
+ l1 &= ~(RZN1_L1_FUNC_MASK << RZN1_L1_FUNCTION);
+
+ if (pin_config < RZN1_FUNC_L2_OFFSET) {
+ l1 |= (pin_config << RZN1_L1_FUNCTION);
+ } else {
+ l1 |= (RZN1_L1_FUNCTION_L2 << RZN1_L1_FUNCTION);
+
+ l2 = pin_config - RZN1_FUNC_L2_OFFSET;
+ }
+
+ /* If either configuration changes, we update both anyway */
+ if (l1 != l1_cache || l2 != l2_cache) {
+ writel(l1, &ipctl->lev1->conf[pin]);
+ writel(l2, &ipctl->lev2->conf[pin]);
+ }
+
+ return 0;
+}
+
+static const struct rzn1_pin_group *rzn1_pinctrl_find_group_by_name(
+ const struct rzn1_pinctrl *ipctl, const char *name)
+{
+ unsigned int i;
+
+ for (i = 0; i < ipctl->ngroups; i++) {
+ if (!strcmp(ipctl->groups[i].name, name))
+ return &ipctl->groups[i];
+ }
+
+ return NULL;
+}
+
+static int rzn1_get_groups_count(struct pinctrl_dev *pctldev)
+{
+ struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+
+ return ipctl->ngroups;
+}
+
+static const char *rzn1_get_group_name(struct pinctrl_dev *pctldev,
+ unsigned int selector)
+{
+ struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+
+ return ipctl->groups[selector].name;
+}
+
+static int rzn1_get_group_pins(struct pinctrl_dev *pctldev,
+ unsigned int selector, const unsigned int **pins,
+ unsigned int *npins)
+{
+ struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+
+ if (selector >= ipctl->ngroups)
+ return -EINVAL;
+
+ *pins = ipctl->groups[selector].pins;
+ *npins = ipctl->groups[selector].npins;
+
+ return 0;
+}
+
+/*
+ * This function is called for each pinctl 'Function' node.
+ * Sub-nodes can be used to describe multiple 'Groups' for the 'Function'
+ * If there aren't any sub-nodes, the 'Group' is essentially the 'Function'.
+ * Each 'Group' uses pinmux = <...> to detail the pins and data used to select
+ * the functionality. Each 'Group' has optional pin configurations that apply
+ * to all pins in the 'Group'.
+ */
+static int rzn1_dt_node_to_map_one(struct pinctrl_dev *pctldev,
+ struct device_node *np,
+ struct pinctrl_map **map,
+ unsigned int *num_maps)
+{
+ struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct rzn1_pin_group *grp;
+ unsigned long *configs = NULL;
+ unsigned int reserved_maps = *num_maps;
+ unsigned int num_configs = 0;
+ unsigned int reserve = 1;
+ int ret;
+
+ dev_dbg(ipctl->dev, "processing node %pOF\n", np);
+
+ grp = rzn1_pinctrl_find_group_by_name(ipctl, np->name);
+ if (!grp) {
+ dev_err(ipctl->dev, "unable to find group for node %pOF\n", np);
+
+ return -EINVAL;
+ }
+
+ /* Get the group's pin configuration */
+ ret = pinconf_generic_parse_dt_config(np, pctldev, &configs,
+ &num_configs);
+ if (ret < 0) {
+ dev_err(ipctl->dev, "%pOF: could not parse property\n", np);
+
+ return ret;
+ }
+
+ if (num_configs)
+ reserve++;
+
+ /* Increase the number of maps to cover this group */
+ ret = pinctrl_utils_reserve_map(pctldev, map, &reserved_maps, num_maps,
+ reserve);
+ if (ret < 0)
+ goto out;
+
+ /* Associate the group with the function */
+ ret = pinctrl_utils_add_map_mux(pctldev, map, &reserved_maps, num_maps,
+ grp->name, grp->func);
+ if (ret < 0)
+ goto out;
+
+ if (num_configs) {
+ /* Associate the group's pin configuration with the group */
+ ret = pinctrl_utils_add_map_configs(pctldev, map,
+ &reserved_maps, num_maps, grp->name,
+ configs, num_configs,
+ PIN_MAP_TYPE_CONFIGS_GROUP);
+ if (ret < 0)
+ goto out;
+ }
+
+ dev_dbg(pctldev->dev, "maps: function %s group %s (%d pins)\n",
+ grp->func, grp->name, grp->npins);
+
+out:
+ kfree(configs);
+
+ return ret;
+}
+
+static int rzn1_dt_node_to_map(struct pinctrl_dev *pctldev,
+ struct device_node *np,
+ struct pinctrl_map **map,
+ unsigned int *num_maps)
+{
+ struct device_node *child;
+ int ret;
+
+ *map = NULL;
+ *num_maps = 0;
+
+ ret = rzn1_dt_node_to_map_one(pctldev, np, map, num_maps);
+ if (ret < 0)
+ return ret;
+
+ for_each_child_of_node(np, child) {
+ ret = rzn1_dt_node_to_map_one(pctldev, child, map, num_maps);
+ if (ret < 0) {
+ of_node_put(child);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static const struct pinctrl_ops rzn1_pctrl_ops = {
+ .get_groups_count = rzn1_get_groups_count,
+ .get_group_name = rzn1_get_group_name,
+ .get_group_pins = rzn1_get_group_pins,
+ .dt_node_to_map = rzn1_dt_node_to_map,
+ .dt_free_map = pinctrl_utils_free_map,
+};
+
+static int rzn1_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
+{
+ struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+
+ return ipctl->nfunctions;
+}
+
+static const char *rzn1_pmx_get_func_name(struct pinctrl_dev *pctldev,
+ unsigned int selector)
+{
+ struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+
+ return ipctl->functions[selector].name;
+}
+
+static int rzn1_pmx_get_groups(struct pinctrl_dev *pctldev,
+ unsigned int selector,
+ const char * const **groups,
+ unsigned int * const num_groups)
+{
+ struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+
+ *groups = ipctl->functions[selector].groups;
+ *num_groups = ipctl->functions[selector].num_groups;
+
+ return 0;
+}
+
+static int rzn1_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
+ unsigned int group)
+{
+ struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ struct rzn1_pin_group *grp = &ipctl->groups[group];
+ unsigned int i, grp_pins = grp->npins;
+
+ dev_dbg(ipctl->dev, "set mux %s(%d) group %s(%d)\n",
+ ipctl->functions[selector].name, selector, grp->name, group);
+
+ rzn1_hw_set_lock(ipctl, LOCK_ALL, LOCK_ALL);
+ for (i = 0; i < grp_pins; i++)
+ rzn1_set_hw_pin_func(ipctl, grp->pins[i], grp->pin_ids[i], 0);
+ rzn1_hw_set_lock(ipctl, LOCK_ALL, 0);
+
+ return 0;
+}
+
+static const struct pinmux_ops rzn1_pmx_ops = {
+ .get_functions_count = rzn1_pmx_get_funcs_count,
+ .get_function_name = rzn1_pmx_get_func_name,
+ .get_function_groups = rzn1_pmx_get_groups,
+ .set_mux = rzn1_set_mux,
+};
+
+static int rzn1_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
+ unsigned long *config)
+{
+ struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ enum pin_config_param param = pinconf_to_config_param(*config);
+ static const u32 reg_drive[4] = { 4, 6, 8, 12 };
+ u32 pull, drive, l1mux;
+ u32 l1, l2, arg = 0;
+
+ if (pin >= ARRAY_SIZE(ipctl->lev1->conf))
+ return -EINVAL;
+
+ l1 = readl(&ipctl->lev1->conf[pin]);
+
+ l1mux = l1 & RZN1_L1_FUNC_MASK;
+ pull = (l1 >> RZN1_L1_PIN_PULL) & 0x3;
+ drive = (l1 >> RZN1_L1_PIN_DRIVE_STRENGTH) & 0x3;
+
+ switch (param) {
+ case PIN_CONFIG_BIAS_PULL_UP:
+ if (pull != RZN1_L1_PIN_PULL_UP)
+ return -EINVAL;
+ break;
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ if (pull != RZN1_L1_PIN_PULL_DOWN)
+ return -EINVAL;
+ break;
+ case PIN_CONFIG_BIAS_DISABLE:
+ if (pull != RZN1_L1_PIN_PULL_NONE)
+ return -EINVAL;
+ break;
+ case PIN_CONFIG_DRIVE_STRENGTH:
+ arg = reg_drive[drive];
+ break;
+ case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
+ l2 = readl(&ipctl->lev2->conf[pin]);
+ if (l1mux == RZN1_L1_FUNCTION_L2) {
+ if (l2 != 0)
+ return -EINVAL;
+ } else if (l1mux != RZN1_FUNC_HIGHZ) {
+ return -EINVAL;
+ }
+ break;
+ default:
+ return -ENOTSUPP;
+ }
+
+ *config = pinconf_to_config_packed(param, arg);
+
+ return 0;
+}
+
+static int rzn1_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
+ unsigned long *configs, unsigned int num_configs)
+{
+ struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ enum pin_config_param param;
+ unsigned int i;
+ u32 l1, l1_cache;
+ u32 drv;
+ u32 arg;
+
+ if (pin >= ARRAY_SIZE(ipctl->lev1->conf))
+ return -EINVAL;
+
+ l1 = readl(&ipctl->lev1->conf[pin]);
+ l1_cache = l1;
+
+ for (i = 0; i < num_configs; i++) {
+ param = pinconf_to_config_param(configs[i]);
+ arg = pinconf_to_config_argument(configs[i]);
+
+ switch (param) {
+ case PIN_CONFIG_BIAS_PULL_UP:
+ dev_dbg(ipctl->dev, "set pin %d pull up\n", pin);
+ l1 &= ~(0x3 << RZN1_L1_PIN_PULL);
+ l1 |= (RZN1_L1_PIN_PULL_UP << RZN1_L1_PIN_PULL);
+ break;
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ dev_dbg(ipctl->dev, "set pin %d pull down\n", pin);
+ l1 &= ~(0x3 << RZN1_L1_PIN_PULL);
+ l1 |= (RZN1_L1_PIN_PULL_DOWN << RZN1_L1_PIN_PULL);
+ break;
+ case PIN_CONFIG_BIAS_DISABLE:
+ dev_dbg(ipctl->dev, "set pin %d bias off\n", pin);
+ l1 &= ~(0x3 << RZN1_L1_PIN_PULL);
+ l1 |= (RZN1_L1_PIN_PULL_NONE << RZN1_L1_PIN_PULL);
+ break;
+ case PIN_CONFIG_DRIVE_STRENGTH:
+ dev_dbg(ipctl->dev, "set pin %d drv %umA\n", pin, arg);
+ switch (arg) {
+ case 4:
+ drv = RZN1_L1_PIN_DRIVE_STRENGTH_4MA;
+ break;
+ case 6:
+ drv = RZN1_L1_PIN_DRIVE_STRENGTH_6MA;
+ break;
+ case 8:
+ drv = RZN1_L1_PIN_DRIVE_STRENGTH_8MA;
+ break;
+ case 12:
+ drv = RZN1_L1_PIN_DRIVE_STRENGTH_12MA;
+ break;
+ default:
+ dev_err(ipctl->dev,
+ "Drive strength %umA not supported\n",
+ arg);
+
+ return -EINVAL;
+ }
+
+ l1 &= ~(0x3 << RZN1_L1_PIN_DRIVE_STRENGTH);
+ l1 |= (drv << RZN1_L1_PIN_DRIVE_STRENGTH);
+ break;
+
+ case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
+ dev_dbg(ipctl->dev, "set pin %d High-Z\n", pin);
+ l1 &= ~RZN1_L1_FUNC_MASK;
+ l1 |= RZN1_FUNC_HIGHZ;
+ break;
+ default:
+ return -ENOTSUPP;
+ }
+ }
+
+ if (l1 != l1_cache) {
+ rzn1_hw_set_lock(ipctl, LOCK_LEVEL1, LOCK_LEVEL1);
+ writel(l1, &ipctl->lev1->conf[pin]);
+ rzn1_hw_set_lock(ipctl, LOCK_LEVEL1, 0);
+ }
+
+ return 0;
+}
+
+static int rzn1_pinconf_group_get(struct pinctrl_dev *pctldev,
+ unsigned int selector,
+ unsigned long *config)
+{
+ struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ struct rzn1_pin_group *grp = &ipctl->groups[selector];
+ unsigned long old = 0;
+ unsigned int i;
+
+ dev_dbg(ipctl->dev, "group get %s selector:%u\n", grp->name, selector);
+
+ for (i = 0; i < grp->npins; i++) {
+ if (rzn1_pinconf_get(pctldev, grp->pins[i], config))
+ return -ENOTSUPP;
+
+ /* configs do not match between two pins */
+ if (i && (old != *config))
+ return -ENOTSUPP;
+
+ old = *config;
+ }
+
+ return 0;
+}
+
+static int rzn1_pinconf_group_set(struct pinctrl_dev *pctldev,
+ unsigned int selector,
+ unsigned long *configs,
+ unsigned int num_configs)
+{
+ struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ struct rzn1_pin_group *grp = &ipctl->groups[selector];
+ unsigned int i;
+ int ret;
+
+ dev_dbg(ipctl->dev, "group set %s selector:%u configs:%p/%d\n",
+ grp->name, selector, configs, num_configs);
+
+ for (i = 0; i < grp->npins; i++) {
+ unsigned int pin = grp->pins[i];
+
+ ret = rzn1_pinconf_set(pctldev, pin, configs, num_configs);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct pinconf_ops rzn1_pinconf_ops = {
+ .is_generic = true,
+ .pin_config_get = rzn1_pinconf_get,
+ .pin_config_set = rzn1_pinconf_set,
+ .pin_config_group_get = rzn1_pinconf_group_get,
+ .pin_config_group_set = rzn1_pinconf_group_set,
+ .pin_config_config_dbg_show = pinconf_generic_dump_config,
+};
+
+static struct pinctrl_desc rzn1_pinctrl_desc = {
+ .pctlops = &rzn1_pctrl_ops,
+ .pmxops = &rzn1_pmx_ops,
+ .confops = &rzn1_pinconf_ops,
+ .owner = THIS_MODULE,
+};
+
+static int rzn1_pinctrl_parse_groups(struct device_node *np,
+ struct rzn1_pin_group *grp,
+ struct rzn1_pinctrl *ipctl)
+{
+ const __be32 *list;
+ unsigned int i;
+ int size;
+
+ dev_dbg(ipctl->dev, "%s: %s\n", __func__, np->name);
+
+ /* Initialise group */
+ grp->name = np->name;
+
+ /*
+ * The binding format is
+ * pinmux = <PIN_FUNC_ID CONFIG ...>,
+ * do sanity check and calculate pins number
+ */
+ list = of_get_property(np, RZN1_PINS_PROP, &size);
+ if (!list) {
+ dev_err(ipctl->dev,
+ "no " RZN1_PINS_PROP " property in node %pOF\n", np);
+
+ return -EINVAL;
+ }
+
+ if (!size) {
+ dev_err(ipctl->dev, "Invalid " RZN1_PINS_PROP " in node %pOF\n",
+ np);
+
+ return -EINVAL;
+ }
+
+ grp->npins = size / sizeof(list[0]);
+ grp->pin_ids = devm_kmalloc_array(ipctl->dev,
+ grp->npins, sizeof(grp->pin_ids[0]),
+ GFP_KERNEL);
+ grp->pins = devm_kmalloc_array(ipctl->dev,
+ grp->npins, sizeof(grp->pins[0]),
+ GFP_KERNEL);
+ if (!grp->pin_ids || !grp->pins)
+ return -ENOMEM;
+
+ for (i = 0; i < grp->npins; i++) {
+ u32 pin_id = be32_to_cpu(*list++);
+
+ grp->pins[i] = pin_id & 0xff;
+ grp->pin_ids[i] = (pin_id >> 8) & 0x7f;
+ }
+
+ return grp->npins;
+}
+
+static int rzn1_pinctrl_count_function_groups(struct device_node *np)
+{
+ struct device_node *child;
+ int count = 0;
+
+ if (of_property_count_u32_elems(np, RZN1_PINS_PROP) > 0)
+ count++;
+
+ for_each_child_of_node(np, child) {
+ if (of_property_count_u32_elems(child, RZN1_PINS_PROP) > 0)
+ count++;
+ }
+
+ return count;
+}
+
+static int rzn1_pinctrl_parse_functions(struct device_node *np,
+ struct rzn1_pinctrl *ipctl,
+ unsigned int index)
+{
+ struct rzn1_pmx_func *func;
+ struct rzn1_pin_group *grp;
+ struct device_node *child;
+ unsigned int i = 0;
+ int ret;
+
+ func = &ipctl->functions[index];
+
+ /* Initialise function */
+ func->name = np->name;
+ func->num_groups = rzn1_pinctrl_count_function_groups(np);
+ if (func->num_groups == 0) {
+ dev_err(ipctl->dev, "no groups defined in %pOF\n", np);
+ return -EINVAL;
+ }
+ dev_dbg(ipctl->dev, "function %s has %d groups\n",
+ np->name, func->num_groups);
+
+ func->groups = devm_kmalloc_array(ipctl->dev,
+ func->num_groups, sizeof(char *),
+ GFP_KERNEL);
+ if (!func->groups)
+ return -ENOMEM;
+
+ if (of_property_count_u32_elems(np, RZN1_PINS_PROP) > 0) {
+ func->groups[i] = np->name;
+ grp = &ipctl->groups[ipctl->ngroups];
+ grp->func = func->name;
+ ret = rzn1_pinctrl_parse_groups(np, grp, ipctl);
+ if (ret < 0)
+ return ret;
+ i++;
+ ipctl->ngroups++;
+ }
+
+ for_each_child_of_node(np, child) {
+ func->groups[i] = child->name;
+ grp = &ipctl->groups[ipctl->ngroups];
+ grp->func = func->name;
+ ret = rzn1_pinctrl_parse_groups(child, grp, ipctl);
+ if (ret < 0) {
+ of_node_put(child);
+ return ret;
+ }
+ i++;
+ ipctl->ngroups++;
+ }
+
+ dev_dbg(ipctl->dev, "function %s parsed %u/%u groups\n",
+ np->name, i, func->num_groups);
+
+ return 0;
+}
+
+static int rzn1_pinctrl_probe_dt(struct platform_device *pdev,
+ struct rzn1_pinctrl *ipctl)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct device_node *child;
+ unsigned int maxgroups = 0;
+ unsigned int i = 0;
+ int nfuncs = 0;
+ int ret;
+
+ nfuncs = of_get_child_count(np);
+ if (nfuncs <= 0)
+ return 0;
+
+ ipctl->nfunctions = nfuncs;
+ ipctl->functions = devm_kmalloc_array(&pdev->dev, nfuncs,
+ sizeof(*ipctl->functions),
+ GFP_KERNEL);
+ if (!ipctl->functions)
+ return -ENOMEM;
+
+ ipctl->ngroups = 0;
+ for_each_child_of_node(np, child)
+ maxgroups += rzn1_pinctrl_count_function_groups(child);
+
+ ipctl->groups = devm_kmalloc_array(&pdev->dev,
+ maxgroups,
+ sizeof(*ipctl->groups),
+ GFP_KERNEL);
+ if (!ipctl->groups)
+ return -ENOMEM;
+
+ for_each_child_of_node(np, child) {
+ ret = rzn1_pinctrl_parse_functions(child, ipctl, i++);
+ if (ret < 0) {
+ of_node_put(child);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static int rzn1_pinctrl_probe(struct platform_device *pdev)
+{
+ struct rzn1_pinctrl *ipctl;
+ struct resource *res;
+ int ret;
+
+ /* Create state holders etc for this driver */
+ ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
+ if (!ipctl)
+ return -ENOMEM;
+
+ ipctl->mdio_func[0] = -1;
+ ipctl->mdio_func[1] = -1;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ ipctl->lev1_protect_phys = (u32)res->start + 0x400;
+ ipctl->lev1 = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(ipctl->lev1))
+ return PTR_ERR(ipctl->lev1);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ ipctl->lev2_protect_phys = (u32)res->start + 0x400;
+ ipctl->lev2 = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(ipctl->lev2))
+ return PTR_ERR(ipctl->lev2);
+
+ ipctl->clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(ipctl->clk))
+ return PTR_ERR(ipctl->clk);
+ ret = clk_prepare_enable(ipctl->clk);
+ if (ret)
+ return ret;
+
+ ipctl->dev = &pdev->dev;
+ rzn1_pinctrl_desc.name = dev_name(&pdev->dev);
+ rzn1_pinctrl_desc.pins = rzn1_pins;
+ rzn1_pinctrl_desc.npins = ARRAY_SIZE(rzn1_pins);
+
+ ret = rzn1_pinctrl_probe_dt(pdev, ipctl);
+ if (ret) {
+ dev_err(&pdev->dev, "fail to probe dt properties\n");
+ goto err_clk;
+ }
+
+ platform_set_drvdata(pdev, ipctl);
+
+ ret = devm_pinctrl_register_and_init(&pdev->dev, &rzn1_pinctrl_desc,
+ ipctl, &ipctl->pctl);
+ if (ret) {
+ dev_err(&pdev->dev, "could not register rzn1 pinctrl driver\n");
+ goto err_clk;
+ }
+
+ ret = pinctrl_enable(ipctl->pctl);
+ if (ret)
+ goto err_clk;
+
+ dev_info(&pdev->dev, "probed\n");
+
+ return 0;
+
+err_clk:
+ clk_disable_unprepare(ipctl->clk);
+
+ return ret;
+}
+
+static int rzn1_pinctrl_remove(struct platform_device *pdev)
+{
+ struct rzn1_pinctrl *ipctl = platform_get_drvdata(pdev);
+
+ clk_disable_unprepare(ipctl->clk);
+
+ return 0;
+}
+
+static const struct of_device_id rzn1_pinctrl_match[] = {
+ { .compatible = "renesas,rzn1-pinctrl", },
+ {}
+};
+MODULE_DEVICE_TABLE(of, rzn1_pinctrl_match);
+
+static struct platform_driver rzn1_pinctrl_driver = {
+ .probe = rzn1_pinctrl_probe,
+ .remove = rzn1_pinctrl_remove,
+ .driver = {
+ .name = "rzn1-pinctrl",
+ .of_match_table = rzn1_pinctrl_match,
+ },
+};
+
+static int __init _pinctrl_drv_register(void)
+{
+ return platform_driver_register(&rzn1_pinctrl_driver);
+}
+subsys_initcall(_pinctrl_drv_register);
+
+MODULE_AUTHOR("Phil Edworthy <phil.edworthy@renesas.com>");
+MODULE_DESCRIPTION("Renesas RZ/N1 pinctrl driver");
+MODULE_LICENSE("GPL v2");
projects / linux.git / commitdiff