riscv: dts: starfive: add assigned-clock* to limit frquency

In JH7110 SoC, we need to go by-pass mode, so we need add the
assigned-clock* properties to limit clock frquency.

Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index c4f389a9309b9012bd7865b879e1d182eba4a8f5..5cdecbfa67c0be72140788030bf1fd3c2f36f550 100644 (file)
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -250,6 +250,8 @@
 
 &mmc0 {
        max-frequency = <100000000>;
+       assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
+       assigned-clock-rates = <50000000>;
        bus-width = <8>;
        cap-mmc-highspeed;
        mmc-ddr-1_8v;
@@ -266,6 +268,8 @@
 
 &mmc1 {
        max-frequency = <100000000>;
+       assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
+       assigned-clock-rates = <50000000>;
        bus-width = <4>;
        no-sdio;
        no-mmc;