arm64: dts: imx8mp-evk: correct pcie pad settings

According to RM bit layout, BIT3 and BIT0 are reserved.
  8  7   6   5   4   3  2 1  0
  PE HYS PUE ODE FSEL X  DSE  X

Although function is not broken, we should not set reserved bit.

Fixes: d50650500064 ("arm64: dts: imx8mp-evk: Add PCIe support")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Marco Felsch <m.felsch@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index 9f1469db554d3e0f85c8dccc962726a20a722c64..b4c1ef2559f2045920504b3ff26669163fc70009 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -544,14 +544,14 @@
 
        pinctrl_pcie0: pcie0grp {
                fsl,pins = <
-                       MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B    0x61 /* open drain, pull up */
-                       MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07      0x41
+                       MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B    0x60 /* open drain, pull up */
+                       MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07      0x40
                >;
        };
 
        pinctrl_pcie0_reg: pcie0reggrp {
                fsl,pins = <
-                       MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06      0x41
+                       MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06      0x40
                >;
        };