ASoC: fsl_micfil: explicitly clear software reset bit

[ Upstream commit 292709b9cf3ba470af94b62c9bb60284cc581b79 ]

SRES is self-cleared bit, but REG_MICFIL_CTRL1 is defined as
non volatile register, it still remain in regmap cache after set,
then every update of REG_MICFIL_CTRL1, software reset happens.
to avoid this, clear it explicitly.

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Link: https://lore.kernel.org/r/1651925654-32060-1-git-send-email-shengjiu.wang@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/sound/soc/fsl/fsl_micfil.c b/sound/soc/fsl/fsl_micfil.c
index 9f90989ac59a6f48b38d6e3d4ab2d1f3e63ce92b..cb84d95c3aac147d26dd173805889b59b4117216 100644 (file)
--- a/sound/soc/fsl/fsl_micfil.c
+++ b/sound/soc/fsl/fsl_micfil.c
@@ -191,6 +191,17 @@ static int fsl_micfil_reset(struct device *dev)
                return ret;
        }
 
+       /*
+        * SRES is self-cleared bit, but REG_MICFIL_CTRL1 is defined
+        * as non-volatile register, so SRES still remain in regmap
+        * cache after set, that every update of REG_MICFIL_CTRL1,
+        * software reset happens. so clear it explicitly.
+        */
+       ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
+                               MICFIL_CTRL1_SRES);
+       if (ret)
+               return ret;
+
        return 0;
 }