KVM: x86/pmu: Expand the comment about what bits are check emulating events

Expand the comment about what bits are and aren't checked when emulating
PMC events in software.  As pointed out by Jim, AMD's mask includes bits
35:32, which on Intel overlap with the IN_TX and IN_TXCP bits (32 and 33)
as well as reserved bits (34 and 45).

Checking The IN_TX* bits is actually correct, as it's safe to assert that
the vCPU can't be in an HLE/RTM transaction if KVM is emulating an
instruction, i.e. KVM *shouldn't count if either of those bits is set.

For the reserved bits, KVM is has equal odds of being right if Intel adds
new behavior, i.e. ignoring them is just as likely to be correct as
checking them.

Opportunistically explain *why* the other flags aren't checked.

Suggested-by: Jim Mattson <jmattson@google.com>
Link: https://lore.kernel.org/r/20231110022857.1273836-9-seanjc@google.com
Signed-off-by: Sean Christopherson <seanjc@google.com>

diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c
index f40d8c1edca9665fc06085294e4d044dbdaac464..d891a954b45ac9365b72d1e604458825efd7bcab 100644 (file)
--- a/arch/x86/kvm/pmu.c
+++ b/arch/x86/kvm/pmu.c
@@ -860,7 +860,20 @@ void kvm_pmu_trigger_event(struct kvm_vcpu *vcpu, u64 eventsel)
                if (!pmc_event_is_allowed(pmc))
                        continue;
 
-               /* Ignore checks for edge detect, pin control, invert and CMASK bits */
+               /*
+                * Ignore checks for edge detect (all events currently emulated
+                * but KVM are always rising edges), pin control (unsupported
+                * by modern CPUs), and counter mask and its invert flag (KVM
+                * doesn't emulate multiple events in a single clock cycle).
+                *
+                * Note, the uppermost nibble of AMD's mask overlaps Intel's
+                * IN_TX (bit 32) and IN_TXCP (bit 33), as well as two reserved
+                * bits (bits 35:34).  Checking the "in HLE/RTM transaction"
+                * flags is correct as the vCPU can't be in a transaction if
+                * KVM is emulating an instruction.  Checking the reserved bits
+                * might be wrong if they are defined in the future, but so
+                * could ignoring them, so do the simple thing for now.
+                */
                if ((pmc->eventsel ^ eventsel) & AMD64_RAW_EVENT_MASK_NB)
                        continue;