return ret;
}
-static uint32_t pflash_read(PFlashCFI02 *pfl, hwaddr offset,
- int width, int be)
+static uint64_t pflash_read(void *opaque, hwaddr offset, unsigned int width)
{
+ PFlashCFI02 *pfl = opaque;
hwaddr boff;
- uint32_t ret;
+ uint64_t ret;
ret = -1;
/* Lazy reset to ROMD mode after a certain amount of read accesses */
default:
ret = pflash_data_read(pfl, offset, width);
}
- DPRINTF("%s: ID " TARGET_FMT_plx " %" PRIx32 "\n", __func__, boff, ret);
+ DPRINTF("%s: ID " TARGET_FMT_plx " %" PRIx64 "\n", __func__, boff, ret);
break;
case 0xA0:
case 0x10:
case 0x30:
/* Status register read */
ret = pfl->status;
- DPRINTF("%s: status %" PRIx32 "\n", __func__, ret);
+ DPRINTF("%s: status %" PRIx64 "\n", __func__, ret);
toggle_dq6(pfl);
break;
case 0x98:
}
/* update flash content on disk */
-static void pflash_update(PFlashCFI02 *pfl, int offset,
- int size)
+static void pflash_update(PFlashCFI02 *pfl, int offset, int size)
{
int offset_end;
if (pfl->blk) {
}
}
-static void pflash_write(PFlashCFI02 *pfl, hwaddr offset,
- uint32_t value, int width, int be)
+static void pflash_write(void *opaque, hwaddr offset, uint64_t value,
+ unsigned int width)
{
+ PFlashCFI02 *pfl = opaque;
hwaddr boff;
uint8_t *p;
uint8_t cmd;
pfl->cmd = 0;
}
-static uint64_t pflash_be_readfn(void *opaque, hwaddr addr, unsigned size)
-{
- return pflash_read(opaque, addr, size, 1);
-}
-
-static void pflash_be_writefn(void *opaque, hwaddr addr,
- uint64_t value, unsigned size)
-{
- pflash_write(opaque, addr, value, size, 1);
-}
-
-static uint64_t pflash_le_readfn(void *opaque, hwaddr addr, unsigned size)
-{
- return pflash_read(opaque, addr, size, 0);
-}
-
-static void pflash_le_writefn(void *opaque, hwaddr addr,
- uint64_t value, unsigned size)
-{
- pflash_write(opaque, addr, value, size, 0);
-}
-
-static const MemoryRegionOps pflash_cfi02_ops_be = {
- .read = pflash_be_readfn,
- .write = pflash_be_writefn,
- .valid.min_access_size = 1,
- .valid.max_access_size = 4,
- .endianness = DEVICE_NATIVE_ENDIAN,
-};
-
-static const MemoryRegionOps pflash_cfi02_ops_le = {
- .read = pflash_le_readfn,
- .write = pflash_le_writefn,
+static const MemoryRegionOps pflash_cfi02_ops = {
+ .read = pflash_read,
+ .write = pflash_write,
.valid.min_access_size = 1,
.valid.max_access_size = 4,
.endianness = DEVICE_NATIVE_ENDIAN,
chip_len = pfl->sector_len * pfl->nb_blocs;
- memory_region_init_rom_device(&pfl->orig_mem, OBJECT(pfl), pfl->be ?
- &pflash_cfi02_ops_be : &pflash_cfi02_ops_le,
- pfl, pfl->name, chip_len, &local_err);
+ memory_region_init_rom_device(&pfl->orig_mem, OBJECT(pfl),
+ &pflash_cfi02_ops, pfl, pfl->name,
+ chip_len, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;