drm/amdgpu: Use PSP FW API for partition switch

Use PSP firmware interface for switching compute partitions.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <le.ma@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram_reg_init.c b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram_reg_init.c
index a595bb958215e86353ab7ad66b46c35c1fdacd43..16471b81a1f5d54c5f37b1bedbbd38e539e56c19 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram_reg_init.c
+++ b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram_reg_init.c
@@ -518,9 +518,6 @@ static int aqua_vanjaram_switch_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr,
                adev->gfx.funcs->switch_partition_mode(xcp_mgr->adev,
                                                       num_xcc_per_xcp);
 
-       if (adev->nbio.funcs->set_compute_partition_mode)
-               adev->nbio.funcs->set_compute_partition_mode(adev, mode);
-
        /* Init info about new xcps */
        *num_xcps = num_xcc / num_xcc_per_xcp;
        amdgpu_xcp_init(xcp_mgr, *num_xcps, mode);

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index f5b8d3f388ff623eaf9f262050861b42bd7c667c..c1ee54d4c3d3dc198b4983dbc6c9f690cf289cf8 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -623,22 +623,16 @@ static void gfx_v9_4_3_select_me_pipe_q(struct amdgpu_device *adev,
 static int gfx_v9_4_3_switch_compute_partition(struct amdgpu_device *adev,
                                                int num_xccs_per_xcp)
 {
-       int i, num_xcc;
-       u32 tmp = 0;
-
-       num_xcc = NUM_XCC(adev->gfx.xcc_mask);
+       int ret;
 
-       for (i = 0; i < num_xcc; i++) {
-               tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP,
-                                   num_xccs_per_xcp);
-               tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, VIRTUAL_XCC_ID,
-                                   i % num_xccs_per_xcp);
-               WREG32_SOC15(GC, GET_INST(GC, i), regCP_HYP_XCP_CTL, tmp);
-       }
+       ret = psp_spatial_partition(&adev->psp, NUM_XCC(adev->gfx.xcc_mask) /
+                                                       num_xccs_per_xcp);
+       if (ret)
+               return ret;
 
        adev->gfx.num_xcc_per_xcp = num_xccs_per_xcp;
 
-       return 0;
+       return ret;
 }
 
 static int gfx_v9_4_3_ih_to_xcc_inst(struct amdgpu_device *adev, int ih_node)