if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
                intel_ddi_update_pipe_dp(encoder, crtc_state, conn_state);
  
+       /*
+        * During the HDCP encryption session if Type change is requested,
+        * disable the HDCP and reenable it with new TYPE value.
+        */
        if (conn_state->content_protection ==
-           DRM_MODE_CONTENT_PROTECTION_DESIRED)
-               intel_hdcp_enable(to_intel_connector(conn_state->connector));
-       else if (conn_state->content_protection ==
-                DRM_MODE_CONTENT_PROTECTION_UNDESIRED)
-               intel_hdcp_disable(to_intel_connector(conn_state->connector));
+           DRM_MODE_CONTENT_PROTECTION_UNDESIRED ||
+           content_protection_type_changed)
+               intel_hdcp_disable(connector);
+ 
+       /*
+        * Mark the hdcp state as DESIRED after the hdcp disable of type
+        * change procedure.
+        */
+       if (content_protection_type_changed) {
+               mutex_lock(&hdcp->mutex);
+               hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
+               schedule_work(&hdcp->prop_work);
+               mutex_unlock(&hdcp->mutex);
+       }
+ 
+       if (conn_state->content_protection ==
+           DRM_MODE_CONTENT_PROTECTION_DESIRED ||
+           content_protection_type_changed)
+               intel_hdcp_enable(connector, (u8)conn_state->hdcp_content_type);
  }
  
 -static void intel_ddi_set_fia_lane_count(struct intel_encoder *encoder,
 -                                       const struct intel_crtc_state *pipe_config,
 -                                       enum port port)
 +static void
 +intel_ddi_update_prepare(struct intel_atomic_state *state,
 +                       struct intel_encoder *encoder,
 +                       struct intel_crtc *crtc)
  {
 -      struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 -      struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
 -      enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
 -      u32 val = I915_READ(PORT_TX_DFLEXDPMLE1);
 -      bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
 -
 -      val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port);
 -      switch (pipe_config->lane_count) {
 -      case 1:
 -              val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3(tc_port) :
 -              DFLEXDPMLE1_DPMLETC_ML0(tc_port);
 -              break;
 -      case 2:
 -              val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) :
 -              DFLEXDPMLE1_DPMLETC_ML1_0(tc_port);
 -              break;
 -      case 4:
 -              val |= DFLEXDPMLE1_DPMLETC_ML3_0(tc_port);
 -              break;
 -      default:
 -              MISSING_CASE(pipe_config->lane_count);
 -      }
 -      I915_WRITE(PORT_TX_DFLEXDPMLE1, val);
 +      struct intel_crtc_state *crtc_state =
 +              crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL;
 +      int required_lanes = crtc_state ? crtc_state->lane_count : 1;
 +
 +      WARN_ON(crtc && crtc->active);
 +
 +      intel_tc_port_get_link(enc_to_dig_port(&encoder->base), required_lanes);
 +      if (crtc_state && crtc_state->base.active)
 +              intel_update_active_dpll(state, crtc, encoder);
 +}
 +
 +static void
 +intel_ddi_update_complete(struct intel_atomic_state *state,
 +                        struct intel_encoder *encoder,
 +                        struct intel_crtc *crtc)
 +{
 +      intel_tc_port_put_link(enc_to_dig_port(&encoder->base));
  }
  
  static void