ARM: dts: imx6qdl-apalis/-colibri: remove unused pinctrl groups

100/200MHz states for USDHC3 are not required since the SoC
does not support modes faster than DDR52 for the on board eMMC.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
index 8c04f42fdb71717ee0c91a20271b7a06910f3736..05f07ea3e8c8051338dfec9db3977e095ae19431 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
@@ -947,38 +947,4 @@
                        MX6QDL_PAD_SD3_RST__SD3_RESET  0x17059
                >;
        };
-
-       pinctrl_usdhc3_100mhz: usdhc3100mhzgrp {
-               fsl,pins = <
-                       MX6QDL_PAD_SD3_CMD__SD3_CMD    0x170b9
-                       MX6QDL_PAD_SD3_CLK__SD3_CLK    0x100b9
-                       MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
-                       MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
-                       MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
-                       MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
-                       MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9
-                       MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9
-                       MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9
-                       MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9
-                       /* eMMC reset */
-                       MX6QDL_PAD_SD3_RST__SD3_RESET  0x170b9
-               >;
-       };
-
-       pinctrl_usdhc3_200mhz: usdhc3200mhzgrp {
-               fsl,pins = <
-                       MX6QDL_PAD_SD3_CMD__SD3_CMD    0x170f9
-                       MX6QDL_PAD_SD3_CLK__SD3_CLK    0x100f9
-                       MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
-                       MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
-                       MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
-                       MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
-                       MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9
-                       MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9
-                       MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9
-                       MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9
-                       /* eMMC reset */
-                       MX6QDL_PAD_SD3_RST__SD3_RESET  0x170f9
-               >;
-       };
 };

diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi
index 6821ea51105143654ca2bd172917b63190230570..87e15e7cb32b1e7ea3305faf0d233f129d8eb0b0 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi
@@ -692,40 +692,6 @@
                >;
        };
 
-       pinctrl_usdhc3_100mhz: usdhc3100mhzgrp {
-               fsl,pins = <
-                       MX6QDL_PAD_SD3_CMD__SD3_CMD     0x170b9
-                       MX6QDL_PAD_SD3_CLK__SD3_CLK     0x100b9
-                       MX6QDL_PAD_SD3_DAT0__SD3_DATA0  0x170b9
-                       MX6QDL_PAD_SD3_DAT1__SD3_DATA1  0x170b9
-                       MX6QDL_PAD_SD3_DAT2__SD3_DATA2  0x170b9
-                       MX6QDL_PAD_SD3_DAT3__SD3_DATA3  0x170b9
-                       MX6QDL_PAD_SD3_DAT4__SD3_DATA4  0x170b9
-                       MX6QDL_PAD_SD3_DAT5__SD3_DATA5  0x170b9
-                       MX6QDL_PAD_SD3_DAT6__SD3_DATA6  0x170b9
-                       MX6QDL_PAD_SD3_DAT7__SD3_DATA7  0x170b9
-                       /* eMMC reset */
-                       MX6QDL_PAD_SD3_RST__SD3_RESET   0x170b9
-               >;
-       };
-
-       pinctrl_usdhc3_200mhz: usdhc3200mhzgrp {
-               fsl,pins = <
-                       MX6QDL_PAD_SD3_CMD__SD3_CMD     0x170f9
-                       MX6QDL_PAD_SD3_CLK__SD3_CLK     0x100f9
-                       MX6QDL_PAD_SD3_DAT0__SD3_DATA0  0x170f9
-                       MX6QDL_PAD_SD3_DAT1__SD3_DATA1  0x170f9
-                       MX6QDL_PAD_SD3_DAT2__SD3_DATA2  0x170f9
-                       MX6QDL_PAD_SD3_DAT3__SD3_DATA3  0x170f9
-                       MX6QDL_PAD_SD3_DAT4__SD3_DATA4  0x170f9
-                       MX6QDL_PAD_SD3_DAT5__SD3_DATA5  0x170f9
-                       MX6QDL_PAD_SD3_DAT6__SD3_DATA6  0x170f9
-                       MX6QDL_PAD_SD3_DAT7__SD3_DATA7  0x170f9
-                       /* eMMC reset */
-                       MX6QDL_PAD_SD3_RST__SD3_RESET   0x170f9
-               >;
-       };
-
        pinctrl_weim_cs0: weimcs0grp {
                fsl,pins = <
                        /* nEXT_CS0 */