drm/amdgpu: add pre_asic_init callback for SOC15

We need to restore some registers prior to running asic
init to work around a firmware bug.

Acked-by: Nirmoy Das <nirmoy.das@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index a858912eb0942ad42a1d99266dead1b40ada8a2e..1ca79030e95eb8c701067ebb6ef4d6f58b75e5b8 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -1075,6 +1075,20 @@ static int gmc_v9_0_gart_init(struct amdgpu_device *adev)
        return amdgpu_gart_table_vram_alloc(adev);
 }
 
+/**
+ * gmc_v9_0_save_registers - saves regs
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * This saves potential register values that should be
+ * restored upon resume
+ */
+static void gmc_v9_0_save_registers(struct amdgpu_device *adev)
+{
+       if (adev->asic_type == CHIP_RAVEN)
+               adev->gmc.sdpif_register = RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0);
+}
+
 static int gmc_v9_0_sw_init(void *handle)
 {
        int r, vram_width = 0, vram_type = 0, vram_vendor = 0;
@@ -1229,6 +1243,8 @@ static int gmc_v9_0_sw_init(void *handle)
 
        amdgpu_vm_manager_init(adev);
 
+       gmc_v9_0_save_registers(adev);
+
        return 0;
 }
 
@@ -1282,7 +1298,7 @@ static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
  *
  * This restores register values, saved at suspend.
  */
-static void gmc_v9_0_restore_registers(struct amdgpu_device *adev)
+void gmc_v9_0_restore_registers(struct amdgpu_device *adev)
 {
        if (adev->asic_type == CHIP_RAVEN)
                WREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0, adev->gmc.sdpif_register);
@@ -1386,20 +1402,6 @@ static int gmc_v9_0_hw_init(void *handle)
        return r;
 }
 
-/**
- * gmc_v9_0_save_registers - saves regs
- *
- * @adev: amdgpu_device pointer
- *
- * This saves potential register values that should be
- * restored upon resume
- */
-static void gmc_v9_0_save_registers(struct amdgpu_device *adev)
-{
-       if (adev->asic_type == CHIP_RAVEN)
-               adev->gmc.sdpif_register = RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0);
-}
-
 /**
  * gmc_v9_0_gart_disable - gart disable
  *
@@ -1440,8 +1442,6 @@ static int gmc_v9_0_suspend(void *handle)
        if (r)
                return r;
 
-       gmc_v9_0_save_registers(adev);
-
        return 0;
 }
 
@@ -1450,7 +1450,6 @@ static int gmc_v9_0_resume(void *handle)
        int r;
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-       gmc_v9_0_restore_registers(adev);
        r = gmc_v9_0_hw_init(adev);
        if (r)
                return r;

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h
index e0585e8c6c1b74fb690d07c4b16ee8dc5d453a3e..c415c439f6905093b0d35b9785b3a62ef2492523 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h
@@ -26,4 +26,6 @@
 
 extern const struct amd_ip_funcs gmc_v9_0_ip_funcs;
 extern const struct amdgpu_ip_block_version gmc_v9_0_ip_block;
+
+void gmc_v9_0_restore_registers(struct amdgpu_device *adev);
 #endif

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 3c3a7adad02494c719f504eb85c7fbce8796ee6a..2f93c475d6d86c4e57b6964c1cea416d67bc1f74 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -1029,6 +1029,11 @@ static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev)
        return (nak_r + nak_g);
 }
 
+static void soc15_pre_asic_init(struct amdgpu_device *adev)
+{
+       gmc_v9_0_restore_registers(adev);
+}
+
 static const struct amdgpu_asic_funcs soc15_asic_funcs =
 {
        .read_disabled_bios = &soc15_read_disabled_bios,
@@ -1049,6 +1054,7 @@ static const struct amdgpu_asic_funcs soc15_asic_funcs =
        .need_reset_on_init = &soc15_need_reset_on_init,
        .get_pcie_replay_count = &soc15_get_pcie_replay_count,
        .supports_baco = &soc15_supports_baco,
+       .pre_asic_init = &soc15_pre_asic_init,
 };
 
 static const struct amdgpu_asic_funcs vega20_asic_funcs =
@@ -1072,6 +1078,7 @@ static const struct amdgpu_asic_funcs vega20_asic_funcs =
        .need_reset_on_init = &soc15_need_reset_on_init,
        .get_pcie_replay_count = &soc15_get_pcie_replay_count,
        .supports_baco = &soc15_supports_baco,
+       .pre_asic_init = &soc15_pre_asic_init,
 };
 
 static int soc15_common_early_init(void *handle)