drm/amd/display: Add i2c speed arbitration for dc_i2c and hdcp_i2c

[why]
HDCP 1.4 failed on SL8800 SW w/a test driver use.

[how]
Slow down the HW i2c speed when used by HW i2c.
This request: each acquired_i2c_engine setup the i2c speed needed
and sets the I2c engine for HDCP use at release_engine.

This covers SW using HW i2c engine and HDCP using HW i2c engine.
for dmcu using HW i2c engine, needs add similar logic in dmcu fw.

Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Reviewed-by: Chris Park <Chris.Park@amd.com>
Acked-by: Eryk Brol <eryk.brol@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index d893211977ff49da1bed2e76d3381bea7685fabe..d2d2032a40e14b5cecf893e6259a297b400a9bce 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -152,6 +152,7 @@ struct dc_caps {
        uint32_t max_planes;
        uint32_t max_downscale_ratio;
        uint32_t i2c_speed_in_khz;
+       uint32_t i2c_speed_in_khz_hdcp;
        uint32_t dmdata_alloc_size;
        unsigned int max_cursor_size;
        unsigned int max_video_width;

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
index 24adec407972ae5a90ea6211c5ec146a9becb560..3e34afe8c5041eb5ba35387e7bd916b18818d5ae 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
@@ -299,8 +299,12 @@ static bool setup_engine(
        /* we have checked I2c not used by DMCU, set SW use I2C REQ to 1 to indicate SW using it*/
        REG_UPDATE(DC_I2C_ARBITRATION, DC_I2C_SW_USE_I2C_REG_REQ, 1);
 
+       /*set SW requested I2c speed to default, if API calls in it will be override later*/
+       set_speed(dce_i2c_hw, dce_i2c_hw->ctx->dc->caps.i2c_speed_in_khz);
+
        if (dce_i2c_hw->setup_limit != 0)
                i2c_setup_limit = dce_i2c_hw->setup_limit;
+
        /* Program pin select */
        REG_UPDATE_6(DC_I2C_CONTROL,
                     DC_I2C_GO, 0,
@@ -339,8 +343,6 @@ static void release_engine(
 {
        bool safe_to_reset;
 
-       /* Restore original HW engine speed */
-       set_speed(dce_i2c_hw, dce_i2c_hw->default_speed);
 
        /* Reset HW engine */
        {
@@ -360,6 +362,9 @@ static void release_engine(
        /* HW I2c engine - clock gating feature */
        if (!dce_i2c_hw->engine_keep_power_up_count)
                REG_UPDATE_N(SETUP, 1, FN(SETUP, DC_I2C_DDC1_ENABLE), 0);
+
+       /*for HW HDCP Ri polling failure w/a test*/
+       set_speed(dce_i2c_hw, dce_i2c_hw->ctx->dc->caps.i2c_speed_in_khz_hdcp);
        /* Release I2C after reset, so HW or DMCU could use it */
        REG_UPDATE_2(DC_I2C_ARBITRATION, DC_I2C_SW_DONE_USING_I2C_REG, 1,
                DC_I2C_SW_USE_I2C_REG_REQ, 0);

diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
index a28c4ae0f2599062db4c7e74d7245e31ec79ca0d..d741787f75dcb5e1505f7b8988b5656d1e608842 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
@@ -1071,6 +1071,7 @@ static bool dce100_resource_construct(
        pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
        dc->caps.max_downscale_ratio = 200;
        dc->caps.i2c_speed_in_khz = 40;
+       dc->caps.i2c_speed_in_khz = 40;
        dc->caps.max_cursor_size = 128;
        dc->caps.dual_link_dvi = true;
        dc->caps.disable_dp_clk_share = true;

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
index 1d5385072a390440b045cccfdd181e4f971021e3..2bbfa2e176a9fbe4a6d074501aa8723a8b057ee4 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
@@ -1372,7 +1372,8 @@ static bool dce110_resource_construct(
        pool->base.underlay_pipe_index = pool->base.pipe_count;
        pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
        dc->caps.max_downscale_ratio = 150;
-       dc->caps.i2c_speed_in_khz = 100;
+       dc->caps.i2c_speed_in_khz = 40;
+       dc->caps.i2c_speed_in_khz_hdcp = 40;
        dc->caps.max_cursor_size = 128;
        dc->caps.is_apu = true;
        dc->caps.extended_aux_timeout_support = false;

diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
index 0853bc9917c75e6adca187fbde7c843fedb1ad0d..b622b4b1dac3d432118e9b34bc62366c26ff097d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
@@ -1240,6 +1240,7 @@ static bool dce112_resource_construct(
        pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
        dc->caps.max_downscale_ratio = 200;
        dc->caps.i2c_speed_in_khz = 100;
+       dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/
        dc->caps.max_cursor_size = 128;
        dc->caps.dual_link_dvi = true;
        dc->caps.extended_aux_timeout_support = false;

diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
index 8f362e8c17870baebaaf31ca8a516ba53692505d..16fe7344702f4ab3e11ce47d907bd938dea12ead 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
@@ -1080,6 +1080,7 @@ static bool dce120_resource_construct(
 
        dc->caps.max_downscale_ratio = 200;
        dc->caps.i2c_speed_in_khz = 100;
+       dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/
        dc->caps.max_cursor_size = 128;
        dc->caps.dual_link_dvi = true;
        dc->caps.psp_setup_panel_mode = true;

diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
index a19be9de2df7d87a76e14db7792abdae35a82c18..0eae8cd35f9a138a2456f4248fe5200b2a70f05a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
@@ -970,6 +970,7 @@ static bool dce80_construct(
        pool->base.timing_generator_count = res_cap.num_timing_generator;
        dc->caps.max_downscale_ratio = 200;
        dc->caps.i2c_speed_in_khz = 40;
+       dc->caps.i2c_speed_in_khz_hdcp = 40;
        dc->caps.max_cursor_size = 128;
        dc->caps.dual_link_dvi = true;
        dc->caps.extended_aux_timeout_support = false;
@@ -1168,6 +1169,7 @@ static bool dce81_construct(
        pool->base.timing_generator_count = res_cap_81.num_timing_generator;
        dc->caps.max_downscale_ratio = 200;
        dc->caps.i2c_speed_in_khz = 40;
+       dc->caps.i2c_speed_in_khz_hdcp = 40;
        dc->caps.max_cursor_size = 128;
        dc->caps.is_apu = true;
 
@@ -1365,6 +1367,7 @@ static bool dce83_construct(
        pool->base.timing_generator_count = res_cap_83.num_timing_generator;
        dc->caps.max_downscale_ratio = 200;
        dc->caps.i2c_speed_in_khz = 40;
+       dc->caps.i2c_speed_in_khz_hdcp = 40;
        dc->caps.max_cursor_size = 128;
        dc->caps.is_apu = true;
 

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index a78712caf1244f2d1e6f5abf13d0abfb62f3e30a..634171f63a2f494ae0744eaabfce5e5014d97f16 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -1416,6 +1416,7 @@ static bool dcn10_resource_construct(
        dc->caps.max_video_width = 3840;
        dc->caps.max_downscale_ratio = 200;
        dc->caps.i2c_speed_in_khz = 100;
+       dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/
        dc->caps.max_cursor_size = 256;
        dc->caps.max_slave_planes = 1;
        dc->caps.is_apu = true;

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index d50a9c37063729560bcec2cc51aed67ee4ccd215..1b3b6ba20d18db7071822946481eaa486d8182f8 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -3801,6 +3801,7 @@ static bool dcn20_resource_construct(
 
        dc->caps.max_downscale_ratio = 200;
        dc->caps.i2c_speed_in_khz = 100;
+       dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/
        dc->caps.max_cursor_size = 256;
        dc->caps.dmdata_alloc_size = 2048;
 

diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index e73785e74cba8bc68e00ffc546671d1dd6bcaec2..0ab718fd43b1abe1b5220b1012879adc9218788e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -1808,6 +1808,7 @@ static bool dcn21_resource_construct(
 
        dc->caps.max_downscale_ratio = 200;
        dc->caps.i2c_speed_in_khz = 100;
+       dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by default*/
        dc->caps.max_cursor_size = 256;
        dc->caps.dmdata_alloc_size = 2048;
 

diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index 24fb39a11e5d5c261a7b4e5dc8daf991fd399191..783a1d7ae7d3dae1909f93272ebebba9a57c2b34 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -2593,6 +2593,7 @@ static bool dcn30_resource_construct(
        pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
        dc->caps.max_downscale_ratio = 600;
        dc->caps.i2c_speed_in_khz = 100;
+       dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/
        dc->caps.max_cursor_size = 256;
        dc->caps.dmdata_alloc_size = 2048;