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arm64: dts: rockchip: enable sfc controller on Quartz64 Model A
author
Peter Geis
<pgwipeout@gmail.com>
Wed, 11 May 2022 15:01:17 +0000
(11:01 -0400)
committer
Heiko Stuebner
<heiko@sntech.de>
Tue, 7 Jun 2022 08:31:20 +0000
(10:31 +0200)
Add the sfc controller binding for the Quartz64 Model A. This is not
populated by default, so leave it disabled.
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Link:
https://lore.kernel.org/r/20220511150117.113070-7-pgwipeout@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
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diff --git
a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
index a3f9b949643c7f2e549c994327c2282a4845557d..a02ac75916f40fda6138ee5c713f65227541cdf6 100644
(file)
--- a/
arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
+++ b/
arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
@@
-617,6
+617,22
@@
status = "okay";
};
+&sfc {
+ pinctrl-0 = <&fspi_pins>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <24000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <1>;
+ };
+};
+
/* spdif is exposed on con40 pin 18 */
&spdif {
status = "okay";