drm/i915/guc: Update guc shim control programming on newer platforms

Starting from xehpsdv, bit 0 of the GuC shim control register has
been repurposed, while bit 2 is now reserved, so we need to avoid
setting those for their old meaning on newer platforms.

Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Cc: Stuart Summers <stuart.summers@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220120222436.3449778-1-daniele.ceraolospurio@intel.com

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
index f773e7f35bc1a8046ef1358bee179fa4820ddf2b..40f7d4779c9ec924f2e734788efb209f64ed7db2 100644 (file)
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
@@ -15,13 +15,15 @@
 
 static void guc_prepare_xfer(struct intel_uncore *uncore)
 {
-       u32 shim_flags = GUC_DISABLE_SRAM_INIT_TO_ZEROES |
-                        GUC_ENABLE_READ_CACHE_LOGIC |
-                        GUC_ENABLE_MIA_CACHING |
+       u32 shim_flags = GUC_ENABLE_READ_CACHE_LOGIC |
                         GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA |
                         GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA |
                         GUC_ENABLE_MIA_CLOCK_GATING;
 
+       if (GRAPHICS_VER_FULL(uncore->i915) < IP_VER(12, 50))
+               shim_flags |= GUC_DISABLE_SRAM_INIT_TO_ZEROES |
+                             GUC_ENABLE_MIA_CACHING;
+
        /* Must program this register before loading the ucode with DMA */
        intel_uncore_write(uncore, GUC_SHIM_CONTROL, shim_flags);