clk: renesas: r9a07g044: Update multiplier and divider values for PLL2/3

As per the HW manual (Rev.1.00 Sep, 2021) PLL2 and PLL3 should be
1600 MHz, but with current multiplier and divider values this resulted
to 1596 MHz.

This patch updates the multiplier and divider values for PLL2 and PLL3
so that we get the exact (1600 MHz) values.

Fixes: 17f0ff3d49ff1 ("clk: renesas: Add support for R9A07G044 SoC")
Suggested-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211223093223.4725-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index 79042bf46fe859d37e1cf4e65a99490bb10cc1bb..46359afef0d43d50b027ee100508de0d0c6a949d 100644 (file)
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -88,8 +88,8 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
        DEF_FIXED(".osc", R9A07G044_OSCCLK, CLK_EXTAL, 1, 1),
        DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000),
        DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),
-       DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 133, 2),
-       DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 133, 2),
+       DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3),
+       DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3),
        DEF_FIXED(".pll3_400", CLK_PLL3_400, CLK_PLL3, 1, 4),
        DEF_FIXED(".pll3_533", CLK_PLL3_533, CLK_PLL3, 1, 3),