drm/i915: Extract ilk_update_pll_dividers()

Make the PCH dpll code match the gmch code by splitting
the FP register handling out from ilk_compute_dpll().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210715093530.31711-4-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 939a1a6e5c1e1cbcfb2459822609c600f57a7a88..e2ca6f2108d17a42c87e48376b34279f6fda41d5 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -948,12 +948,12 @@ static bool ilk_needs_fb_cb_tune(struct dpll *dpll, int factor)
 }
 
 
-static void ilk_compute_dpll(struct intel_crtc *crtc,
-                            struct intel_crtc_state *crtc_state,
-                            struct dpll *reduced_clock)
+static void ilk_update_pll_dividers(struct intel_crtc *crtc,
+                                   struct intel_crtc_state *crtc_state,
+                                   struct dpll *reduced_clock)
 {
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-       u32 dpll, fp, fp2;
+       u32 fp, fp2 = 0;
        int factor;
 
        /* Enable autotuning of the PLL clock (if permissible) */
@@ -978,10 +978,21 @@ static void ilk_compute_dpll(struct intel_crtc *crtc,
 
                if (reduced_clock->m < factor * reduced_clock->n)
                        fp2 |= FP_CB_TUNE;
-       } else {
-               fp2 = fp;
        }
 
+       crtc_state->dpll_hw_state.fp0 = fp;
+       crtc_state->dpll_hw_state.fp1 = reduced_clock ? fp2 : fp;
+}
+
+static void ilk_compute_dpll(struct intel_crtc *crtc,
+                            struct intel_crtc_state *crtc_state,
+                            struct dpll *reduced_clock)
+{
+       struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+       u32 dpll;
+
+       ilk_update_pll_dividers(crtc, crtc_state, reduced_clock);
+
        dpll = 0;
 
        if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
@@ -1046,8 +1057,6 @@ static void ilk_compute_dpll(struct intel_crtc *crtc,
        dpll |= DPLL_VCO_ENABLE;
 
        crtc_state->dpll_hw_state.dpll = dpll;
-       crtc_state->dpll_hw_state.fp0 = fp;
-       crtc_state->dpll_hw_state.fp1 = fp2;
 }
 
 static int ilk_crtc_compute_clock(struct intel_crtc *crtc,