drm/amdgpu: add more fields into device info, caches sizes, etc.

AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD: important for conformance on gfx11
Other fields are exposed from IP discovery.
enabled_rb_pipes_mask_hi is added for future chips, currently 0.

Mesa MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21403

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index bfb7ed254ee4c2b47927fde12fb42d8e9f91e01f..641bdcdab10ea4ff58c9c7e10b39c7a686630a79 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -107,9 +107,12 @@
  * - 3.50.0 - Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock
  *            Update AMDGPU_INFO_SENSOR IOCTL for PEAK_PSTATE engine and memory clock
  *   3.51.0 - Return the PCIe gen and lanes from the INFO ioctl
+ *   3.52.0 - Add AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD, add device_info fields:
+ *            tcp_cache_size, num_sqc_per_wgp, sqc_data_cache_size, sqc_inst_cache_size,
+ *            gl1c_cache_size, gl2c_cache_size, mall_size, enabled_rb_pipes_mask_hi
  */
 #define KMS_DRIVER_MAJOR       3
-#define KMS_DRIVER_MINOR       51
+#define KMS_DRIVER_MINOR       52
 #define KMS_DRIVER_PATCHLEVEL  0
 
 unsigned int amdgpu_vram_limit = UINT_MAX;

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 86ec9d0d12c8eebf881f2680cdbb93c48207905c..de9e7a00bb1504a19f94a626e82fe784bdda73cd 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -178,6 +178,8 @@ struct amdgpu_gfx_config {
        uint32_t num_sc_per_sh;
        uint32_t num_packer_per_sc;
        uint32_t pa_sc_tile_steering_override;
+       /* Whether texture coordinate truncation is conformant. */
+       bool ta_cntl2_truncate_coord_mode;
        uint64_t tcc_disabled_mask;
        uint32_t gc_num_tcp_per_sa;
        uint32_t gc_num_sdp_interface;

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index ca945055e683654a47385c31746873744faea295..0efb38539d70cc6dff5da3e222cf3b4a2ac3a25f 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -808,6 +808,8 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
                        dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
                if (amdgpu_is_tmz(adev))
                        dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ;
+               if (adev->gfx.config.ta_cntl2_truncate_coord_mode)
+                       dev_info->ids_flags |= AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD;
 
                vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
                vm_size -= AMDGPU_VA_RESERVED_SIZE;
@@ -865,6 +867,15 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
                        adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 ? 4 :
                        adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 ? 2 : 1;
 
+               dev_info->tcp_cache_size = adev->gfx.config.gc_tcp_l1_size;
+               dev_info->num_sqc_per_wgp = adev->gfx.config.gc_num_sqc_per_wgp;
+               dev_info->sqc_data_cache_size = adev->gfx.config.gc_l1_data_cache_size_per_sqc;
+               dev_info->sqc_inst_cache_size = adev->gfx.config.gc_l1_instruction_cache_size_per_sqc;
+               dev_info->gl1c_cache_size = adev->gfx.config.gc_gl1c_size_per_instance *
+                                           adev->gfx.config.gc_gl1c_per_sa;
+               dev_info->gl2c_cache_size = adev->gfx.config.gc_gl2c_per_gpu;
+               dev_info->mall_size = adev->gmc.mall_size;
+
                ret = copy_to_user(out, dev_info,
                                   min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0;
                kfree(dev_info);

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 417ab8d1eacea7a5c8e84bbaeece3b9447ef4327..3bf697a80cf2fc30a4dcc49e154ee87b5ffe4370 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -1659,6 +1659,11 @@ static void gfx_v11_0_constants_init(struct amdgpu_device *adev)
        gfx_v11_0_get_tcc_info(adev);
        adev->gfx.config.pa_sc_tile_steering_override = 0;
 
+       /* Set whether texture coordinate truncation is conformant. */
+       tmp = RREG32_SOC15(GC, 0, regTA_CNTL2);
+       adev->gfx.config.ta_cntl2_truncate_coord_mode =
+               REG_GET_FIELD(tmp, TA_CNTL2, TRUNCATE_COORD_MODE);
+
        /* XXX SH_MEM regs */
        /* where to put LDS, scratch, GPUVM in FSA64 space */
        mutex_lock(&adev->srbm_mutex);

diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 973af6d066260a1dbf8252746494b90236903bb4..b6eb90df5d052d997f09c55b276e62b198ee36a8 100644 (file)
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -715,6 +715,7 @@ struct drm_amdgpu_cs_chunk_data {
 #define AMDGPU_IDS_FLAGS_FUSION         0x1
 #define AMDGPU_IDS_FLAGS_PREEMPTION     0x2
 #define AMDGPU_IDS_FLAGS_TMZ            0x4
+#define AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD 0x8
 
 /* indicate if acceleration can be working */
 #define AMDGPU_INFO_ACCEL_WORKING              0x00
@@ -1115,6 +1116,16 @@ struct drm_amdgpu_info_device {
        __u64 tcc_disabled_mask;
        __u64 min_engine_clock;
        __u64 min_memory_clock;
+       /* The following fields are only set on gfx11+, older chips set 0. */
+       __u32 tcp_cache_size;       /* AKA GL0, VMEM cache */
+       __u32 num_sqc_per_wgp;
+       __u32 sqc_data_cache_size;  /* AKA SMEM cache */
+       __u32 sqc_inst_cache_size;
+       __u32 gl1c_cache_size;
+       __u32 gl2c_cache_size;
+       __u64 mall_size;            /* AKA infinity cache */
+       /* high 32 bits of the rb pipes mask */
+       __u32 enabled_rb_pipes_mask_hi;
 };
 
 struct drm_amdgpu_info_hw_ip {