pinctrl: renesas: r8a779a0: Add TMU pins, groups and functions

This patch adds TMU TCLK1-4 pins, groups and functions to the R8A779A0
(V3U) SoC.

Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Link: https://lore.kernel.org/r/20210112165929.31002-12-uli+renesas@fpond.eu
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/pinctrl/renesas/pfc-r8a779a0.c b/drivers/pinctrl/renesas/pfc-r8a779a0.c
index a22604ae87e837f1a627e3dd4d5840c49bbcc8c0..a85e2c750e41013704a829f42b696567fec7d46d 100644 (file)
--- a/drivers/pinctrl/renesas/pfc-r8a779a0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779a0.c
@@ -2535,6 +2535,53 @@ static const unsigned int scif_clk_mux[] = {
        SCIF_CLK_MARK,
 };
 
+/* - TMU -------------------------------------------------------------------- */
+static const unsigned int tmu_tclk1_a_pins[] = {
+       /* TCLK1 */
+       RCAR_GP_PIN(2, 23),
+};
+static const unsigned int tmu_tclk1_a_mux[] = {
+       TCLK1_A_MARK,
+};
+static const unsigned int tmu_tclk1_b_pins[] = {
+       /* TCLK1 */
+       RCAR_GP_PIN(1, 23),
+};
+static const unsigned int tmu_tclk1_b_mux[] = {
+       TCLK1_B_MARK,
+};
+
+static const unsigned int tmu_tclk2_a_pins[] = {
+       /* TCLK2 */
+       RCAR_GP_PIN(2, 24),
+};
+static const unsigned int tmu_tclk2_a_mux[] = {
+       TCLK2_A_MARK,
+};
+static const unsigned int tmu_tclk2_b_pins[] = {
+       /* TCLK2 */
+       RCAR_GP_PIN(2, 10),
+};
+static const unsigned int tmu_tclk2_b_mux[] = {
+       TCLK2_B_MARK,
+};
+
+static const unsigned int tmu_tclk3_pins[] = {
+       /* TCLK3 */
+       RCAR_GP_PIN(2, 11),
+};
+static const unsigned int tmu_tclk3_mux[] = {
+       TCLK3_MARK,
+};
+
+static const unsigned int tmu_tclk4_pins[] = {
+       /* TCLK4 */
+       RCAR_GP_PIN(2, 12),
+};
+static const unsigned int tmu_tclk4_mux[] = {
+       TCLK4_MARK,
+};
+
 static const struct sh_pfc_pin_group pinmux_groups[] = {
        SH_PFC_PIN_GROUP(avb0_link),
        SH_PFC_PIN_GROUP(avb0_magic),
@@ -2711,6 +2758,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
        SH_PFC_PIN_GROUP(scif4_clk),
        SH_PFC_PIN_GROUP(scif4_ctrl),
        SH_PFC_PIN_GROUP(scif_clk),
+
+       SH_PFC_PIN_GROUP(tmu_tclk1_a),
+       SH_PFC_PIN_GROUP(tmu_tclk1_b),
+       SH_PFC_PIN_GROUP(tmu_tclk2_a),
+       SH_PFC_PIN_GROUP(tmu_tclk2_b),
+       SH_PFC_PIN_GROUP(tmu_tclk3),
+       SH_PFC_PIN_GROUP(tmu_tclk4),
 };
 
 static const char * const avb0_groups[] = {
@@ -3014,6 +3068,15 @@ static const char * const scif_clk_groups[] = {
        "scif_clk",
 };
 
+static const char * const tmu_groups[] = {
+       "tmu_tclk1_a",
+       "tmu_tclk1_b",
+       "tmu_tclk2_a",
+       "tmu_tclk2_b",
+       "tmu_tclk3",
+       "tmu_tclk4",
+};
+
 static const struct sh_pfc_function pinmux_functions[] = {
        SH_PFC_FUNCTION(avb0),
        SH_PFC_FUNCTION(avb1),
@@ -3072,6 +3135,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
        SH_PFC_FUNCTION(scif3),
        SH_PFC_FUNCTION(scif4),
        SH_PFC_FUNCTION(scif_clk),
+
+       SH_PFC_FUNCTION(tmu),
 };
 
 static const struct pinmux_cfg_reg pinmux_config_regs[] = {