arm64: dts: rockchip: Assign PLL_PPLL clock rate to 1.1 GHz on rk3588s

The clock rate for PLL_PPLL has been wrongly initialized to 100 MHz
instead of 1.1 GHz. Fix it.

Fixes: c9211fa2602b ("arm64: dts: rockchip: Add base DT for rk3588 SoC")
Reported-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Link: https://lore.kernel.org/r/20230402095054.384739-3-cristian.ciocaltea@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
index 37d03330a37e7b22567ee4e7313080dab69e703c..5e27905b9d6ab799f14573b19b8ca19908919980 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -416,7 +416,7 @@
                        <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>,
                        <&cru CLK_GPU>;
                assigned-clock-rates =
-                       <100000000>, <786432000>,
+                       <1100000000>, <786432000>,
                        <850000000>, <1188000000>,
                        <702000000>,
                        <400000000>, <500000000>,