clk: ingenic: Add MDMA and BDMA clocks

The Ingenic JZ4760 and JZ4770 both have an extra DMA core named BDMA
dedicated to the NAND and BCH controller, but which can also do
memory-to-memory transfers. The JZ4760 additionally has a DMA core named
MDMA dedicated to memory-to-memory transfers. The programming manual for
the JZ4770 does have a bit for a MDMA clock, but does not seem to have
the hardware wired in.

Add the BDMA and MDMA clocks to the JZ4760 CGU code, and the BDMA clock
to the JZ4770 code, so that the BDMA and MDMA controllers can be used.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20211220193319.114974-3-paul@crapouillou.net
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/ingenic/jz4760-cgu.c b/drivers/clk/ingenic/jz4760-cgu.c
index 080d492ac95c7c7bf45a95535c496cfd69904765..8fdd383560fbc770e5932c1ddd26bf4eecfd0359 100644 (file)
--- a/drivers/clk/ingenic/jz4760-cgu.c
+++ b/drivers/clk/ingenic/jz4760-cgu.c
@@ -313,6 +313,16 @@ static const struct ingenic_cgu_clk_info jz4760_cgu_clocks[] = {
                .parents = { JZ4760_CLK_H2CLK, },
                .gate = { CGU_REG_CLKGR0, 21 },
        },
+       [JZ4760_CLK_MDMA] = {
+               "mdma", CGU_CLK_GATE,
+               .parents = { JZ4760_CLK_HCLK, },
+               .gate = { CGU_REG_CLKGR0, 25 },
+       },
+       [JZ4760_CLK_BDMA] = {
+               "bdma", CGU_CLK_GATE,
+               .parents = { JZ4760_CLK_HCLK, },
+               .gate = { CGU_REG_CLKGR1, 0 },
+       },
        [JZ4760_CLK_I2C0] = {
                "i2c0", CGU_CLK_GATE,
                .parents = { JZ4760_CLK_EXT, },

diff --git a/drivers/clk/ingenic/jz4770-cgu.c b/drivers/clk/ingenic/jz4770-cgu.c
index 8c6c1208f46279d6919579a56774c17653aae35d..7ef91257630e7406175303accdbed2a025c1cb97 100644 (file)
--- a/drivers/clk/ingenic/jz4770-cgu.c
+++ b/drivers/clk/ingenic/jz4770-cgu.c
@@ -329,6 +329,11 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = {
                .parents = { JZ4770_CLK_H2CLK, },
                .gate = { CGU_REG_CLKGR0, 21 },
        },
+       [JZ4770_CLK_BDMA] = {
+               "bdma", CGU_CLK_GATE,
+               .parents = { JZ4770_CLK_H2CLK, },
+               .gate = { CGU_REG_CLKGR1, 0 },
+       },
        [JZ4770_CLK_I2C0] = {
                "i2c0", CGU_CLK_GATE,
                .parents = { JZ4770_CLK_EXT, },