drm/xe/xe2hpg: Determine flat ccs offset for vram

on Xe2 dgfx platform determine the offset using Flat CCS size
bitfield of XE2_FLAT_CCS_BASE_RANGE_[UPPER/LOWER] mcr registers.

v2: function argument tile_size changed from pass by reference to pass
by value

Bspec: 68023
Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
Signed-off-by: Akshata Jahagirdar <akshata.jahagirdar@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240408170545.3769566-7-balasubramani.vivekanandan@intel.com

diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 6617c86a096b6b30751f8768a4457ff05e03e308..d404f211bc367702266da099e7ebae7670df41c6 100644 (file)
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -69,6 +69,7 @@
 
 #define XEHP_TILE_ADDR_RANGE(_idx)             XE_REG_MCR(0x4900 + (_idx) * 4)
 #define XEHP_FLAT_CCS_BASE_ADDR                        XE_REG_MCR(0x4910)
+#define XEHP_FLAT_CCS_PTR                      REG_GENMASK(31, 8)
 
 #define WM_CHICKEN3                            XE_REG_MCR(0x5588, XE_REG_OPTION_MASKED)
 #define   HIZ_PLANE_COMPRESSION_DIS            REG_BIT(10)
@@ -142,6 +143,10 @@
 
 #define XE2_FLAT_CCS_BASE_RANGE_LOWER          XE_REG_MCR(0x8800)
 #define   XE2_FLAT_CCS_ENABLE                  REG_BIT(0)
+#define XE2_FLAT_CCS_BASE_LOWER_ADDR_MASK      REG_GENMASK(31, 6)
+
+#define XE2_FLAT_CCS_BASE_RANGE_UPPER          XE_REG_MCR(0x8804)
+#define XE2_FLAT_CCS_BASE_UPPER_ADDR_MASK      REG_GENMASK(7, 0)
 
 #define GSCPSMI_BASE                           XE_REG(0x880c)
 

diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
index 5d13fc7cb9d29b4ba431681ddcc4c2717ff98bb0..d66da1a9f165365b26a0c0c5bce61e871da71f29 100644 (file)
--- a/drivers/gpu/drm/xe/xe_mmio.c
+++ b/drivers/gpu/drm/xe/xe_mmio.c
@@ -163,6 +163,42 @@ static int xe_determine_lmem_bar_size(struct xe_device *xe)
        return 0;
 }
 
+static inline u64 get_flat_ccs_offset(struct xe_gt *gt, u64 tile_size)
+{
+       struct xe_device *xe = gt_to_xe(gt);
+       u64 offset;
+       u32 reg;
+
+       if (GRAPHICS_VER(xe) >= 20) {
+               u64 ccs_size = tile_size / 512;
+               u64 offset_hi, offset_lo;
+               u32 nodes, num_enabled;
+
+               reg = xe_mmio_read32(gt, MIRROR_FUSE3);
+               nodes = REG_FIELD_GET(XE2_NODE_ENABLE_MASK, reg);
+               num_enabled = hweight32(nodes); /* Number of enabled l3 nodes */
+
+               reg = xe_gt_mcr_unicast_read_any(gt, XE2_FLAT_CCS_BASE_RANGE_LOWER);
+               offset_lo = REG_FIELD_GET(XE2_FLAT_CCS_BASE_LOWER_ADDR_MASK, reg);
+
+               reg = xe_gt_mcr_unicast_read_any(gt, XE2_FLAT_CCS_BASE_RANGE_UPPER);
+               offset_hi = REG_FIELD_GET(XE2_FLAT_CCS_BASE_UPPER_ADDR_MASK, reg);
+
+               offset = offset_hi << 32; /* HW view bits 39:32 */
+               offset |= offset_lo << 6; /* HW view bits 31:6 */
+               offset *= num_enabled; /* convert to SW view */
+
+               /* We don't expect any holes */
+               xe_assert_msg(xe, offset == (xe_mmio_read64_2x32(gt, GSMBASE) - ccs_size),
+                             "Hole between CCS and GSM.\n");
+       } else {
+               reg = xe_gt_mcr_unicast_read_any(gt, XEHP_FLAT_CCS_BASE_ADDR);
+               offset = (u64)REG_FIELD_GET(XEHP_FLAT_CCS_PTR, reg) * SZ_64K;
+       }
+
+       return offset;
+}
+
 /**
  * xe_mmio_tile_vram_size() - Collect vram size and offset information
  * @tile: tile to get info for
@@ -207,8 +243,7 @@ static int xe_mmio_tile_vram_size(struct xe_tile *tile, u64 *vram_size,
 
        /* minus device usage */
        if (xe->info.has_flat_ccs) {
-               reg = xe_gt_mcr_unicast_read_any(gt, XEHP_FLAT_CCS_BASE_ADDR);
-               offset = (u64)REG_FIELD_GET(GENMASK(31, 8), reg) * SZ_64K;
+               offset = get_flat_ccs_offset(gt, *tile_size);
        } else {
                offset = xe_mmio_read64_2x32(gt, GSMBASE);
        }