drm/msm/dpu: drop enum msm_display_caps

After the commit c46f0d69039c ("drm/msm: remove unused hotplug and edid
macros from msm_drv.h") the msm_display_caps enum contains two bits
describing whether the encoder should work in video or command mode.
Drop the enum and replace capabilities field in struct msm_display_info
with boolean is_cmd_mode field.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/485454/
Link: https://lore.kernel.org/r/20220507115942.1705872-2-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index d14415b58e5b881aaa4c8ee47b820cc8c4ee92eb..5ccaf35929a0e628d6711dc235dc77044a1c5408 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -634,7 +634,7 @@ static void _dpu_encoder_update_vsync_source(struct dpu_encoder_virt *dpu_enc,
        }
 
        if (hw_mdptop->ops.setup_vsync_source &&
-                       disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) {
+                       disp_info->is_cmd_mode) {
                for (i = 0; i < dpu_enc->num_phys_encs; i++)
                        vsync_cfg.ppnumber[i] = dpu_enc->hw_pp[i]->idx;
 
@@ -718,8 +718,7 @@ static int dpu_encoder_resource_control(struct drm_encoder *drm_enc,
        }
        dpu_enc = to_dpu_encoder_virt(drm_enc);
        priv = drm_enc->dev->dev_private;
-       is_vid_mode = dpu_enc->disp_info.capabilities &
-                                               MSM_DISPLAY_CAP_VID_MODE;
+       is_vid_mode = !dpu_enc->disp_info.is_cmd_mode;
 
        /*
         * when idle_pc is not supported, process only KICKOFF, STOP and MODESET
@@ -1603,7 +1602,7 @@ void dpu_encoder_trigger_kickoff_pending(struct drm_encoder *drm_enc)
 
                /* update only for command mode primary ctl */
                if ((phys == dpu_enc->cur_master) &&
-                  (disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE)
+                   disp_info->is_cmd_mode
                    && ctl->ops.trigger_pending)
                        ctl->ops.trigger_pending(ctl);
        }
@@ -2139,20 +2138,19 @@ static int dpu_encoder_virt_add_phys_encs(
                return -EINVAL;
        }
 
-       if (disp_info->capabilities & MSM_DISPLAY_CAP_VID_MODE) {
-               enc = dpu_encoder_phys_vid_init(params);
+
+       if (disp_info->intf_type == DRM_MODE_ENCODER_VIRTUAL) {
+               enc = dpu_encoder_phys_wb_init(params);
 
                if (IS_ERR(enc)) {
-                       DPU_ERROR_ENC(dpu_enc, "failed to init vid enc: %ld\n",
+                       DPU_ERROR_ENC(dpu_enc, "failed to init wb enc: %ld\n",
                                PTR_ERR(enc));
                        return PTR_ERR(enc);
                }
 
                dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc;
                ++dpu_enc->num_phys_encs;
-       }
-
-       if (disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) {
+       } else if (disp_info->is_cmd_mode) {
                enc = dpu_encoder_phys_cmd_init(params);
 
                if (IS_ERR(enc)) {
@@ -2163,14 +2161,12 @@ static int dpu_encoder_virt_add_phys_encs(
 
                dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc;
                ++dpu_enc->num_phys_encs;
-       }
-
-       if (disp_info->intf_type == DRM_MODE_ENCODER_VIRTUAL) {
-               enc = dpu_encoder_phys_wb_init(params);
+       } else {
+               enc = dpu_encoder_phys_vid_init(params);
 
                if (IS_ERR(enc)) {
-                       DPU_ERROR_ENC(dpu_enc, "failed to init wb enc: %ld\n",
-                                       PTR_ERR(enc));
+                       DPU_ERROR_ENC(dpu_enc, "failed to init vid enc: %ld\n",
+                               PTR_ERR(enc));
                        return PTR_ERR(enc);
                }
 
@@ -2230,8 +2226,7 @@ static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc,
 
        DPU_DEBUG("dsi_info->num_of_h_tiles %d\n", disp_info->num_of_h_tiles);
 
-       if ((disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) ||
-           (disp_info->capabilities & MSM_DISPLAY_CAP_VID_MODE))
+       if (disp_info->intf_type != DRM_MODE_ENCODER_VIRTUAL)
                dpu_enc->idle_pc_supported =
                                dpu_kms->catalog->caps->has_idle_pc;
 

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
index 781d41c91994c09da1c06204c26d487aacf31bd2..861870ac8ae708c2ee53f6300a95b26786f13d05 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
@@ -21,19 +21,19 @@
 /**
  * struct msm_display_info - defines display properties
  * @intf_type:          DRM_MODE_ENCODER_ type
- * @capabilities:       Bitmask of display flags
  * @num_of_h_tiles:     Number of horizontal tiles in case of split interface
  * @h_tile_instance:    Controller instance used per tile. Number of elements is
  *                      based on num_of_h_tiles
+ * @is_cmd_mode                Boolean to indicate if the CMD mode is requested
  * @is_te_using_watchdog_timer:  Boolean to indicate watchdog TE is
  *                              used instead of panel TE in cmd mode panels
  * @dsc:               DSC configuration data for DSC-enabled displays
  */
 struct msm_display_info {
        int intf_type;
-       uint32_t capabilities;
        uint32_t num_of_h_tiles;
        uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY];
+       bool is_cmd_mode;
        bool is_te_using_watchdog_timer;
        struct msm_display_dsc_config *dsc;
 };

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 1b3781f276d1607d5becd6eaf2b954a2963e6f2e..a2d71f0c96af22489b97e4ff3172c1327ee9589e 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -582,9 +582,7 @@ static int _dpu_kms_initialize_dsi(struct drm_device *dev,
                }
 
                info.h_tile_instance[info.num_of_h_tiles++] = i;
-               info.capabilities = msm_dsi_is_cmd_mode(priv->dsi[i]) ?
-                       MSM_DISPLAY_CAP_CMD_MODE :
-                       MSM_DISPLAY_CAP_VID_MODE;
+               info.is_cmd_mode = msm_dsi_is_cmd_mode(priv->dsi[i]);
 
                info.dsc = msm_dsi_get_dsc_config(priv->dsi[i]);
 
@@ -637,7 +635,6 @@ static int _dpu_kms_initialize_displayport(struct drm_device *dev,
 
                info.num_of_h_tiles = 1;
                info.h_tile_instance[0] = i;
-               info.capabilities = MSM_DISPLAY_CAP_VID_MODE;
                info.intf_type = encoder->encoder_type;
                rc = dpu_encoder_setup(dev, encoder, &info);
                if (rc) {

diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index 099a67d10c3a76ae3e0d13adb1fd6fd93f942d71..ae49e56ac0268dedce57d529e2910628953ad644 100644 (file)
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -61,16 +61,6 @@ enum msm_dp_controller {
 #define MSM_GPU_MAX_RINGS 4
 #define MAX_H_TILES_PER_DISPLAY 2
 
-/**
- * enum msm_display_caps - features/capabilities supported by displays
- * @MSM_DISPLAY_CAP_VID_MODE:           Video or "active" mode supported
- * @MSM_DISPLAY_CAP_CMD_MODE:           Command mode supported
- */
-enum msm_display_caps {
-       MSM_DISPLAY_CAP_VID_MODE        = BIT(0),
-       MSM_DISPLAY_CAP_CMD_MODE        = BIT(1),
-};
-
 /**
  * enum msm_event_wait - type of HW events to wait for
  * @MSM_ENC_COMMIT_DONE - wait for the driver to flush the registers to HW