dt-bindings: clock: exynosautov9: correct clock numbering of peric0/c1
authorChanho Park <chanho61.park@samsung.com>
Wed, 27 Jul 2022 02:13:55 +0000 (11:13 +0900)
committerKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Tue, 23 Aug 2022 06:03:49 +0000 (09:03 +0300)
There are duplicated definitions of peric0 and peric1 cmu blocks. Thus,
they should be defined correctly as numerical order.

Fixes: 680e1c8370a2 ("dt-bindings: clock: add clock binding definitions for Exynos Auto v9")
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220727021357.152421-2-chanho61.park@samsung.com
include/dt-bindings/clock/samsung,exynosautov9.h

index ea9f91b4eb1a3586580f22ec074fd1fab045a1a4..a7db6516593fefdadf999ced4dc880793a5a2a53 100644 (file)
 #define CLK_GOUT_PERIC0_IPCLK_8                28
 #define CLK_GOUT_PERIC0_IPCLK_9                29
 #define CLK_GOUT_PERIC0_IPCLK_10       30
-#define CLK_GOUT_PERIC0_IPCLK_11       30
-#define CLK_GOUT_PERIC0_PCLK_0         31
-#define CLK_GOUT_PERIC0_PCLK_1         32
-#define CLK_GOUT_PERIC0_PCLK_2         33
-#define CLK_GOUT_PERIC0_PCLK_3         34
-#define CLK_GOUT_PERIC0_PCLK_4         35
-#define CLK_GOUT_PERIC0_PCLK_5         36
-#define CLK_GOUT_PERIC0_PCLK_6         37
-#define CLK_GOUT_PERIC0_PCLK_7         38
-#define CLK_GOUT_PERIC0_PCLK_8         39
-#define CLK_GOUT_PERIC0_PCLK_9         40
-#define CLK_GOUT_PERIC0_PCLK_10                41
-#define CLK_GOUT_PERIC0_PCLK_11                42
+#define CLK_GOUT_PERIC0_IPCLK_11       31
+#define CLK_GOUT_PERIC0_PCLK_0         32
+#define CLK_GOUT_PERIC0_PCLK_1         33
+#define CLK_GOUT_PERIC0_PCLK_2         34
+#define CLK_GOUT_PERIC0_PCLK_3         35
+#define CLK_GOUT_PERIC0_PCLK_4         36
+#define CLK_GOUT_PERIC0_PCLK_5         37
+#define CLK_GOUT_PERIC0_PCLK_6         38
+#define CLK_GOUT_PERIC0_PCLK_7         39
+#define CLK_GOUT_PERIC0_PCLK_8         40
+#define CLK_GOUT_PERIC0_PCLK_9         41
+#define CLK_GOUT_PERIC0_PCLK_10                42
+#define CLK_GOUT_PERIC0_PCLK_11                43
 
-#define PERIC0_NR_CLK                  43
+#define PERIC0_NR_CLK                  44
 
 /* CMU_PERIC1 */
 #define CLK_MOUT_PERIC1_BUS_USER       1
 #define CLK_GOUT_PERIC1_IPCLK_8                28
 #define CLK_GOUT_PERIC1_IPCLK_9                29
 #define CLK_GOUT_PERIC1_IPCLK_10       30
-#define CLK_GOUT_PERIC1_IPCLK_11       30
-#define CLK_GOUT_PERIC1_PCLK_0         31
-#define CLK_GOUT_PERIC1_PCLK_1         32
-#define CLK_GOUT_PERIC1_PCLK_2         33
-#define CLK_GOUT_PERIC1_PCLK_3         34
-#define CLK_GOUT_PERIC1_PCLK_4         35
-#define CLK_GOUT_PERIC1_PCLK_5         36
-#define CLK_GOUT_PERIC1_PCLK_6         37
-#define CLK_GOUT_PERIC1_PCLK_7         38
-#define CLK_GOUT_PERIC1_PCLK_8         39
-#define CLK_GOUT_PERIC1_PCLK_9         40
-#define CLK_GOUT_PERIC1_PCLK_10                41
-#define CLK_GOUT_PERIC1_PCLK_11                42
+#define CLK_GOUT_PERIC1_IPCLK_11       31
+#define CLK_GOUT_PERIC1_PCLK_0         32
+#define CLK_GOUT_PERIC1_PCLK_1         33
+#define CLK_GOUT_PERIC1_PCLK_2         34
+#define CLK_GOUT_PERIC1_PCLK_3         35
+#define CLK_GOUT_PERIC1_PCLK_4         36
+#define CLK_GOUT_PERIC1_PCLK_5         37
+#define CLK_GOUT_PERIC1_PCLK_6         38
+#define CLK_GOUT_PERIC1_PCLK_7         39
+#define CLK_GOUT_PERIC1_PCLK_8         40
+#define CLK_GOUT_PERIC1_PCLK_9         41
+#define CLK_GOUT_PERIC1_PCLK_10                42
+#define CLK_GOUT_PERIC1_PCLK_11                43
 
-#define PERIC1_NR_CLK                  43
+#define PERIC1_NR_CLK                  44
 
 /* CMU_PERIS */
 #define CLK_MOUT_PERIS_BUS_USER                1