drm/amd/display: Update DCN32 to use new SR latencies
authorAlvin Lee <Alvin.Lee2@amd.com>
Tue, 13 Sep 2022 15:06:31 +0000 (11:06 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 27 Sep 2022 21:55:11 +0000 (17:55 -0400)
[Description]
Update to new SR latencies for DCN32

Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

index f43686997917f2868594ae269b20fd588c7d973f..c3cc068762103df7110865857d5f2ca0193c0b4d 100644 (file)
@@ -121,8 +121,8 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_2_soc = {
                },
        },
        .num_states = 1,
-       .sr_exit_time_us = 20.16,
-       .sr_enter_plus_exit_time_us = 27.13,
+       .sr_exit_time_us = 42.97,
+       .sr_enter_plus_exit_time_us = 49.94,
        .sr_exit_z8_time_us = 285.0,
        .sr_enter_plus_exit_z8_time_us = 320,
        .writeback_latency_us = 12.0,