clk: renesas: r9a07g044: Add POEG clock and reset entries

Add POEG clock and reset entries to CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220510110653.7326-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index cd2777abd957158e3edabf7ef3423b674ddfefb9..fd7c4eecd39870138fca5209fdb7347dc7ef1ae2 100644 (file)
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -182,7 +182,7 @@ static const struct {
 };
 
 static const struct {
-       struct rzg2l_mod_clk common[72];
+       struct rzg2l_mod_clk common[76];
 #ifdef CONFIG_CLK_R9A07G054
        struct rzg2l_mod_clk drp[0];
 #endif
@@ -206,6 +206,14 @@ static const struct {
                                        0x534, 2),
                DEF_MOD("gpt_pclk",     R9A07G044_GPT_PCLK, R9A07G044_CLK_P0,
                                        0x540, 0),
+               DEF_MOD("poeg_a_clkp",  R9A07G044_POEG_A_CLKP, R9A07G044_CLK_P0,
+                                       0x544, 0),
+               DEF_MOD("poeg_b_clkp",  R9A07G044_POEG_B_CLKP, R9A07G044_CLK_P0,
+                                       0x544, 1),
+               DEF_MOD("poeg_c_clkp",  R9A07G044_POEG_C_CLKP, R9A07G044_CLK_P0,
+                                       0x544, 2),
+               DEF_MOD("poeg_d_clkp",  R9A07G044_POEG_D_CLKP, R9A07G044_CLK_P0,
+                                       0x544, 3),
                DEF_MOD("wdt0_pclk",    R9A07G044_WDT0_PCLK, R9A07G044_CLK_P0,
                                        0x548, 0),
                DEF_MOD("wdt0_clk",     R9A07G044_WDT0_CLK, R9A07G044_OSCCLK,
@@ -349,6 +357,10 @@ static struct rzg2l_reset r9a07g044_resets[] = {
        DEF_RST(R9A07G044_OSTM1_PRESETZ, 0x834, 1),
        DEF_RST(R9A07G044_OSTM2_PRESETZ, 0x834, 2),
        DEF_RST(R9A07G044_GPT_RST_C, 0x840, 0),
+       DEF_RST(R9A07G044_POEG_A_RST, 0x844, 0),
+       DEF_RST(R9A07G044_POEG_B_RST, 0x844, 1),
+       DEF_RST(R9A07G044_POEG_C_RST, 0x844, 2),
+       DEF_RST(R9A07G044_POEG_D_RST, 0x844, 3),
        DEF_RST(R9A07G044_WDT0_PRESETN, 0x848, 0),
        DEF_RST(R9A07G044_WDT1_PRESETN, 0x848, 1),
        DEF_RST(R9A07G044_WDT2_PRESETN, 0x848, 2),