iommu/vt-d: Rename cap_5lp_support to cap_fl5lp_support
authorYi Liu <yi.l.liu@intel.com>
Mon, 26 Sep 2022 13:15:27 +0000 (21:15 +0800)
committerJoerg Roedel <jroedel@suse.de>
Mon, 26 Sep 2022 13:52:25 +0000 (15:52 +0200)
This renaming better describes it is for first level page table (a.k.a
first stage page table since VT-d spec 3.4).

Signed-off-by: Yi Liu <yi.l.liu@intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
Link: https://lore.kernel.org/r/20220916071326.2223901-1-yi.l.liu@intel.com
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
drivers/iommu/intel/cap_audit.c
drivers/iommu/intel/iommu.c
drivers/iommu/intel/iommu.h
drivers/iommu/intel/pasid.c
drivers/iommu/intel/svm.c

index 3ee68393122ffe3b40123c90af7fe562a35ab58e..806986696841405af1c235c686722b801d919a6f 100644 (file)
@@ -37,7 +37,7 @@ static inline void check_dmar_capabilities(struct intel_iommu *a,
        MINIMAL_FEATURE_IOMMU(b, ecap, ECAP_MHMV_MASK);
        MINIMAL_FEATURE_IOMMU(b, ecap, ECAP_IRO_MASK);
 
-       CHECK_FEATURE_MISMATCH(a, b, cap, 5lp_support, CAP_FL5LP_MASK);
+       CHECK_FEATURE_MISMATCH(a, b, cap, fl5lp_support, CAP_FL5LP_MASK);
        CHECK_FEATURE_MISMATCH(a, b, cap, fl1gp_support, CAP_FL1GP_MASK);
        CHECK_FEATURE_MISMATCH(a, b, cap, read_drain, CAP_RD_MASK);
        CHECK_FEATURE_MISMATCH(a, b, cap, write_drain, CAP_WD_MASK);
@@ -84,7 +84,7 @@ static int cap_audit_hotplug(struct intel_iommu *iommu, enum cap_audit_type type
                goto out;
        }
 
-       CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, cap, 5lp_support, CAP_FL5LP_MASK);
+       CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, cap, fl5lp_support, CAP_FL5LP_MASK);
        CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, cap, fl1gp_support, CAP_FL1GP_MASK);
        CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, cap, read_drain, CAP_RD_MASK);
        CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, cap, write_drain, CAP_WD_MASK);
index af17177b6d76608d9ad9251eb9042f39f59616c8..7410d6232cbbe70355970b32abcd8d06a746517d 100644 (file)
@@ -404,7 +404,7 @@ static unsigned long __iommu_calculate_sagaw(struct intel_iommu *iommu)
 {
        unsigned long fl_sagaw, sl_sagaw;
 
-       fl_sagaw = BIT(2) | (cap_5lp_support(iommu->cap) ? BIT(3) : 0);
+       fl_sagaw = BIT(2) | (cap_fl5lp_support(iommu->cap) ? BIT(3) : 0);
        sl_sagaw = cap_sagaw(iommu->cap);
 
        /* Second level only. */
index 8f29a183467ddbddab0659f337d7cff79a0b19a7..99cc75ecac6348445a0275baeba1c1742bd579de 100644 (file)
 /*
  * Decoding Capability Register
  */
-#define cap_5lp_support(c)     (((c) >> 60) & 1)
+#define cap_fl5lp_support(c)   (((c) >> 60) & 1)
 #define cap_pi_support(c)      (((c) >> 59) & 1)
 #define cap_fl1gp_support(c)   (((c) >> 56) & 1)
 #define cap_read_drain(c)      (((c) >> 55) & 1)
index ccaf329492542d8313091849a062c0609b389a3e..c30ddac40ee5fc2d5ce79cc1353854959bf5a998 100644 (file)
@@ -519,7 +519,7 @@ int intel_pasid_setup_first_level(struct intel_iommu *iommu,
                }
        }
 
-       if ((flags & PASID_FLAG_FL5LP) && !cap_5lp_support(iommu->cap)) {
+       if ((flags & PASID_FLAG_FL5LP) && !cap_fl5lp_support(iommu->cap)) {
                pr_err("No 5-level paging support for first-level on %s\n",
                       iommu->name);
                return -EINVAL;
index d1cab931dcb01e09b0b120fa721c2d8efb3ad7b0..7d08eb034f2d2e2bfb72d2a1f69b48fcc0a46a11 100644 (file)
@@ -164,7 +164,7 @@ void intel_svm_check(struct intel_iommu *iommu)
        }
 
        if (cpu_feature_enabled(X86_FEATURE_LA57) &&
-           !cap_5lp_support(iommu->cap)) {
+           !cap_fl5lp_support(iommu->cap)) {
                pr_err("%s SVM disabled, incompatible paging mode\n",
                       iommu->name);
                return;