#define GLINT_DYN_CTL_ITR_INDX_M               ICE_M(0x3, 3)
 #define GLINT_DYN_CTL_INTERVAL_S               5
 #define GLINT_DYN_CTL_INTERVAL_M               ICE_M(0xFFF, 5)
+#define GLINT_DYN_CTL_SW_ITR_INDX_ENA_M                BIT(24)
 #define GLINT_DYN_CTL_SW_ITR_INDX_M            ICE_M(0x3, 25)
 #define GLINT_DYN_CTL_WB_ON_ITR_M              BIT(30)
 #define GLINT_DYN_CTL_INTENA_MSK_M             BIT(31)
 
 static void ice_update_ena_itr(struct ice_q_vector *q_vector)
 {
        struct ice_vsi *vsi = q_vector->vsi;
+       bool wb_en = q_vector->wb_on_itr;
        u32 itr_val;
 
        if (test_bit(ICE_DOWN, vsi->state))
        /* When exiting WB_ON_ITR, let ITR resume its normal
         * interrupts-enabled path.
         */
-       if (q_vector->wb_on_itr)
+       if (wb_en)
                q_vector->wb_on_itr = false;
 
        /* This will do nothing if dynamic updates are not enabled. */
 
        /* net_dim() updates ITR out-of-band using a work item */
        itr_val = ice_buildreg_itr(ICE_ITR_NONE, 0);
+       /* trigger an immediate software interrupt when exiting
+        * busy poll, to make sure to catch any pending cleanups
+        * that might have been missed due to interrupt state
+        * transition.
+        */
+       if (wb_en) {
+               itr_val |= GLINT_DYN_CTL_SWINT_TRIG_M |
+                          GLINT_DYN_CTL_SW_ITR_INDX_M |
+                          GLINT_DYN_CTL_SW_ITR_INDX_ENA_M;
+       }
        wr32(&vsi->back->hw, GLINT_DYN_CTL(q_vector->reg_idx), itr_val);
 }