arm64: mops: detect and enable FEAT_MOPS
authorKristina Martsenko <kristina.martsenko@arm.com>
Tue, 9 May 2023 14:22:33 +0000 (15:22 +0100)
committerCatalin Marinas <catalin.marinas@arm.com>
Mon, 5 Jun 2023 16:05:41 +0000 (17:05 +0100)
The Arm v8.8/9.3 FEAT_MOPS feature provides new instructions that
perform a memory copy or set. Wire up the cpufeature code to detect the
presence of FEAT_MOPS and enable it.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com>
Link: https://lore.kernel.org/r/20230509142235.3284028-10-kristina.martsenko@arm.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Documentation/arm64/cpu-feature-registers.rst
Documentation/arm64/elf_hwcaps.rst
arch/arm64/include/asm/hwcap.h
arch/arm64/include/uapi/asm/hwcap.h
arch/arm64/kernel/cpufeature.c
arch/arm64/kernel/cpuinfo.c
arch/arm64/tools/cpucaps

index c7adc7897df606a6ed07114e42e7480bddf70f91..4e4625f2455fe92552365fc1c088d497bdef5a55 100644 (file)
@@ -288,6 +288,8 @@ infrastructure:
      +------------------------------+---------+---------+
      | Name                         |  bits   | visible |
      +------------------------------+---------+---------+
+     | MOPS                         | [19-16] |    y    |
+     +------------------------------+---------+---------+
      | RPRES                        | [7-4]   |    y    |
      +------------------------------+---------+---------+
      | WFXT                         | [3-0]   |    y    |
index 83e57e4d38e2a49d5bf63748c8b6e6dcfe10e8c5..8f847d0dcf57b2154882ad5c0420d39ba0c13483 100644 (file)
@@ -302,6 +302,9 @@ HWCAP2_SMEB16B16
 HWCAP2_SMEF16F16
     Functionality implied by ID_AA64SMFR0_EL1.F16F16 == 0b1
 
+HWCAP2_MOPS
+    Functionality implied by ID_AA64ISAR2_EL1.MOPS == 0b0001.
+
 4. Unused AT_HWCAP bits
 -----------------------
 
index 5d45f19fda7f5f39fbcbb28628778ab5987d8374..692b1ec663b279cb261f367a32b1028c33632cd4 100644 (file)
 #define KERNEL_HWCAP_SME_BI32I32       __khwcap2_feature(SME_BI32I32)
 #define KERNEL_HWCAP_SME_B16B16                __khwcap2_feature(SME_B16B16)
 #define KERNEL_HWCAP_SME_F16F16                __khwcap2_feature(SME_F16F16)
+#define KERNEL_HWCAP_MOPS              __khwcap2_feature(MOPS)
 
 /*
  * This yields a mask that user programs can use to figure out what
index 69a4fb749c65d42197a7696a93756eb861caf227..a2cac4305b1e0b48581f816af8bb7339dd7c1cd4 100644 (file)
 #define HWCAP2_SME_BI32I32     (1UL << 40)
 #define HWCAP2_SME_B16B16      (1UL << 41)
 #define HWCAP2_SME_F16F16      (1UL << 42)
+#define HWCAP2_MOPS            (1UL << 43)
 
 #endif /* _UAPI__ASM_HWCAP_H */
index 9898ad77b1dbab464a327a60f9b613d5340bb104..3badc4fa71541a37374c8151776a6121d1af8b57 100644 (file)
@@ -223,6 +223,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar2[] = {
        ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, 0),
        ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, 0),
        ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_MOPS_SHIFT, 4, 0),
        ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
                       FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0),
        ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
@@ -2187,6 +2188,11 @@ static void cpu_enable_dit(const struct arm64_cpu_capabilities *__unused)
        set_pstate_dit(1);
 }
 
+static void cpu_enable_mops(const struct arm64_cpu_capabilities *__unused)
+{
+       sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_MSCEn);
+}
+
 /* Internal helper functions to match cpu capability type */
 static bool
 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap)
@@ -2649,6 +2655,14 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
                .cpu_enable = cpu_enable_dit,
                ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, DIT, IMP)
        },
+       {
+               .desc = "Memory Copy and Memory Set instructions",
+               .capability = ARM64_HAS_MOPS,
+               .type = ARM64_CPUCAP_SYSTEM_FEATURE,
+               .matches = has_cpuid_feature,
+               .cpu_enable = cpu_enable_mops,
+               ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, MOPS, IMP)
+       },
        {},
 };
 
@@ -2777,6 +2791,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
        HWCAP_CAP(ID_AA64ISAR2_EL1, RPRFM, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRFM),
        HWCAP_CAP(ID_AA64ISAR2_EL1, RPRES, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRES),
        HWCAP_CAP(ID_AA64ISAR2_EL1, WFxT, IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT),
+       HWCAP_CAP(ID_AA64ISAR2_EL1, MOPS, IMP, CAP_HWCAP, KERNEL_HWCAP_MOPS),
 #ifdef CONFIG_ARM64_SME
        HWCAP_CAP(ID_AA64PFR1_EL1, SME, IMP, CAP_HWCAP, KERNEL_HWCAP_SME),
        HWCAP_CAP(ID_AA64SMFR0_EL1, FA64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64),
index eb4378c23b3c3ed13287cb8df2b4f89987c4f6c2..076a124255d0e9609733982b6dcc04316312e84a 100644 (file)
@@ -125,6 +125,7 @@ static const char *const hwcap_str[] = {
        [KERNEL_HWCAP_SME_BI32I32]      = "smebi32i32",
        [KERNEL_HWCAP_SME_B16B16]       = "smeb16b16",
        [KERNEL_HWCAP_SME_F16F16]       = "smef16f16",
+       [KERNEL_HWCAP_MOPS]             = "mops",
 };
 
 #ifdef CONFIG_COMPAT
index e1de10fa080e0ae9488b4f9aa7bb3d7b129c0600..debc4609f129aea7a52e2a85f7a7e3291bd40399 100644 (file)
@@ -35,6 +35,7 @@ HAS_GIC_PRIO_RELAXED_SYNC
 HAS_HCX
 HAS_LDAPR
 HAS_LSE_ATOMICS
+HAS_MOPS
 HAS_NESTED_VIRT
 HAS_NO_FPSIMD
 HAS_NO_HW_PREFETCH