ASoC: cs42l42: Always configure both ASP TX channels
authorRichard Fitzgerald <rf@opensource.cirrus.com>
Fri, 15 Oct 2021 13:36:05 +0000 (14:36 +0100)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Thu, 18 Nov 2021 18:16:53 +0000 (19:16 +0100)
[ Upstream commit 6e6825801ab926360f7f4f2dbcfd107d5ab8f025 ]

An I2S frame always has two slots (left and right) even when sending
mono. The right channel (channel 2) of ASP TX will always have the
same bit width as the left channel and will always be on the high
phase of LRCLK.

The previous implementation always passed the field masks for both
channels to snd_soc_component_update_bits() but for mono the written value
only contained the settings for channel 1. The result was that for mono
channel 2 was set to 8-bit (which is an invalid configuration) with both
channels on the low phase of LRCLK.

Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com>
Fixes: 585e7079de0e ("ASoC: cs42l42: Add Capture Support")
Link: https://lore.kernel.org/r/20211015133619.4698-3-rf@opensource.cirrus.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
sound/soc/codecs/cs42l42.c

index 9a463ab54bddc6d74ca5cc6b4a3ab2963e11e069..4548dae7ed834c97264a0907987512616819bede 100644 (file)
@@ -853,11 +853,10 @@ static int cs42l42_pcm_hw_params(struct snd_pcm_substream *substream,
 
        switch(substream->stream) {
        case SNDRV_PCM_STREAM_CAPTURE:
-               if (channels == 2) {
-                       val |= CS42L42_ASP_TX_CH2_AP_MASK;
-                       val |= width << CS42L42_ASP_TX_CH2_RES_SHIFT;
-               }
-               val |= width << CS42L42_ASP_TX_CH1_RES_SHIFT;
+               /* channel 2 on high LRCLK */
+               val = CS42L42_ASP_TX_CH2_AP_MASK |
+                     (width << CS42L42_ASP_TX_CH2_RES_SHIFT) |
+                     (width << CS42L42_ASP_TX_CH1_RES_SHIFT);
 
                snd_soc_component_update_bits(component, CS42L42_ASP_TX_CH_AP_RES,
                                CS42L42_ASP_TX_CH1_AP_MASK | CS42L42_ASP_TX_CH2_AP_MASK |