i2c: mediatek: fixing the incorrect register offset

The reason for the modification here is that the previous
offset information is incorrect, OFFSET_DEBUGSTAT = 0xE4 is
the correct value.

Fixes: 25708278f810 ("i2c: mediatek: Add i2c support for MediaTek MT8183")
Signed-off-by: Kewei Xu <kewei.xu@mediatek.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: Qii Wang <qii.wang@mediatek.com>
Signed-off-by: Wolfram Sang <wsa@kernel.org>

diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
index 477480d1de6bd10054009114381429949465af1f..32518081b5a468ff8c9f235789781ed85f89ace5 100644 (file)
--- a/drivers/i2c/busses/i2c-mt65xx.c
+++ b/drivers/i2c/busses/i2c-mt65xx.c
@@ -193,7 +193,7 @@ static const u16 mt_i2c_regs_v2[] = {
        [OFFSET_CLOCK_DIV] = 0x48,
        [OFFSET_SOFTRESET] = 0x50,
        [OFFSET_SCL_MIS_COMP_POINT] = 0x90,
-       [OFFSET_DEBUGSTAT] = 0xe0,
+       [OFFSET_DEBUGSTAT] = 0xe4,
        [OFFSET_DEBUGCTRL] = 0xe8,
        [OFFSET_FIFO_STAT] = 0xf4,
        [OFFSET_FIFO_THRESH] = 0xf8,