drm/amdgpu: move out asic specific definition from common header
authorJames Zhu <James.Zhu@amd.com>
Sat, 4 Dec 2021 17:20:37 +0000 (12:20 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 4 May 2022 14:43:56 +0000 (10:43 -0400)
Move out asic specific definition from common header.

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

index 5f7da4c19822621b3141310b0c0031b61f0e127b..912ead2e5bc80450547e8a85405cdc29de26fe38 100644 (file)
@@ -65,8 +65,6 @@
 #define VCN_ENC_CMD_REG_WRITE          0x0000000b
 #define VCN_ENC_CMD_REG_WAIT           0x0000000c
 
-#define VCN_VID_SOC_ADDRESS_2_0        0x1fa00
-#define VCN1_VID_SOC_ADDRESS_3_0       0x48200
 #define VCN_AON_SOC_ADDRESS_2_0        0x1f800
 #define VCN1_AON_SOC_ADDRESS_3_0       0x48000
 #define VCN_VID_IP_ADDRESS_2_0         0x0
index 8421044d562947b1b56fc6d5db2f80beab37b19e..08871bad9994a25888787a5d0c0997b431067180 100644 (file)
@@ -37,6 +37,9 @@
 #include "vcn/vcn_2_0_0_sh_mask.h"
 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
 
+#define VCN_VID_SOC_ADDRESS_2_0                                        0x1fa00
+#define VCN1_VID_SOC_ADDRESS_3_0                               0x48200
+
 #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET                       0x1fd
 #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET                   0x503
 #define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET                 0x504
index 9352d07539b931a163880dc105a14d4dbabb8f53..abf5ea23896267fdba9c6afda6342b084dd1d466 100644 (file)
@@ -37,6 +37,9 @@
 #include "vcn/vcn_2_5_sh_mask.h"
 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
 
+#define VCN_VID_SOC_ADDRESS_2_0                                        0x1fa00
+#define VCN1_VID_SOC_ADDRESS_3_0                               0x48200
+
 #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET                       0x27
 #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET                   0x0f
 #define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET                 0x10
index 930d3bcbb3e4052b37d28e3c74a3aa76b08fbd7c..c7280ca5e836092decc9f66a1f609b7b57a526c5 100644 (file)
@@ -37,6 +37,9 @@
 
 #include <drm/drm_drv.h>
 
+#define VCN_VID_SOC_ADDRESS_2_0                                        0x1fa00
+#define VCN1_VID_SOC_ADDRESS_3_0                               0x48200
+
 #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET                       0x27
 #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET                   0x0f
 #define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET                 0x10