MIPS: Loongson: update cpu-feature-overrides.h

Loongson doesn't support MIPSR2, therefore, MIPSR2 vectored interrupts
(cpu_has_vint) and MIPSR2 external interrupt controller mode
(cpu_has_veic) are 0.

Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com>
Cc: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: http://patchwork.linux-mips.org/patch/1112/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
index 16210cedd929870b97017ab33bc8c8309094ed8c..675bd8641d5a1efc0df38c258d7343c5eddcdb1e 100644 (file)
--- a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
@@ -52,6 +52,8 @@
 #define cpu_has_tx39_cache     0
 #define cpu_has_userlocal      0
 #define cpu_has_vce            0
+#define cpu_has_veic           0
+#define cpu_has_vint           0
 #define cpu_has_vtag_icache    0
 #define cpu_has_watch          1