i2c: octeon: Handle watchdog timeout

Add watchdog timeout handling to cater to the unhandled warnings
seen during validation on boards with different I2C slaves.
This status code reflects the state that controller couldn't
receive any response from slave while being in non-idle state
and HW recommends to reset before any further bus access.

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Signed-off-by: Piyush Malgujar <pmalgujar@marvell.com>
Acked-by: Andi Shyti <andi.shyti@kernel.org>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>

diff --git a/drivers/i2c/busses/i2c-octeon-core.c b/drivers/i2c/busses/i2c-octeon-core.c
index 76a5ec100d3039b840ba28ae7a817da447923d4f..5b7b942141e725c7f9071c217c728efce067cee6 100644 (file)
--- a/drivers/i2c/busses/i2c-octeon-core.c
+++ b/drivers/i2c/busses/i2c-octeon-core.c
@@ -182,6 +182,7 @@ static int octeon_i2c_hlc_wait(struct octeon_i2c *i2c)
 static int octeon_i2c_check_status(struct octeon_i2c *i2c, int final_read)
 {
        u8 stat;
+       u64 mode;
 
        /*
         * This is ugly... in HLC mode the status is not in the status register
@@ -244,6 +245,13 @@ static int octeon_i2c_check_status(struct octeon_i2c *i2c, int final_read)
        case STAT_RXADDR_NAK:
        case STAT_AD2W_NAK:
                return -ENXIO;
+
+       case STAT_WDOG_TOUT:
+               mode = __raw_readq(i2c->twsi_base + OCTEON_REG_MODE(i2c));
+               /* Set BUS_MON_RST to reset bus monitor */
+               mode |= BUS_MON_RST_MASK;
+               octeon_i2c_writeq_flush(mode, i2c->twsi_base + OCTEON_REG_MODE(i2c));
+               return -EIO;
        default:
                dev_err(i2c->dev, "unhandled state: %d\n", stat);
                return -EIO;

diff --git a/drivers/i2c/busses/i2c-octeon-core.h b/drivers/i2c/busses/i2c-octeon-core.h
index 39481e23e36fad098cf72dfd764e368e778f2840..7af01864da7522fc9485511e1feb184e8659c74f 100644 (file)
--- a/drivers/i2c/busses/i2c-octeon-core.h
+++ b/drivers/i2c/busses/i2c-octeon-core.h
@@ -73,6 +73,7 @@
 #define STAT_SLAVE_ACK         0xC8
 #define STAT_AD2W_ACK          0xD0
 #define STAT_AD2W_NAK          0xD8
+#define STAT_WDOG_TOUT         0xF0
 #define STAT_IDLE              0xF8
 
 /* TWSI_INT values */
@@ -107,6 +108,9 @@ struct octeon_i2c_reg_offset {
 #define TWSX_MODE_HS_MODE      BIT(0)
 #define TWSX_MODE_HS_MASK      (TWSX_MODE_REFCLK_SRC | TWSX_MODE_HS_MODE)
 
+/* Set BUS_MON_RST to reset bus monitor */
+#define BUS_MON_RST_MASK       BIT(3)
+
 struct octeon_i2c {
        wait_queue_head_t queue;
        struct i2c_adapter adap;