drm/xe: Add LRC parsing for more GPU instructions
authorMatt Roper <matthew.d.roper@intel.com>
Thu, 22 Feb 2024 18:40:08 +0000 (10:40 -0800)
committerMatt Roper <matthew.d.roper@intel.com>
Thu, 29 Feb 2024 20:39:16 +0000 (12:39 -0800)
The LRCs on some of our newer platforms appear to contain a few GPU
instructions that weren't handled in our LRC parser.  Add the relevant
instruction names and opcodes so that our debugfs LRC dumps will
properly indicate what these are.

Bspec: 55866, 64848, 46931
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240222184009.6857-2-matthew.d.roper@intel.com
drivers/gpu/drm/xe/instructions/xe_gfx_state_commands.h [new file with mode: 0644]
drivers/gpu/drm/xe/instructions/xe_gfxpipe_commands.h
drivers/gpu/drm/xe/instructions/xe_instr_defs.h
drivers/gpu/drm/xe/xe_lrc.c

diff --git a/drivers/gpu/drm/xe/instructions/xe_gfx_state_commands.h b/drivers/gpu/drm/xe/instructions/xe_gfx_state_commands.h
new file mode 100644 (file)
index 0000000..dca62af
--- /dev/null
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2024 Intel Corporation
+ */
+
+#ifndef _XE_GFX_STATE_COMMANDS_H_
+#define _XE_GFX_STATE_COMMANDS_H_
+
+#include "instructions/xe_instr_defs.h"
+
+#define GFX_STATE_OPCODE                       REG_GENMASK(28, 26)
+
+#define GFX_STATE_CMD(opcode) \
+       (XE_INSTR_GFX_STATE | REG_FIELD_PREP(GFX_STATE_OPCODE, opcode))
+
+#define STATE_WRITE_INLINE                     GFX_STATE_CMD(0x0)
+
+#endif
index 8e6dd061f2aea29040ce866dd29725ee8d23b05c..31d28a67ef6a314a456a956711720860743fd6f1 100644 (file)
@@ -47,6 +47,8 @@
 #define GPGPU_CSR_BASE_ADDRESS                 GFXPIPE_COMMON_CMD(0x1, 0x4)
 #define STATE_COMPUTE_MODE                     GFXPIPE_COMMON_CMD(0x1, 0x5)
 #define CMD_3DSTATE_BTD                                GFXPIPE_COMMON_CMD(0x1, 0x6)
+#define STATE_SYSTEM_MEM_FENCE_ADDRESS         GFXPIPE_COMMON_CMD(0x1, 0x9)
+#define STATE_CONTEXT_DATA_BASE_ADDRESS                GFXPIPE_COMMON_CMD(0x1, 0xB)
 
 #define CMD_3DSTATE_VF_STATISTICS              GFXPIPE_SINGLE_DW_CMD(0x0, 0xB)
 
@@ -71,6 +73,7 @@
 #define CMD_3DSTATE_WM                         GFXPIPE_3D_CMD(0x0, 0x14)
 #define CMD_3DSTATE_CONSTANT_VS                        GFXPIPE_3D_CMD(0x0, 0x15)
 #define CMD_3DSTATE_CONSTANT_GS                        GFXPIPE_3D_CMD(0x0, 0x16)
+#define CMD_3DSTATE_CONSTANT_PS                        GFXPIPE_3D_CMD(0x0, 0x17)
 #define CMD_3DSTATE_SAMPLE_MASK                        GFXPIPE_3D_CMD(0x0, 0x18)
 #define CMD_3DSTATE_CONSTANT_HS                        GFXPIPE_3D_CMD(0x0, 0x19)
 #define CMD_3DSTATE_CONSTANT_DS                        GFXPIPE_3D_CMD(0x0, 0x1A)
index 04179b2a48e1159190fd543afe77ccc4efcab3ac..fd2ce7ace5108f68e61387241a6ef75310fcf4ac 100644 (file)
@@ -17,6 +17,7 @@
 #define   XE_INSTR_MI                  REG_FIELD_PREP(XE_INSTR_CMD_TYPE, 0x0)
 #define   XE_INSTR_GSC                 REG_FIELD_PREP(XE_INSTR_CMD_TYPE, 0x2)
 #define   XE_INSTR_GFXPIPE             REG_FIELD_PREP(XE_INSTR_CMD_TYPE, 0x3)
+#define   XE_INSTR_GFX_STATE           REG_FIELD_PREP(XE_INSTR_CMD_TYPE, 0x4)
 
 /*
  * Most (but not all) instructions have a "length" field in the instruction
index 7ad853b0788af4c5d76411e66cd9d952263918c1..6c675d1bcb5771388b577e2d73a06e338185f643 100644 (file)
@@ -7,6 +7,7 @@
 
 #include "instructions/xe_mi_commands.h"
 #include "instructions/xe_gfxpipe_commands.h"
+#include "instructions/xe_gfx_state_commands.h"
 #include "regs/xe_engine_regs.h"
 #include "regs/xe_gpu_commands.h"
 #include "regs/xe_lrc_layout.h"
@@ -1037,6 +1038,8 @@ static int dump_gfxpipe_command(struct drm_printer *p,
        MATCH(GPGPU_CSR_BASE_ADDRESS);
        MATCH(STATE_COMPUTE_MODE);
        MATCH3D(3DSTATE_BTD);
+       MATCH(STATE_SYSTEM_MEM_FENCE_ADDRESS);
+       MATCH(STATE_CONTEXT_DATA_BASE_ADDRESS);
 
        MATCH3D(3DSTATE_VF_STATISTICS);
 
@@ -1061,6 +1064,7 @@ static int dump_gfxpipe_command(struct drm_printer *p,
        MATCH3D(3DSTATE_WM);
        MATCH3D(3DSTATE_CONSTANT_VS);
        MATCH3D(3DSTATE_CONSTANT_GS);
+       MATCH3D(3DSTATE_CONSTANT_PS);
        MATCH3D(3DSTATE_SAMPLE_MASK);
        MATCH3D(3DSTATE_CONSTANT_HS);
        MATCH3D(3DSTATE_CONSTANT_DS);
@@ -1153,6 +1157,31 @@ static int dump_gfxpipe_command(struct drm_printer *p,
        }
 }
 
+static int dump_gfx_state_command(struct drm_printer *p,
+                                 struct xe_gt *gt,
+                                 u32 *dw,
+                                 int remaining_dw)
+{
+       u32 numdw = instr_dw(*dw);
+       u32 opcode = REG_FIELD_GET(GFX_STATE_OPCODE, *dw);
+
+       /*
+        * Make sure we haven't mis-parsed a number of dwords that exceeds the
+        * remaining size of the LRC.
+        */
+       if (xe_gt_WARN_ON(gt, numdw > remaining_dw))
+               numdw = remaining_dw;
+
+       switch (*dw & (XE_INSTR_GFX_STATE | GFX_STATE_OPCODE)) {
+       MATCH(STATE_WRITE_INLINE);
+
+       default:
+               drm_printf(p, "[%#010x] unknown GFX_STATE command (opcode=%#x), likely %d dwords\n",
+                          *dw, opcode, numdw);
+               return numdw;
+       }
+}
+
 void xe_lrc_dump_default(struct drm_printer *p,
                         struct xe_gt *gt,
                         enum xe_engine_class hwe_class)
@@ -1177,6 +1206,8 @@ void xe_lrc_dump_default(struct drm_printer *p,
                        num_dw = dump_mi_command(p, gt, dw, remaining_dw);
                } else if ((*dw & XE_INSTR_CMD_TYPE) == XE_INSTR_GFXPIPE) {
                        num_dw = dump_gfxpipe_command(p, gt, dw, remaining_dw);
+               } else if ((*dw & XE_INSTR_CMD_TYPE) == XE_INSTR_GFX_STATE) {
+                       num_dw = dump_gfx_state_command(p, gt, dw, remaining_dw);
                } else {
                        num_dw = min(instr_dw(*dw), remaining_dw);
                        drm_printf(p, "[%#10x] Unknown instruction of type %#x, likely %d dwords\n",