MIPS: X1830: Add X1830 system type.

1.Add X1830 system type for cat /proc/cpuinfo to give out X1830.
2.Change "PRID_IMP_XBURST" to "PRID_IMP_XBURST_REV1" and add a
  new "PRID_IMP_XBURST_REV2" for new Ingenic CPUs which has
  XBurst with MXU2 SIMD ISA.

Notice:
1."PRID_IMP_XBURST_REV2" is corresponds to the latest XBurst
  processor with 128bit MXU2 SIMD instruction set, not the upcoming
  XBurst2 processor. This version of the processors fixes issues
  such as BTB and HPTLB.
2.In order to simplify and reuse the code, the "c->cputype" and
  the "c->writecombine" and the "__cpu_name[cpu]" in the original
  "PRID_IMP_XBURST" (now is "PRID_IMP_XBURST_REV1") are removed,
  and the corresponding settings are abtained through fall-through
  to "PRID_IMP_XBURST_REV2", which will cause the name that was
  previously mistakenly called "JZRISC" to become to the real name
  "XBurst".

Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Signed-off-by: Paul Burton <paulburton@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: yamada.masahiro@socionext.com
Cc: tglx@linutronix.de
Cc: chenhc@lemote.com
Cc: tbogendoerfer@suse.de
Cc: paul.burton@mips.com
Cc: paul@crapouillou.net
Cc: jhogan@kernel.org
Cc: fancer.lancer@gmail.com
Cc: ralf@linux-mips.org
Cc: jiaxun.yang@flygoat.com

diff --git a/arch/mips/include/asm/bootinfo.h b/arch/mips/include/asm/bootinfo.h
index d41a5057bc6950d808f441a19cd028cc83095978..61727785a247787136da20bb5db0b352575a03bc 100644 (file)
--- a/arch/mips/include/asm/bootinfo.h
+++ b/arch/mips/include/asm/bootinfo.h
@@ -81,6 +81,7 @@ enum loongson2ef_machine_type {
 #define  MACH_INGENIC_JZ4770   2       /* JZ4770 SOC           */
 #define  MACH_INGENIC_JZ4780   3       /* JZ4780 SOC           */
 #define  MACH_INGENIC_X1000            4       /* X1000 SOC            */
+#define  MACH_INGENIC_X1830            5       /* X1830 SOC            */
 
 extern char *system_type;
 const char *get_system_type(void);

diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index ea830783d6630279d633c02ca9900bceaeafda3e..0e10ffcf0c1b40ccacfedc31c9040b5c946295ac 100644 (file)
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -46,7 +46,7 @@
 #define PRID_COMP_NETLOGIC     0x0c0000
 #define PRID_COMP_CAVIUM       0x0d0000
 #define PRID_COMP_LOONGSON     0x140000
-#define PRID_COMP_INGENIC_D0   0xd00000        /* JZ4740, JZ4750 */
+#define PRID_COMP_INGENIC_D0   0xd00000        /* JZ4740, JZ4750, X1830 */
 #define PRID_COMP_INGENIC_D1   0xd10000        /* JZ4770, JZ4775, X1000 */
 #define PRID_COMP_INGENIC_E1   0xe10000        /* JZ4780 */
 
@@ -185,7 +185,8 @@
  * These are the PRID's for when 23:16 == PRID_COMP_INGENIC_*
  */
 
-#define PRID_IMP_XBURST               0x0200
+#define PRID_IMP_XBURST_REV1   0x0200  /* XBurst with MXU SIMD ISA             */
+#define PRID_IMP_XBURST_REV2   0x0100  /* XBurst with MXU2 SIMD ISA    */
 
 /*
  * These are the PRID's for when 23:16 == PRID_COMP_NETLOGIC

diff --git a/arch/mips/jz4740/setup.c b/arch/mips/jz4740/setup.c
index dc8ee21e0948ec1855e3df9e0ca5c82f38bc7309..880c26857affb1f16f2fcfe95775409bcb4513a4 100644 (file)
--- a/arch/mips/jz4740/setup.c
+++ b/arch/mips/jz4740/setup.c
@@ -44,6 +44,8 @@ static void __init jz4740_detect_mem(void)
 
 static unsigned long __init get_board_mach_type(const void *fdt)
 {
+       if (!fdt_node_check_compatible(fdt, 0, "ingenic,x1830"))
+               return MACH_INGENIC_X1830;
        if (!fdt_node_check_compatible(fdt, 0, "ingenic,x1000"))
                return MACH_INGENIC_X1000;
        if (!fdt_node_check_compatible(fdt, 0, "ingenic,jz4780"))
@@ -86,6 +88,8 @@ void __init device_tree_init(void)
 const char *get_system_type(void)
 {
        switch (mips_machtype) {
+       case MACH_INGENIC_X1830:
+               return "X1830";
        case MACH_INGENIC_X1000:
                return "X1000";
        case MACH_INGENIC_JZ4780:

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index c54332697673e0f92f2431bb6e42ed738343fe73..c06365404a8e72172329218f2c3fad7738b29c7a 100644 (file)
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -1960,10 +1960,8 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
        BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
 
        switch (c->processor_id & PRID_IMP_MASK) {
-       case PRID_IMP_XBURST:
-               c->cputype = CPU_XBURST;
-               c->writecombine = _CACHE_UNCACHED_ACCELERATED;
-               __cpu_name[cpu] = "Ingenic JZRISC";
+       case PRID_IMP_XBURST_REV1:
+
                /*
                 * The XBurst core by default attempts to avoid branch target
                 * buffer lookups by detecting & special casing loops. This
@@ -1971,34 +1969,43 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
                 * Set cp0 config7 bit 4 to disable this feature.
                 */
                set_c0_config7(MIPS_CONF7_BTB_LOOP_EN);
-               break;
-       default:
-               panic("Unknown Ingenic Processor ID!");
-               break;
-       }
 
-       switch (c->processor_id & PRID_COMP_MASK) {
-       /*
-        * The config0 register in the XBurst CPUs with a processor ID of
-        * PRID_COMP_INGENIC_D1 has an abandoned huge page tlb mode, this
-        * mode is not compatible with the MIPS standard, it will cause
-        * tlbmiss and into an infinite loop (line 21 in the tlb-funcs.S)
-        * when starting the init process. After chip reset, the default
-        * is HPTLB mode, Write 0xa9000000 to cp0 register 5 sel 4 to
-        * switch back to VTLB mode to prevent getting stuck.
-        */
-       case PRID_COMP_INGENIC_D1:
-               write_c0_page_ctrl(XBURST_PAGECTRL_HPTLB_DIS);
-               break;
-       /*
-        * The config0 register in the XBurst CPUs with a processor ID of
-        * PRID_COMP_INGENIC_D0 report themselves as MIPS32r2 compatible,
-        * but they don't actually support this ISA.
-        */
-       case PRID_COMP_INGENIC_D0:
-               c->isa_level &= ~MIPS_CPU_ISA_M32R2;
+               switch (c->processor_id & PRID_COMP_MASK) {
+
+               /*
+                * The config0 register in the XBurst CPUs with a processor ID of
+                * PRID_COMP_INGENIC_D0 report themselves as MIPS32r2 compatible,
+                * but they don't actually support this ISA.
+                */
+               case PRID_COMP_INGENIC_D0:
+                       c->isa_level &= ~MIPS_CPU_ISA_M32R2;
+                       break;
+
+               /*
+                * The config0 register in the XBurst CPUs with a processor ID of
+                * PRID_COMP_INGENIC_D1 has an abandoned huge page tlb mode, this
+                * mode is not compatible with the MIPS standard, it will cause
+                * tlbmiss and into an infinite loop (line 21 in the tlb-funcs.S)
+                * when starting the init process. After chip reset, the default
+                * is HPTLB mode, Write 0xa9000000 to cp0 register 5 sel 4 to
+                * switch back to VTLB mode to prevent getting stuck.
+                */
+               case PRID_COMP_INGENIC_D1:
+                       write_c0_page_ctrl(XBURST_PAGECTRL_HPTLB_DIS);
+                       break;
+
+               default:
+                       break;
+               }
+       /* fall-through */
+       case PRID_IMP_XBURST_REV2:
+               c->cputype = CPU_XBURST;
+               c->writecombine = _CACHE_UNCACHED_ACCELERATED;
+               __cpu_name[cpu] = "Ingenic XBurst";
                break;
+
        default:
+               panic("Unknown Ingenic Processor ID!");
                break;
        }
 }