crypto: qat - check MMP size before writing to the SRAM
authorJack Xu <jack.xu@intel.com>
Mon, 17 May 2021 09:13:13 +0000 (05:13 -0400)
committerHerbert Xu <herbert@gondor.apana.org.au>
Fri, 28 May 2021 06:20:40 +0000 (14:20 +0800)
Change "sram_visible" to "mmp_sram_size" and compare it with the MMP
size to prevent an overly large MMP file being written to SRAM.

Signed-off-by: Jack Xu <jack.xu@intel.com>
Co-developed-by: Zhehui Xiang <zhehui.xiang@intel.com>
Signed-off-by: Zhehui Xiang <zhehui.xiang@intel.com>
Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
drivers/crypto/qat/qat_common/icp_qat_fw_loader_handle.h
drivers/crypto/qat/qat_common/qat_hal.c
drivers/crypto/qat/qat_common/qat_uclo.c

index b8f3463be6ef4174276c55b5ff49107bc3a84b28..7eb5daef4f885dfca23a189ec026f0c5371080cb 100644 (file)
@@ -24,7 +24,7 @@ struct icp_qat_fw_loader_hal_handle {
 };
 
 struct icp_qat_fw_loader_chip_info {
-       bool sram_visible;
+       int mmp_sram_size;
        bool nn;
        bool lm2lm3;
        u32 lm_size;
index bd3028126cbe62020c3c16ac28fca70211633df8..ed9b813471443d4241b8817c92993f34ce4d0b51 100644 (file)
@@ -696,7 +696,7 @@ static int qat_hal_chip_init(struct icp_qat_fw_loader_handle *handle,
        handle->pci_dev = pci_info->pci_dev;
        switch (handle->pci_dev->device) {
        case ADF_4XXX_PCI_DEVICE_ID:
-               handle->chip_info->sram_visible = false;
+               handle->chip_info->mmp_sram_size = 0;
                handle->chip_info->nn = false;
                handle->chip_info->lm2lm3 = true;
                handle->chip_info->lm_size = ICP_QAT_UCLO_MAX_LMEM_REG_2X;
@@ -730,7 +730,7 @@ static int qat_hal_chip_init(struct icp_qat_fw_loader_handle *handle,
                break;
        case PCI_DEVICE_ID_INTEL_QAT_C62X:
        case PCI_DEVICE_ID_INTEL_QAT_C3XXX:
-               handle->chip_info->sram_visible = false;
+               handle->chip_info->mmp_sram_size = 0;
                handle->chip_info->nn = true;
                handle->chip_info->lm2lm3 = false;
                handle->chip_info->lm_size = ICP_QAT_UCLO_MAX_LMEM_REG;
@@ -763,7 +763,7 @@ static int qat_hal_chip_init(struct icp_qat_fw_loader_handle *handle,
                        + LOCAL_TO_XFER_REG_OFFSET);
                break;
        case PCI_DEVICE_ID_INTEL_QAT_DH895XCC:
-               handle->chip_info->sram_visible = true;
+               handle->chip_info->mmp_sram_size = 0x40000;
                handle->chip_info->nn = true;
                handle->chip_info->lm2lm3 = false;
                handle->chip_info->lm_size = ICP_QAT_UCLO_MAX_LMEM_REG;
@@ -800,7 +800,7 @@ static int qat_hal_chip_init(struct icp_qat_fw_loader_handle *handle,
                goto out_err;
        }
 
-       if (handle->chip_info->sram_visible) {
+       if (handle->chip_info->mmp_sram_size > 0) {
                sram_bar =
                        &pci_info->pci_bars[hw_data->get_sram_bar_id(hw_data)];
                handle->hal_sram_addr_v = sram_bar->virt_addr;
index d2c2db58c93ffdf5e9661e2954b56191cf8f8d39..8adf25769128a4000280e0496385866818262909 100644 (file)
@@ -1551,7 +1551,7 @@ int qat_uclo_wr_mimage(struct icp_qat_fw_loader_handle *handle,
                        status = qat_uclo_auth_fw(handle, desc);
                qat_uclo_ummap_auth_fw(handle, &desc);
        } else {
-               if (!handle->chip_info->sram_visible) {
+               if (handle->chip_info->mmp_sram_size < mem_size) {
                        dev_dbg(&handle->pci_dev->dev,
                                "QAT MMP fw not loaded for device 0x%x",
                                handle->pci_dev->device);