cxl/component_regs: Fix offset

The CXL.cache and CXL.mem registers begin after the CXL.io registers
which occupy the first 0x1000 bytes. The current code wasn't setting
this up properly for future users of the component registers. It was
correct for the probing code however.

Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Ira Weiny <ira.weiny@intel.com>
Fixes: 08422378c4ad ("cxl/pci: Add HDM decoder capabilities")
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/20210611051113.224328-1-ben.widawsky@intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>

diff --git a/drivers/cxl/core.c b/drivers/cxl/core.c
index b134b29923cad8deeba492b0349c699ddb811028..c613dc795498f99f4884b6c8aa7acee8f38997fa 100644 (file)
--- a/drivers/cxl/core.c
+++ b/drivers/cxl/core.c
@@ -599,7 +599,7 @@ void cxl_probe_component_regs(struct device *dev, void __iomem *base,
                        length = 0x20 * decoder_cnt + 0x10;
 
                        map->hdm_decoder.valid = true;
-                       map->hdm_decoder.offset = offset;
+                       map->hdm_decoder.offset = CXL_CM_OFFSET + offset;
                        map->hdm_decoder.size = length;
                        break;
                default: