riscv: dts: sophgo: add clock generator for Sophgo CV1800 series SoC

Add clock generator node for CV1800B and CV1812H.

Until now, It uses DT override to minimize duplication. This may
change in the future. See the last link for the discussion on
maintaining DT of CV1800 series.

Link: https://github.com/milkv-duo/duo-files/blob/6f4e9b8ecb459e017cca1a8df248a19ca70837a3/duo/datasheet/CV1800B-CV1801B-Preliminary-Datasheet-full-en.pdf
Link: https://lore.kernel.org/all/IA1PR20MB495373158F3B690EF3BF2901BB8BA@IA1PR20MB4953.namprd20.prod.outlook.com/
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Link: https://lore.kernel.org/r/IA1PR20MB4953ED6A4B57773865F49D6DBB262@IA1PR20MB4953.namprd20.prod.outlook.com
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>

diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
index 165e9e320a8c72d7f56ecb61fd86e7d58c8c4333..baf641829e726886a94e9fe1f8b26465096d201d 100644 (file)
--- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
@@ -16,3 +16,7 @@
 &clint {
        compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
 };
+
+&clk {
+       compatible = "sophgo,cv1800-clk";
+};

diff --git a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
index 3e7a942f5c1a5ac988291b0b2224ffc750ce86c7..7fa4c1e2d1da45ac705fcc0d4dd289e31a9b2a15 100644 (file)
--- a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
@@ -22,3 +22,7 @@
 &clint {
        compatible = "sophgo,cv1812h-clint", "thead,c900-clint";
 };
+
+&clk {
+       compatible = "sophgo,cv1810-clk";
+};

diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
index 405f4ba18392f127d6e00d921d4416c66158e386..c744c442304cf3f0560aa39d75cdad66b0c9f3ac 100644 (file)
--- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
@@ -61,6 +61,12 @@
                dma-noncoherent;
                ranges;
 
+               clk: clock-controller@3002000 {
+                       reg = <0x03002000 0x1000>;
+                       clocks = <&osc>;
+                       #clock-cells = <1>;
+               };
+
                gpio0: gpio@3020000 {
                        compatible = "snps,dw-apb-gpio";
                        reg = <0x3020000 0x1000>;