arm64: dts: imx93-11x11-evk: set SION for cmd and data pad of USDHC

imx93 pad integrate has one issue, refer to ERR052021:

ERR052021 uSDHC: Sometimes uSDHC does not work under VDD_SOC low
		 drive mode and nominal mode
Description:
uSDHC PADs have one integration issue.
When CMD/DATA lines direction change from output to input, uSDHC
controller begin sampling, the integration issue will make input
enable signal from uSDHC propagated to the PAD with a long delay,
thus the new input value on the pad comes to uSDHC lately. The
uSDHC sampled the old input value and the sampling result is wrong.

Workaround:
Set uSDHC CMD/DATA PADs iomux register SION bit to 1, then PADs will
propagate input to uSDHC with no delay, so correct value is sampled.

This issue will wrongly trigger the start bit when sample the USDHC
command response, cause the USDHC trigger command CRC/index/endbit
error, which will finally impact the tuning pass window, espically
will impact the standard tuning logic, and can't find a correct delay
cell to get the best timing.

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts
index 2b9d47716f750ce0ae5857422ecc3c5449128d17..021caf471bf6c943e8b41da3ef0c1f7e2009f976 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts
@@ -237,18 +237,19 @@
                >;
        };
 
+       /* need to config the SION for data and cmd pad, refer to ERR052021 */
        pinctrl_usdhc1: usdhc1grp {
                fsl,pins = <
                        MX93_PAD_SD1_CLK__USDHC1_CLK            0x15fe
-                       MX93_PAD_SD1_CMD__USDHC1_CMD            0x13fe
-                       MX93_PAD_SD1_DATA0__USDHC1_DATA0        0x13fe
-                       MX93_PAD_SD1_DATA1__USDHC1_DATA1        0x13fe
-                       MX93_PAD_SD1_DATA2__USDHC1_DATA2        0x13fe
-                       MX93_PAD_SD1_DATA3__USDHC1_DATA3        0x13fe
-                       MX93_PAD_SD1_DATA4__USDHC1_DATA4        0x13fe
-                       MX93_PAD_SD1_DATA5__USDHC1_DATA5        0x13fe
-                       MX93_PAD_SD1_DATA6__USDHC1_DATA6        0x13fe
-                       MX93_PAD_SD1_DATA7__USDHC1_DATA7        0x13fe
+                       MX93_PAD_SD1_CMD__USDHC1_CMD            0x400013fe
+                       MX93_PAD_SD1_DATA0__USDHC1_DATA0        0x400013fe
+                       MX93_PAD_SD1_DATA1__USDHC1_DATA1        0x400013fe
+                       MX93_PAD_SD1_DATA2__USDHC1_DATA2        0x400013fe
+                       MX93_PAD_SD1_DATA3__USDHC1_DATA3        0x400013fe
+                       MX93_PAD_SD1_DATA4__USDHC1_DATA4        0x400013fe
+                       MX93_PAD_SD1_DATA5__USDHC1_DATA5        0x400013fe
+                       MX93_PAD_SD1_DATA6__USDHC1_DATA6        0x400013fe
+                       MX93_PAD_SD1_DATA7__USDHC1_DATA7        0x400013fe
                        MX93_PAD_SD1_STROBE__USDHC1_STROBE      0x15fe
                >;
        };
@@ -265,14 +266,15 @@
                >;
        };
 
+       /* need to config the SION for data and cmd pad, refer to ERR052021 */
        pinctrl_usdhc2: usdhc2grp {
                fsl,pins = <
                        MX93_PAD_SD2_CLK__USDHC2_CLK            0x15fe
-                       MX93_PAD_SD2_CMD__USDHC2_CMD            0x13fe
-                       MX93_PAD_SD2_DATA0__USDHC2_DATA0        0x13fe
-                       MX93_PAD_SD2_DATA1__USDHC2_DATA1        0x13fe
-                       MX93_PAD_SD2_DATA2__USDHC2_DATA2        0x13fe
-                       MX93_PAD_SD2_DATA3__USDHC2_DATA3        0x13fe
+                       MX93_PAD_SD2_CMD__USDHC2_CMD            0x400013fe
+                       MX93_PAD_SD2_DATA0__USDHC2_DATA0        0x400013fe
+                       MX93_PAD_SD2_DATA1__USDHC2_DATA1        0x400013fe
+                       MX93_PAD_SD2_DATA2__USDHC2_DATA2        0x400013fe
+                       MX93_PAD_SD2_DATA3__USDHC2_DATA3        0x400013fe
                        MX93_PAD_SD2_VSELECT__USDHC2_VSELECT    0x51e
                >;
        };