perf/x86/intel/cstate: Add Grand Ridge support

The same as the Sierra Forest, the Grand Ridge supports core C1/C6 and
module C6. But it doesn't support pkg C6 residency counter.

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lore.kernel.org/r/20231116142245.1233485-4-kan.liang@linux.intel.com

diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
index 4a46ef315284621dc2f12cc59ee22c1356c77482..4b50a3a9818aec676d44da4db29fc5d4448757e1 100644 (file)
--- a/arch/x86/events/intel/cstate.c
+++ b/arch/x86/events/intel/cstate.c
@@ -41,7 +41,7 @@
  *     MSR_CORE_C1_RES: CORE C1 Residency Counter
  *                      perf code: 0x00
  *                      Available model: SLM,AMT,GLM,CNL,ICX,TNT,ADL,RPL
- *                                       MTL,SRF
+ *                                       MTL,SRF,GRR
  *                      Scope: Core (each processor core has a MSR)
  *     MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter
  *                            perf code: 0x01
@@ -52,7 +52,8 @@
  *                            perf code: 0x02
  *                            Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
  *                                             SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX,
- *                                             TGL,TNT,RKL,ADL,RPL,SPR,MTL,SRF
+ *                                             TGL,TNT,RKL,ADL,RPL,SPR,MTL,SRF,
+ *                                             GRR
  *                            Scope: Core
  *     MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter
  *                            perf code: 0x03
@@ -99,7 +100,7 @@
  *                            Scope: Package (physical package)
  *     MSR_MODULE_C6_RES_MS:  Module C6 Residency Counter.
  *                            perf code: 0x00
- *                            Available model: SRF
+ *                            Available model: SRF,GRR
  *                            Scope: A cluster of cores shared L2 cache
  *
  */
@@ -677,6 +678,13 @@ static const struct cstate_model glm_cstates __initconst = {
                                  BIT(PERF_CSTATE_PKG_C10_RES),
 };
 
+static const struct cstate_model grr_cstates __initconst = {
+       .core_events            = BIT(PERF_CSTATE_CORE_C1_RES) |
+                                 BIT(PERF_CSTATE_CORE_C6_RES),
+
+       .module_events          = BIT(PERF_CSTATE_MODULE_C6_RES),
+};
+
 static const struct cstate_model srf_cstates __initconst = {
        .core_events            = BIT(PERF_CSTATE_CORE_C1_RES) |
                                  BIT(PERF_CSTATE_CORE_C6_RES),
@@ -739,6 +747,7 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
        X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L,      &glm_cstates),
        X86_MATCH_INTEL_FAM6_MODEL(ATOM_GRACEMONT,      &adl_cstates),
        X86_MATCH_INTEL_FAM6_MODEL(ATOM_CRESTMONT_X,    &srf_cstates),
+       X86_MATCH_INTEL_FAM6_MODEL(ATOM_CRESTMONT,      &grr_cstates),
 
        X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L,           &icl_cstates),
        X86_MATCH_INTEL_FAM6_MODEL(ICELAKE,             &icl_cstates),