ARM: dts: at91: sama7g5: add nodes for video capture

Add node for the XISC (eXtended Image Sensor Controller) and CSI2DC
(csi2 demux controller).
These nodes represent the top level of the video capture hardware pipeline
and are directly connected in hardware.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220503095127.48710-4-eugen.hristev@microchip.com

diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi
index ab131762ecb58d99ec229333edcd0a1062183266..929ba73702e935acd74a859b745f3afbde5ad7e7 100644 (file)
--- a/arch/arm/boot/dts/sama7g5.dtsi
+++ b/arch/arm/boot/dts/sama7g5.dtsi
@@ -516,6 +516,57 @@
                        status = "disabled";
                };
 
+               csi2dc: csi2dc@e1404000 {
+                       compatible = "microchip,sama7g5-csi2dc";
+                       reg = <0xe1404000 0x500>;
+                       clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&xisc>;
+                       clock-names = "pclk", "scck";
+                       assigned-clocks = <&xisc>;
+                       assigned-clock-rates = <266000000>;
+                       status = "disabled";
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               port@0 {
+                                       reg = <0>;
+                                       csi2dc_in: endpoint {
+                                       };
+                               };
+
+                               port@1 {
+                                       reg = <1>;
+                                       csi2dc_out: endpoint {
+                                               bus-width = <14>;
+                                               hsync-active = <1>;
+                                               vsync-active = <1>;
+                                               remote-endpoint = <&xisc_in>;
+                                       };
+                               };
+                       };
+               };
+
+               xisc: xisc@e1408000 {
+                       compatible = "microchip,sama7g5-isc";
+                       reg = <0xe1408000 0x2000>;
+                       interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&pmc PMC_TYPE_PERIPHERAL 56>;
+                       clock-names = "hclock";
+                       #clock-cells = <0>;
+                       clock-output-names = "isc-mck";
+                       status = "disabled";
+
+                       port {
+                               xisc_in: endpoint {
+                                       bus-type = <5>; /* Parallel */
+                                       bus-width = <14>;
+                                       hsync-active = <1>;
+                                       vsync-active = <1>;
+                                       remote-endpoint = <&csi2dc_out>;
+                               };
+                       };
+               };
+
                pwm: pwm@e1604000 {
                        compatible = "microchip,sama7g5-pwm", "atmel,sama5d2-pwm";
                        reg = <0xe1604000 0x4000>;